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I would try the following change:
> process(clk, reset, TEMP_count(1), in_mca)
> variable temp : std_logic_vector(11 downto 0);
> begin
> if reset = '1' then
> out_mca <= "000000000000" ;
temp : = (others => '0'); -- Reset temp too.
> elsif rising_edge(clk) then
> temp(11 downto 0) := in_mca ;
> if TEMP_count(1) = '1' then
> temp := ("111111111111" xor temp)+1 ;
> end if;
out_mca <= temp; -- Assignment should be
here.
> end if;
-- out_mca <= temp ; Take this line out
> end process;
Antonio wrote:
>
> I've realized a circuit with the following behaviour :
>
> clk -> out_mca[11:0] = in_mca[11:0]
> clk -> out_mca[11:0] = in_mca[11:0]
> clk -> out_mca[11:0] = -in_mca[11:0]
> clk -> out_mca[11:0] = -in_mca[11:0]
>
> ....
>
> clk -> out_mca[11:0] = in_mca[11:0]
> clk -> out_mca[11:0] = in_mca[11:0]
> clk -> out_mca[11:0] = -in_mca[11:0]
> clk -> out_mca[11:0] = -in_mca[11:0]
>
> from Synplify I've a warning that I don't understand , it is :
>
> @W: mult_C2_adder.vhd(43): Feedback mux created for signal
> out_mca[11:0]. Did you forget the set/reset assignment for this
> signal?
>
> Can you help me to understand it, here's the code :
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_signed.all;
>
> entity mult_C2_adder is
> port(in_mca : in std_logic_vector(11 downto 0);
> reset : in std_logic ;
> clk : in std_logic ;
> out_mca : out std_logic_vector(11 downto 0));
> end mult_C2_adder;
>
> architecture mult_C2_adder_arch of mult_C2_adder is
> signal TEMP_count : std_logic_vector(1 downto 0);
> begin
>
> process(clk, reset)
> begin
> if reset = '1' then
> TEMP_count <= "11";
> elsif rising_edge(clk) then
> TEMP_count <= TEMP_count + 1;
> end if;
> end process;
>
>
> process(clk, reset, TEMP_count(1), in_mca)
> variable temp : std_logic_vector(11 downto 0);
> begin
> if reset = '1' then
> out_mca <= "000000000000" ;
> elsif rising_edge(clk) then
> temp(11 downto 0) := in_mca ;
> if TEMP_count(1) = '1' then
> temp := ("111111111111" xor temp)+1 ;
> end if;
> end if;
> out_mca <= temp ;
> end process;
>
> end mult_C2_adder_arch ;
--
Francisco Camarero
Hardware Engineer
---------------------------------------------
Acterna Zürich AG
Förrlibuckstrasse 62 / 3d floor
P.O. Box 74
CH - 8037 Zürich
GSM: +41 76 355 67 69
Fax: +41 1 355 65 05
---------------------------------------------
Article: 40026Dear Theron, Whilst the ISE environment does not understand an edif file, a vhdl 'black box' will result in a 'socket' into which the edif will be inserted during the translate stage. You will probably notice that after you translate the first time, you will have a file called kcpsm.ngo (probably in a sub directory). This is the edif translated into the internal format. BTW - I have just completed an all VHDL implementation of KCPSM-II which is specifically for Virtex-II (not suitable for Virtex(E) and Spartan-II). If anyone wants a copy, please drop me a direct email (chapman@xilinx.com). Yours sincerely, Ken ChapmanArticle: 40027
The obvious solution is to instantiate the control flop and give it whatever location attribute (LOC) you desire. Kevin Brace wrote > I am wondering if it is possible to have an output FF in an IOB, but a > tri-state control FF outside of an IOB in Xilinx Virtex family of FPGAs? > The reason I care about this is because I still need to keep output FF's > Tco (Tval) low (That's why I still want to use the IOB output FF.), but > want to use CLB's FF to handle output tri-state buffer control to > improve the setup time of the tri-state control FF. > I know that both FFs can be in a CLB, or inside an IOB, and I already > know how to do that.Article: 40028
Hi all, I have a design which uses say X no of XCV1000E FPGAs. I wud like to go for denser FPGAs ( XC2V6000). The total system gates in XCV1000E is approximately 1.5 Million while in XC2V6000 is 6 Million. So can I assume that the logic implemented in four (6/1.5) FPGAs can be implemented using a single XC2V6000 FPGAs? But the LUTs of the two looks different. Will this affect the beforesaid ratio? Or is there any other decisive factors involved? Ur reply will be most welcom with kind regs kingArticle: 40029
When analyzing unisims and simprims synopsys libraries (XilinX ISE4.1 +
Service Pack 3)
i get this message :
==> VITAL Entity 'DCM' has VITAL conformance error(s):
CLKFX : out std_ulogic := '0';
^
**Error: vhdlan,2264
/soft/xilinx_hd/M4.1i/vhdl/src/unisims/unisim_VITAL.vhd(9977
The port 'CLKFX' associated with timing generic 'TPW_CLKFX_POSEDGE'
must be
of mode InOut, Out or Buffer.
CLKFX : out std_ulogic := '0'
Can anyone here give me a suggestion?
Thanks.
Charles
Article: 40030The problem I'am having is the following: I'm working on a design which uses a cpld to configure the fpga in parallel mode. Additinally the cpld and the fpga are configurable true jtag. (they are connected in serial, FPGA-TDO connected to CPLD-TDI) When I try to configure the Spartan2 and a the cpld true jtag, there's no problem. When I replace the Spartan2 by a virtex-E, the Xilinx Impact tools do recognize the cpld but the Virtex-E remains invisible. When I try to configure the cpld, I get an error. Note that the Spartan2 and Virtex-E are almost completely pin-compatible (the ones that don't match are not used). I can change the applied Vccint Voltage to 2.5 V for the Spartan2 or 1.8V for the Virtex-E. Does anyone have an idea what could be wrong? Maybe there are some differences between the Spartan2 and the Virtex-E I didn't noticed? Am I forgetting something else? thanks in advance, Jo KenensArticle: 40031
Hello,
has anybody used an EDIF netlist in FPGA Express? The documentation tells
that it is possible to do so, but whenever I take an EDIF netlist (in my
case from ViewDraw) as source file and want to create an implementation
from it, there are no errors or warnings, but I cannot look at the
schematic and the EDIF netlist, that can be exported from FPGA Express is
nearly empty:
(edif NUR_EDIF
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0)
)
(status
(written
(timeStamp 2002 2 20 14 41 6)
(program "FPGA Express"
(version "3.3.1.4719")
)
(author "carsten")
)
)
(library DESIGNS
(edifLevel 0)
(technology
(numberDefinition)
)
(cell NUR_EDIF
(cellType GENERIC)
(view Netlist_representation
(viewType NETLIST)
(interface)
(contents)
)
)
)
(design NUR_EDIF
(cellRef NUR_EDIF
(libraryRef DESIGNS)
)
)
)
Can anybody send me a hint?
Thanks
Carste Heise
Article: 40032Think about it: When you access a BlockRAM, you have to perform adress decoding, 1 of at least 512, at most 16K. When you access a flip-flop, there is no decoding. Obviously, a BlockRAM is slower than a flip-flop, or even a LUTRAM. Peter Alfke =================== Antonio wrote: > Looking at this post with more attenction It comes to me a doubt, it > is about Ray affermation : > " The block RAMs have fairly long tsu, th and tco numbers compared > to the CLB flip-flop " > > but this means that if instead of block RAMs I use the ROM that XST > infer when I use a vhdl CASE , I can obtain a faster design ??Article: 40033
May you explain me why this is true also for a 4096x12 deep memory ??Article: 40034
2nS risetime? I thought most (performance) logic these days had sub-ns rise and fall times unless (for the FPGAs) you specify a slow slew rate which would give you unacceptable (?) delays for the 133MHz timing. The 1/6 factor seems like a nice rule of thumb but I'd worry more about hyperactive drivers doing funny things without good signal integrity design. If you *always* have the three memories on board, the capacitance will be uniform making the signal integrity issues a bit easier to deal with unlike SDRAM systems with one or many banks. Tuning the current drive of the FPGA to your situation may help balance the demands of the heavier capacitance - SDRAM clock, address, and control lines - and the lighter capacitance signals. It may be more of a mess than you expect. Good luck with the effort. - John_H rickman wrote: > Ray Andraka wrote: > > > > You should be able to pull it off, especially if pipeline latency is not an issue. We are > > doing a 133MHz SDRAM interface as part of a video processor in spartanII for a customer next > > month, and are not particularly worried about it. Make sure your board layout is good, and if > > driving more than one chip make sure the lines are properly terminated. If it is a single > > SDRAM on a private interface to the FPGA, you can get probably away without terminators if you > > are careful with the board layout and route. > > I was not aware that terminators were being used on SDRAM busses. This > will be a bus with both the DSP and the FPGA driving and three different > memories as slaves (Flash, SBSRAM and SDRAM). The one thing in my favor > is that the board is very small (PC/104, 4" x 4") and so the runs should > all be very short. My understanding is that I should be able to get > away with no terminators if the runs are kept shorter than 1/6 the rise > time. I believe I read that rule-of-thumb in one of Howard Johnson's > magazine articles. With a 2 nS rise time, I would have about 4" of run > before I had to start worrying about signal integrity. I will have to > pay close attention to this. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40035
Same reasoning. BTW, 4096 x 12 uses either 12 BlockRAMs in Virtex, or three BlockRAMs each 4Kx4 in Virtex-II. In general, doing something complicated tends to take more time than doing something simple. Can we agree on that? Peter Alfke ================= Antonio wrote: > May you explain me why this is true also for a 4096x12 deep > memory ??Article: 40036
Having come back to logic design after a 5 year break, I had a bit of a culture-shock with the myriad of different tools and their inherent strengths and weaknesses. I'm hoping to help make it a bit easier for others and expand my current limited understanding by creating a set of forums for discussion. My aim in creating the forums was: 1) Provide a forum for discussion of various programmable logic tools and how best to use them. 2) Provide a place to store tips and techniques used by programmable logic designers. 3) Complement the discussions on the main programmable logic newsgroups and perhaps go into more specific detail and provide more tutorial information to supplement the newsgroup information. 4) Provide an edited summary of valuable discussions on the newsgroups. At present I'd appreciate any comment and assistance in starting up the process. http://pub64.ezboard.com/bfpgatipsandtricks Because the forums are new I've focussed on Altera-based tools, but over the coming weeks if there is sufficient interest I'll attempt to extend them to other device toolsets. I should point out that there is little useful content on the forums as yet, which is where your assistance would be invaluable. You will need to register a user name, email and some details to post (viewing doesn't require this). How accurately you want to do this is entirely up to you. If you need to contact me, try pauljnospambaxter@hotnospammail.com without the nospam bits. Feedback appreciated.Article: 40037
Thanks Ken. Actually we finally figured it out and it was just as you say. Part of the confusion was in the difference between ISE4.1 and ISE3.3. I have a couple of students working for me to develop a specialized piece of instrumentation and we are trying to use the KCPSM to parse instructions to the instrument and then send the control parameters to the appropriate registers in the system. It looks like the KCPSM will be a good match for that application in this system. Thanks. Is the VHDL code available for the either the KCPSM or the KCPSM-II? I am wondering whether the code might be useful for them to have available. Also, am I correct in assuming that the KCPSM-II is merely the KCPSM re-implemented for the Virtex2? Or are there some other "refinements" in the KCPSM-II? Thanks again, Theron Hicks "Ken Chapman" <chapman@xilinx.com> wrote in message news:3C7A1EB1.D3DE6725@xilinx.com... > Dear Theron, > > Whilst the ISE environment does not understand an edif file, a vhdl 'black box' > will result in a 'socket' into which the edif will be inserted during the > translate stage. You will probably notice that after you translate the first > time, you will have a file called kcpsm.ngo (probably in a sub directory). This > is the edif translated into the internal format. > > BTW - I have just completed an all VHDL implementation of KCPSM-II which is > specifically for Virtex-II (not suitable for Virtex(E) and Spartan-II). If > anyone wants a copy, please drop me a direct email (chapman@xilinx.com). > > Yours sincerely, > > Ken Chapman > >Article: 40038
Hopefully you guys will pop along to the newly created fpga forum just for this purpose. http://pub64.ezboard.com/bfpgatipsandtricks Lets hope it floats :) I will be making sure ads stay out as long as there is some interest in the forums, but still too early to see if its going to be used. Love to see any tips you have. I'd be happy to edit and post them if you want to email them to me or of course post yourself. Paul "Luigi" <guiducci@cern.ch> wrote in message news:235ed672.0202230848.205f9018@posting.google.com... > Hi > thinking about some specific forum etc. about Altera Quartus and so on > (and Altera products, in general), I really agree. I'm quite new in > the field of FPGA/CPLD designing, and what I noticed is that it's easy > to find find thunderstorms of xilinx related discussion, not the same > with altera. > So, let us novices know! > Thanks for advices > > LuigiArticle: 40039
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:3C792751.E4A573D@yahoo.com... > Actually, the trend is to put more logic into parts with smaller IO > counts. This is from one generation to the next, not within a logic I think this is due to the fact that FPGAs are not intended to be "abused" for IO-port expanders like 8215 or so . . .;-) -- MfG FalkArticle: 40040
I would try the following changes in the code..
process(clk, reset)
Remove the TEMP_count and in_mca from sensitivity list which might be
confusing the synplify tool..
Arvind Kumar
FPGA Design Engineer,
Xebeo Communications, Inc.
One Cragwood Road, Suite 100,
South Plainfield, NJ 07080
Francisco Camarero <francisco.camarero@acterna.com> wrote in message news:<3C7A1DAD.A8A5E529@acterna.com>...
> I would try the following change:
> > process(clk, reset, TEMP_count(1), in_mca)
> > variable temp : std_logic_vector(11 downto 0);
> > begin
> > if reset = '1' then
> > out_mca <= "000000000000" ;
> temp : = (others => '0'); -- Reset temp too.
> > elsif rising_edge(clk) then
> > temp(11 downto 0) := in_mca ;
> > if TEMP_count(1) = '1' then
> > temp := ("111111111111" xor temp)+1 ;
> > end if;
> out_mca <= temp; -- Assignment should be
> here.
> > end if;
> -- out_mca <= temp ; Take this line out
> > end process;
>
>
> Antonio wrote:
> >
> > I've realized a circuit with the following behaviour :
> >
> > clk -> out_mca[11:0] = in_mca[11:0]
> > clk -> out_mca[11:0] = in_mca[11:0]
> > clk -> out_mca[11:0] = -in_mca[11:0]
> > clk -> out_mca[11:0] = -in_mca[11:0]
> >
> > ....
> >
> > clk -> out_mca[11:0] = in_mca[11:0]
> > clk -> out_mca[11:0] = in_mca[11:0]
> > clk -> out_mca[11:0] = -in_mca[11:0]
> > clk -> out_mca[11:0] = -in_mca[11:0]
> >
> > from Synplify I've a warning that I don't understand , it is :
> >
> > @W: mult_C2_adder.vhd(43): Feedback mux created for signal
> > out_mca[11:0]. Did you forget the set/reset assignment for this
> > signal?
> >
> > Can you help me to understand it, here's the code :
> >
> > library ieee;
> > use ieee.std_logic_1164.all;
> > use ieee.std_logic_signed.all;
> >
> > entity mult_C2_adder is
> > port(in_mca : in std_logic_vector(11 downto 0);
> > reset : in std_logic ;
> > clk : in std_logic ;
> > out_mca : out std_logic_vector(11 downto 0));
> > end mult_C2_adder;
> >
> > architecture mult_C2_adder_arch of mult_C2_adder is
> > signal TEMP_count : std_logic_vector(1 downto 0);
> > begin
> >
> > process(clk, reset)
> > begin
> > if reset = '1' then
> > TEMP_count <= "11";
> > elsif rising_edge(clk) then
> > TEMP_count <= TEMP_count + 1;
> > end if;
> > end process;
> >
> >
> > process(clk, reset, TEMP_count(1), in_mca)
> > variable temp : std_logic_vector(11 downto 0);
> > begin
> > if reset = '1' then
> > out_mca <= "000000000000" ;
> > elsif rising_edge(clk) then
> > temp(11 downto 0) := in_mca ;
> > if TEMP_count(1) = '1' then
> > temp := ("111111111111" xor temp)+1 ;
> > end if;
> > end if;
> > out_mca <= temp ;
> > end process;
> >
> > end mult_C2_adder_arch ;
>
> --
> Francisco Camarero
> Hardware Engineer
> ---------------------------------------------
> Acterna Zürich AG
> Förrlibuckstrasse 62 / 3d floor
> P.O. Box 74
> CH - 8037 Zürich
>
> GSM: +41 76 355 67 69
> Fax: +41 1 355 65 05
> ---------------------------------------------
Article: 40041"Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> schrieb im Newsbeitrag news:a5cpua$876$1@newsreader.mailgate.org... > I am wondering if it is possible to have an output FF in an IOB, but a > tri-state control FF outside of an IOB in Xilinx Virtex family of FPGAs? > The reason I care about this is because I still need to keep output FF's > Tco (Tval) low (That's why I still want to use the IOB output FF.), but > want to use CLB's FF to handle output tri-state buffer control to > improve the setup time of the tri-state control FF. How can this improve setup time? Because you can move the FF closer to the generating logic? Hmm, maybe you should revisit you pin layout and rearrange some pins (yes, this is a little bit hard if the board is already finished . .;-) -- MfG FalkArticle: 40042
"Peter Alfke" <peter.alfke@xilinx.com> schrieb im Newsbeitrag news:3C7A6878.971C0BED@xilinx.com... > Think about it: > When you access a BlockRAM, you have to perform adress decoding, 1 of at least > 512, at most 16K. When you access a flip-flop, there is no decoding. > Obviously, a BlockRAM is slower than a flip-flop, or even a LUTRAM. Very obvious, at least to me ;-) Talking about RAMs in FPGAs, the new Altera series sounds very promising. ENDLESS RAM, in all sizes. And the smallest member comes in a 600++ pin BGA :-0 -- MfG FalkArticle: 40043
Hi, What I understand from your comments is that somewhere in your design you are passing value to Feedback clock output port in the DCM Instance. Please check it out. Hope this helps. Arvind Kumar FPGA Design Engineer, Xebeo Communications, Inc. One Cragwood Road, Suite 100, South Plainfield, NJ 08872 Charles Wagner <Charles.Wagner@irisa.fr> wrote in message news:<3C6CEACE.53D7FC0C@irisa.fr>... > When analyzing unisims and simprims synopsys libraries (XilinX ISE4.1 > and Service Pack 3) > i get this message : > > ==> VITAL Entity 'DCM' has VITAL conformance error(s): > CLKFX : out std_ulogic := '0'; > ^ > **Error: vhdlan,2264 > /soft/xilinx_hd/M4.1i/vhdl/src/unisims/unisim_VITAL.vhd(9977 > > The port 'CLKFX' associated with timing generic 'TPW_CLKFX_POSEDGE' > must be > of mode InOut, Out or Buffer. > CLKFX : out std_ulogic := '0' > > > > > > Can anyone here give me a suggestion? > > Thanks. > > CharlesArticle: 40044
Hi, I suggest you use the DLL Locked output to deactivate the reset to your actual logic. This will ensure that your DLLs are locked before the actual Logic starts. Arvind Kumar FPGA Design Engineer, Xebeo Communications, Inc. One Cragwood Road, Suite 100, South Plainfield, NJ 08872 "jean-francois hasson" <jfhasson@club-internet.fr> wrote in message news:<3c776d76$0$4996$7a628cd7@news.club-internet.fr>... > Hi, > > I am working with a Virtex XCV600 dealing with three different clocks each > involving a DLL. After configuration I woul like to be sure the all the DLLs > are locked before any other operation. Can I use the delay until locked > (STARTUP_WAIT) property of each DLL and everything will be fine or do I have > to use some logic between the different locked signals ? > > Thanks, > > JFArticle: 40045
"king" <kingcoolking@rediffmail.com> schrieb im Newsbeitrag news:bd3eddeb.0202250435.2f60c6ea@posting.google.com... > Hi all, > I have a design which uses say X no of XCV1000E FPGAs. I wud like to > go for denser FPGAs ( XC2V6000). The total system gates in XCV1000E is > approximately 1.5 Million while in XC2V6000 is 6 Million. So can I > assume that the logic implemented in four (6/1.5) FPGAs can be > implemented using a single XC2V6000 FPGAs? But the LUTs of the two > looks different. Will this affect the beforesaid ratio? Or is there This depends o the design. If the design uses lot of RAM (BLOCK or DISTRIBUTED), the the size may be significantly reduced due to the much bigger BLOCK-RAMs in Virtex-II. But if the design uses mostly LUTs (not working as Distributed-RAM), then you have to compare the number of LUTs (be careful, a Virtex CLB has 4 LUTs/FFs, a Virtex-II CLB has 8 LUTs/FFs) -- MfG FalkArticle: 40046
"J Kenens" <jo_no_spam_please_.kenens@acunia.com> schrieb im Newsbeitrag news:Xns91C09903E1CAA556677@195.129.110.141... > The problem I'am having is the following: > > I'm working on a design which uses a cpld to configure the fpga in parallel > mode. Additinally the cpld and the fpga are configurable true jtag. (they > are connected in serial, FPGA-TDO connected to CPLD-TDI) > When I try to configure the Spartan2 and a the cpld true jtag, there's no > problem. > When I replace the Spartan2 by a virtex-E, the Xilinx Impact tools do > recognize the cpld but the Virtex-E remains invisible. When I try to > configure the cpld, I get an error. > Note that the Spartan2 and Virtex-E are almost completely pin-compatible ??? Are you SURE?? Last time I compared these two families the where not (at all). Maybe there is a short between VCC and GND, or other weired missconnection. Just today I found a pinout compare tool on the Xilinx website. -- MfG FalkArticle: 40047
kingcoolking@rediffmail.com (king) writes: > The total system gates in XCV1000E is > approximately 1.5 Million while in XC2V6000 is 6 Million. So can I > assume that the logic implemented in four (6/1.5) FPGAs can be > implemented using a single XC2V6000 FPGAs? No. The XC2V6000 gains a larger part of its total gates from BRAMs and its multiplier units. > But the LUTs of the two > looks different. The LUTs are identical 4-input type. The CLBs are different, having 4 vs 8 LUTs in them. > Will this affect the beforesaid ratio? Or is there > any other decisive factors involved? LUT count is the thing to compare: XCV1000E: 64x96x4=24576 XC2V6000: 96x88x8=67584 So you will get 67584/24576=2.75 more logic per chip. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual RobberyArticle: 40048
John_H wrote: > 2nS risetime? > > I thought most (performance) logic these days had sub-ns rise and fall times unless (for the FPGAs) > you specify a slow slew rate which would give you unacceptable (?) delays for the 133MHz timing. > The 1/6 factor seems like a nice rule of thumb but I'd worry more about hyperactive drivers doing > funny things without good signal integrity design. If you *always* have the three memories on > board, the capacitance will be uniform making the signal integrity issues a bit easier to deal with > unlike SDRAM systems with one or many banks. Tuning the current drive of the FPGA to your situation > may help balance the demands of the heavier capacitance - SDRAM clock, address, and control lines - > and the lighter capacitance signals. > > Jonh's raised one of the harder issues with DRAM system design at high speeds. If your memory is fixed, soldered down, then you can tune the IO drive but if your in a situation like ours where it could vary between a single sided DIMM with 4-off x16 chips to 2 fully loaded (i.e. 18 chips each) ones. Then: o For light load you want the slowest drivers so that you can meet the DIMMs hold time requirement of 0.8nsec +/- clock skew. SDRAMs being, these days, one of the few chips with a non-0 hold time requirement. o For heavy load it is, of course, the opposite. and that's before SI issues kick in. With Virtex-2 parts you could use the DCM to move the FPGA and DRAM clock's relative positions but for Virtex-E this is more difficult to achieve. Outstanding request for Virtex-3: make the IO drive strength dynamically configurable, being able to change the whole IO standard would be even better.Article: 40049
IMHO the key number is the number of logic cells. Ignore the 6M gate numbers and compare logic cells. That 6M number is taking some gate equivalency for ram which most designers consider seperately from their logic. So add up the logic cells and use that to compare density. The single part solution is nice because its cute, but something to keep in mind is that if your design can be partitioned in a smart way, you can P&R each section of the design seperately. And since P&R times seem to be exponential with size, there is a P&R big time savings to going with smaller parts. This way you P&R just the section you have changed. Our XC2V6000 takes all night to re-run, and sometimes we only changed a few lines of code in one place. Regards kingcoolking@rediffmail.com (king) wrote in message news:<bd3eddeb.0202250435.2f60c6ea@posting.google.com>... > Hi all, > I have a design which uses say X no of XCV1000E FPGAs. I wud like to > go for denser FPGAs ( XC2V6000). The total system gates in XCV1000E is > approximately 1.5 Million while in XC2V6000 is 6 Million. So can I > assume that the logic implemented in four (6/1.5) FPGAs can be > implemented using a single XC2V6000 FPGAs? But the LUTs of the two > looks different. Will this affect the beforesaid ratio? Or is there > any other decisive factors involved? Ur reply will be most welcom > with kind regs > king
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