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lecroy7200@chek.com wrote: > > I agree with what you wrote, however the video actually shows the > 750MHz LVDS output and they talk about it running at this speed. > I watched the video, but offhand, I don't recall them actually showing the clock the to FPGA at 750 MHz, other than at the viewgraph level- which segment of the video is that 750 MHz reference in? If you look at Nationals app note: http://www.national.com/signalpath/files/sp_designer103.pdf Page 7 shows the 1/4 Fs clock being used to clock the FPGA at Fs=1GHz, Fddr=250 MHz BrianArticle: 100726
One more doubt....
Tried to decrease the fanou by introducing bufferes for the
selection pins to the Mux. But it is not in the final output The Map is
optimizing the buffers away. It is listed in the xilinx library guide
also. But then how can we reduce the fanout or introduce extra
buffering....
Article: 100727vssumesh wrote: > One more doubt.... > Tried to decrease the fanou by introducing bufferes for the > selection pins to the Mux. But it is not in the final output The Map is > optimizing the buffers away. It is listed in the xilinx library guide > also. But then how can we reduce the fanout or introduce extra > buffering.... If the fanout of the select is your biggest problem, don't "buffer" those signals but replicate the registers. You need to talk the synthesizer into leaving the replicated logic in your design; in SynplifyPro I'd use the syn_preserve directive to keep those replicated registers in my design. If you can pipeline your 50:1 mux you can keep the performance and the simple mux structure rather than time-multiplexing a multiplex which... shouldn't produce any net benefit.Article: 100728
John- > The code you wrote was iterating over all addresses in the array in a > single cycle, which a memory cannot do, so you get a lot of > registers.... I had wanted to store the IO values "vertically", each column representing a bit-cell, because the IO pins carry multiple parallel bitstreams... but based on your advice I stored them horizontally and re-arranged other code to match. And that did work -- although I ended up with several distributed RAMs inferred, because read accesses occur in various ways. But it does save one heck of a lot of flip-flops and at least I've a grip now on how XST wants to deal with distributed RAM... thanks John. -JeffArticle: 100729
Hi guys, Any 1 help me with info on *.XDL file, i know that this file a ASCII verison of the NCD file. can 1 tell me where i can get more info?? i have extensively searched the Xilinx webpage in vain.Article: 100730
Hallo, I should measure the frequency of an input signal. Max frequency of signal is 100 KHz. I have made a simple system to detect rising edge of input signal using a flip flop. It samples the input signal every system clock cycle. To measure the input frequency I count the number of system clock periods between two rising edges of input signal. To test the system I' using a function generator. Reading the data acquired (using a fixed frequency) I have watched that every 5-10 datas there is an error. The number aquired is about 50% or 75% less than the others. Using a pull up resistor will be solved the error? Otherwise I need a system that verify glitches? -- MarcoArticle: 100731
On a sunny day (Mon, 17 Apr 2006 16:59:07 +0200) it happened "Marco T." <marc@blabla.com> wrote in <e20afs$303$1@nnrp.ngi.it>: >Hallo, >I should measure the frequency of an input signal. >Max frequency of signal is 100 KHz. > >I have made a simple system to detect rising edge of input signal using a >flip flop. >It samples the input signal every system clock cycle. >To measure the input frequency I count the number of system clock periods >between two rising edges of input signal. > >To test the system I' using a function generator. > >Reading the data acquired (using a fixed frequency) I have watched that >every 5-10 datas there is an error. >The number aquired is about 50% or 75% less than the others. > >Using a pull up resistor will be solved the error? > >Otherwise I need a system that verify glitches? > Hard to tell what your error source is. But in all cases you need to make a fast rise clean pulse. You need a Smitt-trigger. Basically an opamp with some positive feedback.Article: 100732
lecroy7200, That is very funny: "do not allow..." Excuse me, but I find that hilarious. As if the FPGA Police will swoop down on you and have you arrested. Right. In the fine tradition of: 1) knowing that all components are designed to meet certain specifications 2) and that most of the elements of a design normally exceed the specifications 3) and that it may be that you are willing to sacrifice one specification over another (max frequency vs duty cycle) engineers for decades have used components "outside" of their stated specifications. The 'penalty' for being caught, is that the manufacturer may state that the usage is not covered by the specifications, and thus, not guaranteed. Since the guarantee is just one of "take that part out, and replace it with another" the clever engineer has been taking advantage of their components for many years. Of course, the clever engineer has to perform a complete verification and characterization on their own to be sure that suddenly the feature that they are using doesn't go away. For example: is the usage one that has wide margin, or is it very tight? How does the usage vary with voltage and temperature? Have you tested it on devices from different lots? Did you call or ask someone at the factory what their opinion was? A very common practice is to buy commercial grade components. and qualify them yourself for an application that is not commercial grade. Maybe you just need to go from -20C to +85C, and you know, as a reasonably intelligent engineer, that the I grade and C grade parts are pretty similar silicon, and all most of the difference is the test program. Since getting colder is usually not a problem with timing, or performance (at least is used to be, can't say that is true any longer), it is a safe bet to say that a C grade part will work fine at -20C? Now the previous practice was pretty common, and I am not sure of how common that still is. Getting back to the clock. How fast do you want to go? What duty cycle distortion can you tolerate? Over what temperature range? How many do you need to make? Does it still meet the thermal Tj requirements? If it is found "to work" at room temp, and nominal voltages, looks like there is a lot more engineering that you have to do. I have no idea what National did (haven't seen the presentation). I am sure it is all there in the documentation, as it has been pointed out. And, it sounds like they have a clock/4 option, which is just smart. Enjoy. Austin lecroy7200@chek.com wrote: > I think I wrote DES in that last note, which would have been incorrect. > > > Austin, > > Thanks for the input. Do you know if the parts are indeed running at > the 750MHz as stated in the video? Talking with Altera they also claim > the part was running in DDR mode, again not what the video shows. I > have tried to contact National about the design, but no luck yet. > > "It won't be 45/55% like the spec sheet says, but it will still have a > perfectly good pulse there. Obviously National is using this. Since > they are using it, that makes Xilinx kind of responsible for some > support of this application. " > > I am not sure what the arrangement would be that Xilinx would be > responsible for what I would consider a bad design (assuming they > really are running the part at 750MHz). If Xilinx does plan to support > higher clock rates, what does this mean to me as a designer? Are there > any application notes that talk about overclocking the Virtex 4? > > Just an FYI, if I try to do this same thing with the Stratix II and > Quartus, the tool will spit out an error. I spoke with Altera about > this and they made the comment that they do not allow the parts to be > over driven. >Article: 100733
It was a 2-part video. Part 1, they start talking about the 1.5GHz clock. At 8:46 seconds, H.J. states ".. so its actually going to output two words at a time, with a clock thats a half speed clock." At 9:04 Ian states ".. you will create a 750MHz, ah.." Interrupted by H.J. If they ran it using DDR mode, I would think they would not have made a point to call out the 750MHz clock.Article: 100734
Hi, Peter,
Thank for your suggestion.
But I have two questions now:
(1) if i want to "filter" the clock source for generating a new clear
clock,
how can i do ?
(2) you mentioned "add some delay to ...", can i add use LCELL()
delay cell ?
And if i use DC synthesis, how can i do and how can i guarantee
delay is proper ?
thanks
Article: 100735andrewfelch@gmail.com wrote: > I am a Python programmer writing neural network code with binary firing > and binary weight values. My code will take many days to parse my > large data sets. I have no idea how much fpga could help, what the > cost would be, and how easy it would be to access it from Python. The > problem is similar to competitive networks, where I must dot product > many million-length bit vectors (which only change occasionally) with 1 > input vector. Anybody want to estimate the cost, speedup, and value an > fpga could offer me? Probably you could get considerable speedup by changing to a compiled language and by selecting a good algorithm. The most likely speed limit is the rate at which you can get data in and out of the computer. If an fpga can help, how much it can help is likely to be affected by how it's connected: USB, PCI, PCI-X, or even front-side bus.Article: 100736
>That is very funny: "do not allow..." >Excuse me, but I find that hilarious. >As if the FPGA Police will swoop down on you and have you arrested. >Right. I am not sure why they would do this other than trying to protect the customer from themselves. You may want to ask the Altera people this one. >engineers for decades have used components "outside" of their stated specifications. >The 'penalty' for being caught, is that the manufacturer may state that the usage is not covered by the specifications, and thus, not guaranteed. That was my question. Is this the level of support we would expect from Xilinx? >A very common practice is to buy commercial grade components. and qualify them yourself for an application that is not commercial grade. Ah, the stories that come to mind...Article: 100737
does anyone have any information about this chip? I heard it mentioned in the same sentence as a 22v10 but I havent been able to dig up any pin outs/schematics online. ThanksArticle: 100738
I offered a "BandAid", not a cure. Just invert the clock and use this inverted clock as CE. This does not eliminate the glitch, but it makes sure that the counter does not react to it. Maybe you do not need any extra delay... Peter AlfkeArticle: 100739
lecroy7200, Comments on the comments, -snip- > I am not sure why they would do this other than trying to protect the > customer from themselves. You may want to ask the Altera people this > one. That is always a good idea, but the best way to keep customers out of trouble is to educate them. Providing mindless rules without a good reason can just lead to more headaches. >>The 'penalty' for being caught, is that the manufacturer may state that > the usage is not covered by the specifications, and thus, not > guaranteed. > > That was my question. Is this the level of support we would expect > from Xilinx? The conversation from Xilinx would go like this: "Do you use the part within its specifications?" Your answer - 'No...' "OK, so what was your expectation?" 'that it would work' "And does it, in fact work?" 'well, not always' "Well, I'm really sorry about that, maybe there is some way to work around this issue, and get it to work within specifications and do what you want. Let me understand your application..." Basically, Xilinx is not going to throw you to the wolves. But we are not going to redesign the chip for you, either. http://cache.national.com/ds/DC/ADC08D1500.pdf Figure 4, DDR clocking shows how a 1.5 GHz clock into the ADC, comes out as a clock/4 on each of the 0 and 90 degree clocks, so that you can capture four 8 bit bytes in the clock/4 period, (using both rising and falling edges of the 0 and 90 degree data clocks outs). So it looks to me like no "laws" are broken....Article: 100740
hi, please anybody can share a VHDL controller for a FLASH memory likeAm29DL640 : http://www.spansion.com/products/Am29DL640D.html .. i have write mine, but it seem that i have some trouble with the simulation model.. before say "the model is bad" , i would be sure that my controller is right .. ) the trouble is at the last of write cycle, when i try to check the toggle bit. he's never toggle ! .. thank's philippeArticle: 100741
I think I did my first EP610 design (Altera's original PLD family) back in 1989. Why do you want to know about what equates to a 400 year old man? "samiam" <samiamSPAMTHIS@spamthis.org> wrote in message news:mHP0g.164$ID2.163@fe08.lga... > does anyone have any information about this chip? > I heard it mentioned in the same sentence as a 22v10 but I havent > been able to dig up any pin outs/schematics online. > > ThanksArticle: 100742
If you want to measure 100 kHz with 1% accuracy, you need to count the incoming pulses for at least 1 millisecond. Or you can measure the 10 microsecond period length, if you have a clock available that is faster than 10 MHz. Measuring for a longer time reduces the impact of signal rise time and jitter, but requires a counter to establish the ms time base. This is all covered in hundreds of text books... Peter AlfkeArticle: 100743
> Providing mindless rules without a good reason can just lead to more headaches. I would have to leave this one to the Altera guys. I am not sure if they would view it as a mindless rule or not. I have a call into National. I will post their responce.Article: 100744
John_H wrote: > I think I did my first EP610 design (Altera's original PLD family) back in > 1989. > Why do you want to know about what equates to a 400 year old man? LOL I am about to stock up on 200 of these chips ... and would jump at the opportunity if they are ANYTHING like the 22v10 ... Basically I need to stock up on these for my hobby work and I am being offered an unbelievable price on them. Problem is ... I dont have any info on these PLD's What can you tell me about it? How does it differ from the 22v10? How many inputs? How many outputs? Number of Minterms? Programmable output? Registered output? ThanmksArticle: 100745
Guyzz I Was just checkking if the S3E was available at the Xilinx Store but it still isn't. They refer to Avnet , but there it costs $178. Those $28 would be the shipping from Xilinx , so i hope Avnet is shipping for free. Else those $28 + maybe more shipping would "hurt" for a private VHDL learner. I am from from Europe , and wonders if the shipping is also more from Avnet ???. Any places in Europe where the S3E kit is available for £149 ??? Regards CarstenArticle: 100746
On Mon, 17 Apr 2006 13:40:59 -0400, samiam <samiamSPAMTHIS@spamthis.org> wrote: >John_H wrote: >> I think I did my first EP610 design (Altera's original PLD family) back in >> 1989. >> Why do you want to know about what equates to a 400 year old man? > >LOL >I am about to stock up on 200 of these chips ... and would jump at the >opportunity if they are ANYTHING like the 22v10 ... > >Basically I need to stock up on these for my hobby work and I am being >offered an unbelievable price on them. > >Problem is ... I dont have any info on these PLD's > >What can you tell me about it? >How does it differ from the 22v10? >How many inputs? >How many outputs? >Number of Minterms? >Programmable output? >Registered output? > >Thanmks http://www.altera.com/literature/ds/classic.pdfArticle: 100747
samiam wrote:
> I am about to stock up on 200 of these chips ... and would jump at the
> opportunity if they are ANYTHING like the 22v10 ...
You might look before you leap.
You could a buy brand new 3000a series
device (much better than a 22V10)
for $1.25 each at quantity 1.
http://www.buyaltera.com/scripts/partsearch.dll/showfilter?lookup=1,30,3076
Fully documented
http://www.altera.com/literature/ds/m3000a.pdf
free software
http://www.altera.com/products/software/products/quartus2web/sof-quarwebmain.html
-- Mike Treseler
Article: 100748samiam wrote: > John_H wrote: > >> I think I did my first EP610 design (Altera's original PLD family) >> back in 1989. >> Why do you want to know about what equates to a 400 year old man? > > > LOL > I am about to stock up on 200 of these chips ... and would jump at the > opportunity if they are ANYTHING like the 22v10 ... > > Basically I need to stock up on these for my hobby work and I am being > offered an unbelievable price on them. > > Problem is ... I dont have any info on these PLD's > > What can you tell me about it? > How does it differ from the 22v10? > How many inputs? > How many outputs? > Number of Minterms? > Programmable output? > Registered output? You have not asked how to program them yet, which might be the most important question :) You will need to generate code, and also get the code into the chips.... ( which I believe are OTP ) -jgArticle: 100749
Antti Lukats wrote: >Digikey should not be considered as any choice (getting Xilinx silicon) - >Digikey >is great to occasionally check overall thumb guess component pricing and >availability. >It is ok to buy from digikey for small series, but then all components >should be >purchased for the full production span as any components that used to be >available >on Digikey may disappear anytime without notice. I had a project that was >covered >almost 100% from components available at Digikey, at the time it was ready >for >production most of those parts from the BOM where dropped by Digikey. > > > Digi-Key will sell you just about anything Xilinx makes, but they have high minimum orders on a LOT of the parts, now. (This is all from the web, there's practically nothing in the catalog any more.) Some of the minimum orders were in the $10K range, I think, when I scanned through a bunch of parts trying to figure out what the HELL they were up to. It made no sense to me at the time. I have found a vendor in Australia that has good stock and much better prices than anybody in the US, and no minimum. There are also some Hong Kong/Taiwan "distributors" that have such low prices, I assume the parts have to be counterfeit. I'm too scared to try any of those! Jon
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