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Peter Alfke wrote: > Let me blame T.I. for inventing (in the late 'sixties) the stupid name > "Hold Time", when we are really talking about the latest possible > instant of Set-Up Time. Really ?! And I thought the Window between Setup and Hold is where the input signal is NOT supposed to change (e.g. remain stable) ! > Any D-flip-flop has an extremely tiny timing window (femtoseconds wide), > where it takes a snapshot of the D-input and generates either Q or Qbar. > The exact position (in time) of this tiny window with respect to the > clock edge is a function of processing, temperature and Vcc. Depending on the clock transition time the window can be larger or smaller (and is also of course process dependent). Hmm, all flops I have seen generate both Q and Qbar. > The earliest possible position is specified as Set-up-time. The latest > possible position is (unfortunarely) specified as Positive Hold Time if > it is later than the clock edge, and as Negative Hold Time if it is > before the clock edge. Actually the latest possible change of the data is Setup time, and the earlist possible change is Hold Time. > It would be so much nicer if we used only one parameter name, and called > the two extremes the max and the min value of the set-up time. I lost > that battle 30 years ago. It still smarts every time I hear "Hold Time" > . :-( > > Peter Alfke rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 66001
Ville Voipio <vvoipio@kosh.hut.fi> wrote: > > We have two CPLDs on a board (Altera EPM7256A and Xilinx > XCR3064XL) and would like to program them with a single tool. > ... > > Then the workflow would be: > > - Altera: Quartus II Web Edition -> .jam -> JAM player > - Xilinx: ISE WebPack iMpact -> .jam -> JAM player > Are you sure that the free version of Quartus will output .jam files ?? I thought you had to pay for the full version to anything other than program directly from the IDE ??Article: 66002
William Wallace wrote: > rickman <spamgoeshere4@yahoo.com> wrote in message news:<40286B1C.8BD933C4@yahoo.com>... > >>Jan Panteltje wrote: >> >>>On a sunny day (Mon, 09 Feb 2004 13:21:48 -0800) it happened Peter Alfke >>><peter@xilinx.com> wrote in <4027F9ED.F7C82422@xilinx.com>: >>> >>> >>>>If you build something in small volume, everything is expensive: design >>>>effort, pc-boards, most components, testing, marketing, advertising, >>>>selling, servicing etc. You must have a really good product to absorb >>>>all these high costs. That's life. >>>>Peter Alfke >>> >>>Hey, of cause things are expensive. >>>Now log in to www.microchip.com >>>Find a PIC, you can enter a quantity and order right there. >>>Whats your problem? >>>Perfect for small business. >> >>And you will pay some 3 or 4 times what you would pay if you were buying >>1000's. I know, I have looked. >> > > > How is this any different than any other product? Resistors, for > example. Go to digikey and try to buy 3 0805 100 Ohm resistors. Your > price per resistor will be much higher than if you bought several > dozen reels from a distributor. Yes, then add 15$ for shipping the 3 resistors. Or 30$ or so for express delivery. ReneArticle: 66003
Hi all, How to remap an standard IO to a BUFG in the SPARTAN-II techno. Webpack gives error when I try. Are there any webpack option for that? Best regards, LarryArticle: 66004
armcc@lycos.com (Andre) writes: > Are you sure that the free version of Quartus will output .jam files > ?? No, I am not sure. I did not even come to think of an alternative that evil. By looking at the Altera site they do not mention anything about this. This feature is not on the list of "if you pay more, you'll get these", but that does not necessarily mean anything. > I thought you had to pay for the full version to anything other > than program directly from the IDE ?? Possible. Let's see... Anyway, if this is the case, the CPLD on our next design does not start with an "A". Not giving out the software for free is one thing. Not telling the extent of the lobotomy of the "free" version is another. - Ville -- Ville Voipio, Dr.Tech., M.Sc. (EE)Article: 66005
Hi, thank you very much for your help. Best regards AndreArticle: 66006
Hi everybody, I wonder about the consumption of hardware ressources when using memory initialization files (hex or mif) in Altera QuartusII. Are there any differences between mif and hex with regard to consumption ? Do they need extra hardware ressources at all? Thank you in advance AndreArticle: 66007
Here is the particular area on Xilinx's web-site : http://www.xilinx.com/ise/power_tools/. Xilinx provides 2 types of power estimation tools - pre-implementation (Spreadsheet and Web) and design-based (XPower). Both pre-implementation tools are directly accessible from the above site and, as Benjamin points out, require resource and frequency i/ps from the users. XPower comes as part of ISE and requires a design that has been at least mapped. (It also operates on a placed design or on a placed & routed design.) All three tools support V2. Regards, Brendan Benjamin Todd wrote: > if you look on the Xilinx web-site they have power calculation tools, you > need to know the resources used and the clock frequency, as far as I can > remember. > Ben > > "sunil" <inaganti_suni@yahoo.com> wrote in message > news:9f28d282.0402092133.2190279@posting.google.com... > > hi, > > i designed decoder in vhdl and i am going to map that on vertex-II > > xilinx FPGA. Can any body have the idea how to calculate the power > > consumption in that design. > > thanking u all.Article: 66008
I did something similar several months back with a Spartan IIE. Watch out for termination issues. In my case it appeared as double clocking. I was able to work around it because the Spartan allowed me to reduce the drive current and edge rise times. Once I did that, the strange behavior I ran into during hardware testing went away. Also as mentioned in other posts, use the micron dram models and be sure your controller works exactly as you expect in the simulator before even thinking about trying it for real. Otherwise you are in for a lot of frustration and head scratching. "Antti" <antti1000@yahoo.com> wrote in message news:<%m%Vb.8944$g4.183754@news2.nokia.com>... > Hi, > > I've implemented an sdram controller on an fpga (to micron 128 MB memory) > and tested it with a sequence of write and subsequent read bursts. In around > 1 in 5 attempts, the correct read data appears on the dq[31..0] data bus, > otherwise the memory read just returns 0xFFFFFFF. Could someone please give > pointers to why might this be? > > Thanks, > AnttiArticle: 66009
There is no difference in the hardware resources used. You can convert easily between the mif and hex files using the Quartus memory editor and check it out. - Subroto Datta Altera Corp. "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0402110407.2518426f@posting.google.com... > Hi everybody, > > I wonder about the consumption of hardware ressources when > using memory initialization files (hex or mif) in Altera QuartusII. > Are there any differences between mif and hex > with regard to consumption ? Do they need extra hardware ressources > at all? > > Thank you in advance > > AndreArticle: 66010
i have the following full IP core. pls mail me if need . ********************************************************************** Ethernet MAC: 10M/100M/1G/10G USB:1.0/2.0/OTG fast JPEG MPEG4/MPEG2 PCI/PCI-X Bluetooth 8051/ATA/CAN/Z80/QAM/6811/AMBA/MJPEG/smart card/T1E1/PCMCIA/I2C/HDLC/16550/IEEE 1284/G711/G726 ******************************************************************* pls mail me: brahms_view@yahoo.itArticle: 66011
Rudi, Yawn....... Bob "Rudolf Usselmann" <russelmann@hotmail.com> wrote in message news:c0cql4$vb7$1@nobel2.pacific.net.sg... > Peter Alfke wrote: > > > Let me blame T.I. for inventing (in the late 'sixties) the stupid name > > "Hold Time", when we are really talking about the latest possible > > instant of Set-Up Time. > > Really ?! > > And I thought the Window between Setup and Hold is where the > input signal is NOT supposed to change (e.g. remain stable) ! > > > Any D-flip-flop has an extremely tiny timing window (femtoseconds wide), > > where it takes a snapshot of the D-input and generates either Q or Qbar. > > The exact position (in time) of this tiny window with respect to the > > clock edge is a function of processing, temperature and Vcc. > > Depending on the clock transition time the window can be larger > or smaller (and is also of course process dependent). > > Hmm, all flops I have seen generate both Q and Qbar. > > > The earliest possible position is specified as Set-up-time. The latest > > possible position is (unfortunarely) specified as Positive Hold Time if > > it is later than the clock edge, and as Negative Hold Time if it is > > before the clock edge. > > Actually the latest possible change of the data is > Setup time, and the earlist possible change is Hold Time. > > > It would be so much nicer if we used only one parameter name, and called > > the two extremes the max and the min value of the set-up time. I lost > > that battle 30 years ago. It still smarts every time I hear "Hold Time" > > . :-( > > > > Peter Alfke > > > rudi > ======================================================== > ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: > ..............::: FPGAs * Full Custom ICs * IP Cores ::: > FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 66013
Hi, I am trying to debug a microblaze system with use of the opb mdm device. I am able to connect to the mdm target and after being connected, I start a gdb session: XMD% start mb-gdb my_mblaze/code/executable.elf In gdb I do a "connect target" which succeed. Now comes the problem: how to step through the code?? If I try to single step or run the program, gdb looks hanging (the mousepointer changes to an hourglass). I saw in the embedded system tools guide something about "dow", "con" and "stop" commands which are used within xmd. Do I have to run/debug my program from xmd?? What is the relation between gdb and xmd? TIA, FrankArticle: 66014
Hi, Is it possible to debug an application which is in sdram by use of xmdstub? I have a small bootloader program which programs a final application into sdram (by use of xmodem). Now I want to debug this application, is that possible or should I use the opb mdm device?! If it's possible, I guess I have to build a bootloader with the xmdstub and make a connection. But how to get my application into the sdram? Can I use the "dow" command at the xmd command line or an option inside gdb to download the application into sdram (I'm asking this, because in the normal way the user has to give some input via the serial port, but that's the same port for debugging thus I can't give any input). And how to step through the code when the application is in the sdram?! TIA, FrankArticle: 66015
Hello there, Has anyone implemented a NAND interface in a PLD? I don't mean a 'smart' NAND controller, just an interface that lets you toggle ALE, CLE, CE externally and do read/write accesses to the NAND ports. Thanks, Guillermo RodriguezArticle: 66016
Frank, It should not run away from you if you've got the checkbox set to "set breakpoint at main" in the connection window. If it is not halting despite this option, then there's likely a more fundamental problem with your system. If that's the case and with that in mind; it is not required that you debug from XMD but it may be easier to track down the problem. See my response to your second post. Best regards, Ryan Laity Xilinx Applications Frank van Eijkelenburg wrote: > Hi, > > I am trying to debug a microblaze system with use of the opb mdm device. I > am able to connect to the mdm target and after being connected, I start a > gdb session: > > XMD% start mb-gdb my_mblaze/code/executable.elf > > In gdb I do a "connect target" which succeed. Now comes the problem: how to > step through the code?? If I try to single step or run the program, gdb > looks hanging (the mousepointer changes to an hourglass). I saw in the > embedded system tools guide something about "dow", "con" and "stop" commands > which are used within xmd. Do I have to run/debug my program from xmd?? What > is the relation between gdb and xmd? > > TIA, > Frank > >Article: 66017
Frank, Yes, you can do exactly what you have described. When you use the "dow" command from the XMD command prompt (after an mbconnect), XMD will use the available memory interface core to place the .elf at whatever location has been specified in your linker script. Therefore, you want to "dow" the final application, not the bootloader. You are essentially letting MDM/XMD act as your bootloader in this case. Once the .elf is downloaded, you can then "con" to run or "stp" (step) from the command line and see what instruction is causing the problem you described in your previous post. If the system hangs on one of your first steps then you probably have a problem with your hardware (likely logical or timing issue with your memory interface and/or board). If this is the case, try using the "mwr" and "mrd" commands from XMD to see if you can get data in and out of your memory correctly. You can also try to "dow" your .elf file, do an object dump (mb-objdump) of the .elf, then use "mrd" on a large block of the instruction memory, and do a comparison between the dumped .elf and what's in the memory. If there are any mismatches then there's likely a problem with the memory interface hardware/timing. If it's many instructions into the run, and that instruction memory location looks correct, then the software is likely at fault. Use that dumped .elf file to figure out which instruction is causing the problem and debug accordingly. Hopefully you are able to resolve the problem using this information. If not then please contact our support hotline for more help. Best regards, Ryan Laity Xilinx Applications Frank van Eijkelenburg wrote: > Hi, > > Is it possible to debug an application which is in sdram by use of xmdstub? > I have a small bootloader program which programs a final application into > sdram (by use of xmodem). Now I want to debug this application, is that > possible or should I use the opb mdm device?! If it's possible, I guess I > have to build a bootloader with the xmdstub and make a connection. But how > to get my application into the sdram? Can I use the "dow" command at the xmd > command line or an option inside gdb to download the application into sdram > (I'm asking this, because in the normal way the user has to give some input > via the serial port, but that's the same port for debugging thus I can't > give any input). And how to step through the code when the application is in > the sdram?! > > TIA, > Frank > >Article: 66018
Something like U_0 and U_1, but I believe it depends on your synthesis tool.
Check your synthesis output for the correct labels.
"chris" <ccoutand@hotmail.com> wrote in message
news:ee82713.-1@WebX.sUN8CHnE...
Hi,
I'm trying to used the primitive
ROM128X1 in my design and I want to initialise the attribute INIT of this
primitive.
This is working fine when I use only one primitive like :
----------------------------
architecture ...
component ROM128X1
-- synthesis translate_off
generic (INIT : bit_vector := X"128");
-- synthesis translate_on
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic
);
end component;
attribute INIT : string;
attribute INIT of U : label is "..";
begin
U : ROM128X1
port map(
O => data_out,
A0 => addr_in(0),
A1 => addr_in(1),
A2 => addr_in(2),
A3 => addr_in(3),
A4 => addr_in(4),
A5 => addr_in(5),
A6 => addr_in(6)
);
end;
----------------------------
but in the case I used a generate statement like :
----------------------------
begin
t : for i in 0 to 1 generate
U : ROM128X1
port map(
O => data_out(i),
A0 => addr_in(0),
A1 => addr_in(1),
A2 => addr_in(2),
A3 => addr_in(3),
A4 => addr_in(4),
A5 => addr_in(5),
A6 => addr_in(6)
);
end generate;
end;
---------------------------
what name of instance do I have to use to declare the attributes INIT.
Thanks
Article: 66019Besides some meaningless semantic quibbling, Rudi's answer indicated basic conceptual differences. A component data sheet should have a component-centric view: The flip-flop has a window in time during which the D-input must be stable, to guarantee predictable operation. This window has an early edge (commonly called set-up time, often specified as a min, but I would call it a max), and it has a late edge (commonly called positive hold time when it is later than the clock edge, negative hold time when it is before the clock edge. I would like to call it the min set-up time, but it's too late to bring sanity to this issue). Whether something is a min or a max depends on your perspective. With a bridge over a highway, the "14 feet" specification is a min for the bridge builder, but a max for the truck driver... Much of this is semantics, but semantics can interfere with understanding, sometimes. Peter Alfke Rudolf Usselmann wrote: > > Peter Alfke wrote: > > > Let me blame T.I. for inventing (in the late 'sixties) the stupid name > > "Hold Time", when we are really talking about the latest possible > > instant of Set-Up Time. > > Really ?! > > And I thought the Window between Setup and Hold is where the > input signal is NOT supposed to change (e.g. remain stable) ! > > > Any D-flip-flop has an extremely tiny timing window (femtoseconds wide), > > where it takes a snapshot of the D-input and generates either Q or Qbar. > > The exact position (in time) of this tiny window with respect to the > > clock edge is a function of processing, temperature and Vcc. > > Depending on the clock transition time the window can be larger > or smaller (and is also of course process dependent). > > Hmm, all flops I have seen generate both Q and Qbar. > > > The earliest possible position is specified as Set-up-time. The latest > > possible position is (unfortunarely) specified as Positive Hold Time if > > it is later than the clock edge, and as Negative Hold Time if it is > > before the clock edge. > > Actually the latest possible change of the data is > Setup time, and the earlist possible change is Hold Time. > > > It would be so much nicer if we used only one parameter name, and called > > the two extremes the max and the min value of the set-up time. I lost > > that battle 30 years ago. It still smarts every time I hear "Hold Time" > > . :-( > > > > Peter Alfke > > rudi > ======================================================== > ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: > ..............::: FPGAs * Full Custom ICs * IP Cores ::: > FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 66020
Have you tried to buffer the clock to a normal IBUF first then re-buffer it to BUFG? I did that in virtex.Article: 66021
Hi
It's easier to embed the attribute inside the generate
and assign the attribute value using some kind of function
to make the code portable. Something like
t: for i in 0 to 1 generate
attribute INIT of U: label is rom_init_values(i);
begin
U: ROM128X1 port map (
xxxx );
end generate;
where you've previously declared a constant array of init values for your
ROMs.
You can even put that constant array inside the generate, just before the
attribute line
Best regards
Francisco Rodriguez
"Barry Brown" <barry_brown@remove_this.agilent.com> escribió en el mensaje
news:1076520492.769192@cswreg.cos.agilent.com...
> Something like U_0 and U_1, but I believe it depends on your synthesis
tool.
> Check your synthesis output for the correct labels.
>
>
> "chris" <ccoutand@hotmail.com> wrote in message
> news:ee82713.-1@WebX.sUN8CHnE...
> Hi,
> I'm trying to used the primitive
> ROM128X1 in my design and I want to initialise the attribute INIT of this
> primitive.
> This is working fine when I use only one primitive like :
> ----------------------------
> architecture ...
> component ROM128X1
> -- synthesis translate_off
> generic (INIT : bit_vector := X"128");
> -- synthesis translate_on
> port (
> O : out std_ulogic;
> A0 : in std_ulogic;
> A1 : in std_ulogic;
> A2 : in std_ulogic;
> A3 : in std_ulogic;
> A4 : in std_ulogic;
> A5 : in std_ulogic;
> A6 : in std_ulogic
> );
> end component;
> attribute INIT : string;
> attribute INIT of U : label is "..";
> begin
> U : ROM128X1
> port map(
> O => data_out,
> A0 => addr_in(0),
> A1 => addr_in(1),
> A2 => addr_in(2),
> A3 => addr_in(3),
> A4 => addr_in(4),
> A5 => addr_in(5),
> A6 => addr_in(6)
> );
> end;
> ----------------------------
> but in the case I used a generate statement like :
> ----------------------------
> begin
> t : for i in 0 to 1 generate
> U : ROM128X1
> port map(
> O => data_out(i),
> A0 => addr_in(0),
> A1 => addr_in(1),
> A2 => addr_in(2),
> A3 => addr_in(3),
> A4 => addr_in(4),
> A5 => addr_in(5),
> A6 => addr_in(6)
> );
> end generate;
> end;
> ---------------------------
> what name of instance do I have to use to declare the attributes INIT.
> Thanks
>
>
Article: 66022armcc@lycos.com (Andre) wrote in message news:<ae5c06e9.0402110118.5a1ba41f@posting.google.com>... > Ville Voipio <vvoipio@kosh.hut.fi> wrote: > > > > We have two CPLDs on a board (Altera EPM7256A and Xilinx > > XCR3064XL) and would like to program them with a single tool. > > ... > > > > Then the workflow would be: > > > > - Altera: Quartus II Web Edition -> .jam -> JAM player > > - Xilinx: ISE WebPack iMpact -> .jam -> JAM player > > > > Are you sure that the free version of Quartus will output .jam files > ?? I thought you had to pay for the full version to anything other > than program directly from the IDE ?? Yes the Quartus II Web Edition does output jam files. The way do so is to Open the Quartus Programmer, load the pof/sof file and Use the File Create/Update dialog. Both the free Web Edition and the Quartus II Full subscription have the same capabilities for both programming and for generating/converting programming files. - Subroto Datta Altera Corp.Article: 66024
Hi Guillermo, Take a look at Xilinx Application Note, XAPP354 located at: http://direct.xilinx.com/bvdocs/appnotes/xapp354.pdf Hope that helps! Mark guille wrote: > Hello there, > > Has anyone implemented a NAND interface in a PLD? I don't mean a > 'smart' NAND controller, just an interface that lets you toggle ALE, > CLE, CE externally and do read/write accesses to the NAND ports. > > Thanks, > Guillermo Rodriguez
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