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Messages from 65925

Article: 65925
Subject: Re: Is nobody using c++ and/or plugs-lib? was Re: nios c++ and ethernet [may by ot?]
From: Petter Gustad <newsmailcomp5@gustad.com>
Date: 10 Feb 2004 09:57:09 +0100
Links: << >>  << T >>  << A >>
kempaj@yahoo.com (Jesse Kempa) writes:

> The one thing I remember that was special was includes were inside an
> "extern "C" { <includes here> } statement... like this:
> 
> extern "C" {
> #include "excalibur.h"
> #include "plugs.h"
> #include "plugs_example_designs.h"
> }

This should have been done *inside* plugs.h:

#ifndef _plugs_
#define _plugs_

#ifdef __cplusplus
extern "C" {
#endif
...
#ifdef __cplusplus
}
#endif
#endif // _plugs_

This type of structure is used in excalibur.h so it should have been
done in plugs.h too (at least for consistency).

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 65926
Subject: Re: Quartus II taking forever to compile
From: Petter Gustad <newsmailcomp5@gustad.com>
Date: 10 Feb 2004 10:01:51 +0100
Links: << >>  << T >>  << A >>
"Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> writes:

> We'll release a 64-bit version of Quartus when one is needed in
> order to address more memory. Windows XP maxes out at 3 GB (with a


Will Quartus II 4.x *run in 32-bit mode* on an AMD64 based machine? 

I use Opteron based systems due to their excellent performance, even
on 32-bit applications. However, Quartus II 3.x does not run since a
silly csh based driver script failes to detect the architecture (if
the script simply *tried* to run the X86 binary I would probably
work):

$uname -m
x86_64
$/usr/local/altera/quartus2-3.0sp2/bin/quartus_sh -t quartus.tcl
Unknown Linux processor
MWARCH: Undefined variable.


Petter

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 65927
Subject: Synchronization of signals
From: ALuPin@web.de (ALuPin)
Date: 10 Feb 2004 01:03:21 -0800
Links: << >>  << T >>  << A >>
Hi everybody,

I have a question concerning the following:


The signal 'valid_48' is one clock_cycle (48MHz) high.
Now I want to use it in a clock domain which has a clock of 90MHz.

How can I synchronize it correctly?

I have thought of the following:


 process(Clk_90)
 begin
    if Reset='1' then
       valid_90 <= '0';
       valid_h1 <= '0';
       valid_h2 <= '0';
       
    elsif rising_edge(Clk_90) then

       valid_h1 <= valid_48;
       valid_h2 <= valid_h1;
       valid_90 <= valid_h1 and (not valid_h2);
    end if;       
 end process;

Are there some problems arising because of the clock-relation factor 48/90 ?

Thank you very much.

Kind regards

Andre

Article: 65928
Subject: Re: VHDL:Dividing a real number by two??
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Tue, 10 Feb 2004 20:04:56 +1100
Links: << >>  << T >>  << A >>
On Tue, 10 Feb 2004 08:55:53 +0000 (UTC), Uwe Bonnes
<bon@elektron.ikp.physik.tu-darmstadt.de> wrote:

>Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote:
>
>: try 
>
>: LAPP / 2.0
>
>: '2.0' is a real, and '2' is an integer (and the compiler hasn't been
>: told to divide a real by an integer).
>
>What about substracting -1 from the exponent?

That doesn't work in general (for IEEE floating point).  There are
special cases to consider.  Besides, we don't know yet whether the OP
requires synthesisable code.

Regards,
Allan.

Article: 65929
Subject: negative hold time
From: praveenkn123@yahoo.com (prav)
Date: 10 Feb 2004 01:32:42 -0800
Links: << >>  << T >>  << A >>
What is negative hold time and what does it specify physically? 

Thanks in advance

rgds,
prav

Article: 65930
Subject: Re: Online debate: Programmable Logic vs ASIC vs Gate Array
From: pfoord@iee.org.uk (Peter Foord)
Date: 10 Feb 2004 02:10:10 -0800
Links: << >>  << T >>  << A >>
The link should be working now.  We are looking into whether there was
a problem over the weekend.  The full URL for the page is
http://www.iee.org/oncomms/sector/electronics/techdebate.cfm

The IEE has purchased the domain www.iee.tv for streamed video content
from IEE events.

Peter



glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in message news:<lZEVb.8175$QA2.19734@attbi_s52>...
> 
> It seems to be at http://www.iee.org/techdebate/
> 
> I don't know why they would be at iee.tv.
> 
> -- glen

Article: 65931
Subject: Re: negative hold time
From: Muzaffer Kal <kal@dspia.com.deletethis>
Date: Tue, 10 Feb 2004 10:26:44 GMT
Links: << >>  << T >>  << A >>
On 10 Feb 2004 01:32:42 -0800, praveenkn123@yahoo.com (prav) wrote:

>What is negative hold time and what does it specify physically? 

Hold is, as you might know, how long data needs to be stable after the
edge of the clock. There is nothing tricky about a negative hold value
which suggests electrons going back in time. It just means that
internally to the flop, the data has much more delay to the sampler
than the clock. If you think about how you fix a hold violation, it
becomes clearer: you add a delay to the data input of the flop. A flop
with negative hold requirement has some delay added to the data path
already.


Article: 65932
Subject: Re: [Altera/Quartus] Tools to regenerate block schematics from .vhd
From: Rene Tschaggelar <none@none.net>
Date: Tue, 10 Feb 2004 11:44:12 +0100
Links: << >>  << T >>  << A >>
Pszemol wrote:

> I am kind of new to FPGA design and I have to understand a circuit given
> as a set of hierarchical .vhd files (top level and two-three lower levels),
> but it would be kind of nice to see it layed out on a piece of paper...
> Is there a tool to generate schematics from vhd files to visualize vhd?

As I understood it, the schematic approach and the VHDL approach
are not  necessarily equivalent. Meaning not every line of code
can be shown as schematic.
Eg statemachines are supposed not to be displayable in schematics.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 65933
Subject: Re: Xilinx training
From: "Ian Poole" <ian.poole@doulos.delete-this-bit.com>
Date: Tue, 10 Feb 2004 10:45:41 -0000
Links: << >>  << T >>  << A >>
A search in Google for "VHDL training" brings up ourselves plus most of our
rivals. I'll leave it to the rest of the group to comment on each of us and
our various merits...

What you go for depends on your current language skills, project experience
and what you want to achieve through the course. If you're not sure, and
your employers don't have a standard training supplier, I'd suggest phoning
a few of the companies and discussing your requirements with one of their
trainers.


Ian

--
Ian Poole, Consultant and Trainer

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.


"Jakub Dudek" <jaouque@yahoo.com> wrote in message
news:c0889o$2mj$1@home.itg.ti.com...
> Hi,
>
>     Has anyone here taken VHDL training classes from Xilinx?
> http://www.xilinx.com/support/training/abstracts/adv-vhdl.htm
>
> Are they any good?/worth the money?
>
> Any review/feedback on those classes would be appreciated
>
> Jakub
>
>



Article: 65934
Subject: Re: Quartus II and Synthesis
From: johnnynorthener@yahoo.co.uk (JohhnyNorthener)
Date: 10 Feb 2004 04:07:25 -0800
Links: << >>  << T >>  << A >>
Thanks for the response guys

Article: 65935
Subject: Re: Synchronization of signals
From: "Cameron, Charles B. " <cameronc@aplcenmp.apl.jhu.edu>
Date: Tue, 10 Feb 2004 07:56:17 -0500
Links: << >>  << T >>  << A >>


ALuPin wrote:
> Hi everybody,
> 
> I have a question concerning the following:
> 
> 
> The signal 'valid_48' is one clock_cycle (48MHz) high.
> Now I want to use it in a clock domain which has a clock of 90MHz.
> 
> How can I synchronize it correctly?
> 
> I have thought of the following:
> 
> 
>  process(Clk_90)
>  begin
>     if Reset='1' then
>        valid_90 <= '0';
>        valid_h1 <= '0';
>        valid_h2 <= '0';
>        
>     elsif rising_edge(Clk_90) then
> 
>        valid_h1 <= valid_48;
>        valid_h2 <= valid_h1;
>        valid_90 <= valid_h1 and (not valid_h2);
>     end if;       
>  end process;
> 
> Are there some problems arising because of the clock-relation factor 48/90 ?
> 
> Thank you very much.
> 
> Kind regards
> 
> Andre
There is a problem:  the logical result of your code appears to be that valid_90 is always '0'.  My guess is that you were hoping for timing differences to result in a narrow pulse for valid_90.  Since you generally have little or no control over such timing, I recommend you avoid designs which depend upon it.

If this guess is wrong, then you perhaps you meant this:

ENTITY synchronize IS
	PORT(
		reset, valid_48, clk_90	: IN	STD_LOGIC;
		valid_90		: OUT	STD_LOGIC);
END synchronize;
ARCHITECTURE behavior OF synchronize IS
	SIGNAL v_90 : STD_LOGIC;
BEGIN
	synchronize_valid_90:
	PROCESS (clk_90)
	BEGIN
		IF reset = '1' THEN
		    v_90 <= '0';
		ELSIF clk_90'EVENT and clk_90 = '1' THEN
		    IF valid_48 = '1' and v_90 = '0' THEN
		        v_90  <= '1';
		    ELSIF valid_48 = '0' and v_90 = '1' THEN
		        v_90  <= '0';
		    ELSE
		        NULL;
		    END IF;
		ELSE
		    NULL;
		END IF;
	END PROCESS synchronize_valid_90;
	valid_90 <= v_90;
END behavior;

I see nothing significant about the ratio 90/48.  These intervals are nominally commensurate so the output waveform repeats periodically and sometimes the output signal is high (or low) for two 90 MHz periods rather than just for one but that seems reasonable in a synchronization circuit.

Charles B. Cameron


Article: 65936
Subject: Re: negative hold time
From: "Charles B. Cameron" <cameronc@usna.edu>
Date: Tue, 10 Feb 2004 07:59:00 -0500
Links: << >>  << T >>  << A >>


Muzaffer Kal wrote:

> On 10 Feb 2004 01:32:42 -0800, praveenkn123@yahoo.com (prav) wrote:
> 
> 
>>What is negative hold time and what does it specify physically? 
> 
> 
> Hold is, as you might know, how long data needs to be stable after the
> edge of the clock. There is nothing tricky about a negative hold value
> which suggests electrons going back in time. It just means that
> internally to the flop, the data has much more delay to the sampler
> than the clock. If you think about how you fix a hold violation, it
> becomes clearer: you add a delay to the data input of the flop. A flop
> with negative hold requirement has some delay added to the data path
> already.
> 
In case it's not obvious, the implication of this is that the input signal can change _before_ the flip-flop is clocked.  The difference in time between doing this and receiving the clock is the same as the magnitude of the negative hold time.

Charles B. Cameron


Article: 65937
Subject: Re: Quartus II taking forever to compile
From: "Kenneth Land" <kland1@neuralog1.com1>
Date: Tue, 10 Feb 2004 07:08:26 -0600
Links: << >>  << T >>  << A >>
Hi Paul,

Thanks for the reply.  I guess I was thinking more along the lines of
processing the data in 64 vs. 32 bit chunks as opposed to increasing address
space.

I guess I know little of the data structures involved in synthesis and
fitting.  I do image processing where twice the bit width means twice the
number of pixels per fetch etc.  This results in a near linear increase in
processing speed for a given clock rate.

Of course I have to go in and tweak my inner loops to operate on the larger
chunks, but well worth the payoff.

Ken

"Paul Leventis (at home)" <paul.leventis@utoronto.ca> wrote in message
news:e%WVb.28093$R6H.7213@twister01.bloor.is.net.cable.rogers.com...
> Hi Kenneth,
>
> > Is there any chance a 64bit version of Quartus will be released?
>
> We'll release a 64-bit version of Quartus when one is needed in order to
> address more memory.  Windows XP maxes out at 3 GB (with a command-line
> flag), and Linux maxes out at ~3.7 GB.  In all our testing of Stratix II,
I
> don't think I've seen any compile (even on a 2S180) that required more
than
> 2 GB of memory, and most compiles require much less than this -- and we
get
> some very stressful, pathological designs from our internal test/product
> engineering groups.  Also, as memory needs keep increasing due to larger
and
> larger chips, we strive to beat down on the memory requirements of
Quartus.
> In addition, architectural changes in Stratix II result in reduced memory
> consumption compared to the same design compiled in Stratix.
>
> So there is still plenty of room left before we _have_ to go 64-bit -- and
> we will be ready when the market needs a 64-bit version of Quartus.
>
> > I got my 15+ min. builds down to 5+ by upgrading to the fastest
available
> > cpu, but I was thinking this process might benefit from the new 64 bit
AMD
> > and upcoming Intel procs.
>
> Contrary to popular belief, the "bitness" of a processor does not
> (necessarily) equate with speed.  The primary advantage of switching to
> 64-bit computing is the increase in (easily) addressable memory that you
get
> with 64-bit pointers.  You are limited in 32-bit machines to 4 GB of
> addressable memory (minus the up to 2 GB of address space the OS
reserves).
> There are tricks to get this up higher, but aren't fun to program to.
>
> From a processing speed perspective, switching to 64-bit code may help and
> may hinder things.  It can help in those cases where you would have had to
> break up something that wanted a > 32-bit representation across multiple
> integers.  But most things fit fine in 32 bits, and promoting those
> variables to 64 bits just pollutes your data cache, effectively reducing
the
> amount of cache memory available to the processor.  And 64-bit code can be
> larger (because of larger pointers, instruction extensions, larger data
> values, etc.) thus chewing up valuable instruction/trace cache room.
> Luckily, recompiling C code to 64-bits does not change your integers to
> 64-bits -- just your pointers -- but this still has some impact on data
and
> instruction cache consumption.  I am glossing over many pros and cons of
> 32/64-bit code, but you get the idea.
>
> Intel plans to ramp the Prescott (90 nm version of P4) core up to 4 Ghz+,
> and AMD will be making Opteron/Athlon64 for years to come.  As they up the
> speed, you will get more performance on your 32-bit applications.  And you
> can bet future versions of the processors will support fast 32-bit
> processing, since it will take a LONG time before many programs make the
> switch to 64-bit.
>
> If you are interested in some early benchmarks comparing 32-bit and 64-bit
> x86 performance using a beta of Windows XP 64-bit, see
> http://www.anandtech.com/.
>
> Another bit of performance data:  http://www.speg.org/.  Do a search on
> results from "AMD Athlon" and click through to find results that were on
the
> same machine, one running 32-bit windows, the other 64-bit SuSE Linux
> w/64-bit gcc compilation.  On the few machines I looked at, the SPEC level
> was ~5% better on 32-bit.  If you look at the "VPR" component of the
SPECint
> test, this is an academic FPGA place and route tool, and it too yields
> something ~7-8% less speed on 64-bit x86.  Of course, there could be
> immaturity of compilers, different OS efficiencies, etc. in here, but
64-bit
> will be no silver bullet when it comes to performance.
>
> Regards,
>
> Paul Leventis
> Altera Corp.
>
>



Article: 65938
Subject: Re: need desperate help!
From: filippdavid@yahoo.com (filippo)
Date: 10 Feb 2004 05:23:26 -0800
Links: << >>  << T >>  << A >>
"Georgi Beloev" <gbH8SPAM@beloev.net> wrote in message 
> >
> > // ciclo scrittura ADDR
> >
> >      always @(posedge ALE)
> >
> >    ADDR <= ibuf;
> 
> This should be negedge instead of posedge - look at the timing diagrams. Or
> you can synthesize a latch that is transparent when ALE=1.
> 
> > //ciclo scrittura rst
> >
> >      always @(negedge NWR)
> >
> >       if (ADDR == 8'b0000_0000)rst <= (ibuf[0]);
> >
> >    else rst <= rst;
> 
> All "always @(negedge NWR)" statements should use posedge instead. The data
> is not valid yet on the falling edge.
> 

this are the time diagrams i got:

 WRITING CICLE

ALE          +--+
             |  |
    ---------+  +-------------------

NWR -----------------+  +-----------
                     |  |
                     +--+

DA   ----\ /-----\ /------\ /-------
     xxx  |adress |  data  | xxxxxxx
     ----/ \-----/ \------/ \-------


>  -----
> > module iobuff(da,obuf,ibuf,dir);
> >
> >     input dir;
> >
> >     inout [7:0] da;
> >
> >     input [7:0] obuf;
> >
> >     output [7:0] ibuf;
> >
> >
> >
> >     assign da = (dir) ? 8'bzzzz_zzzz : obuf;
> >
> >     assign ibuf = (dir) ? da : 8'bzzzz_zzzz;
> >
> 
> What is dir connected to? Also, I think you don't need a tristate bus for
> ibuf.
> 
> -- Georgi

Now it works (modelsim) i had to split the iobuff in two buffers: one
for ibuf and one for obuf.
I know it seems crazy , but just "assign ibuf= da;" didn' t work i had
to make a tristate buff to make it work .

I hope thursday it will work on the real FPGA ^_^

Article: 65939
Subject: Re: Partial reconfig flow
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Tue, 10 Feb 2004 21:26:12 +0800
Links: << >>  << T >>  << A >>
Following are my opinion only...

I saw WARNING:Guide:147 in every trial but I neglected it...as long as the
final assembly was routed and there was no boundary crossing...

During active module implementation, some wires  & components outside the
active module will not get placed & routed...so the error is presumingly
fine.

During active module implementation, some other wires & components outside
the active module do get placed & routed...and in two reconfigurable
modules,
the placement & routing of these wires and components may be different from
those in the fixed module...maybe the final assembly will resolve these
conflicts...
maybe this is where the WARNING:Guide:147 comes in...

I think, all my NCD files were readable in fpga_editor...I only saw the
version conversion tool failed when I tried to convert the NCD in XAPP290 to
ise 6.1...

John I guess u may need to download service park 3...that will patch the ise
to 6.1.03i...


Kelvin




"John Williams" <jwilliams@itee.uq.edu.au> wrote in message
news:c09k8m$bj5$1@bunyip.cc.uq.edu.au...
> Hi folks,
>
> I'm trying to get the modular partial reconfig flow going (as per XAPP
> 290).  Details below - if anyone has any suggestions I'm all ears!  I'm
> doing this all with ISE 6.1.02i (trying under both Linux and Windows XP,
> same behaviour/problems).
>
> As a first test, I successfully modularised my design, and implemented
> it using the modular flow described in the ISE documentation (Chapter 4
> of the Development System Reference Guide).  This all worked as expected.
>
> Next, I inserted the partial reconfig bus_macro between my two modules,
> and created a set of placement constraints that ngdbuild would be happy
> with.  My toplevel design complies with all of the guidelines and rules
> I can find in the various bits of documentation about the partial
> reconfig flow (my hard-copy of XAPP290 is very well worn!).
>
> I can perform top level initial budgeting without errors or warnings
> (except the expected "assuming such-and-such is a module").
>
> Doing active module implementation - I can MAP and PAR the individual
> modules, and export the PIMs.  PAR reports failure due to some signals
> being unrouted.  This concerned me, however I see that the same happens
> in the example distributed with XAPP290...
>
> I can perform final assembly on the pims and my toplevel, and it MAPs
> and PARs succesfully (all signals routed in final assembly
> implementation).  There is one strange message in this final PAR during
> guide file processing:
>
> WARNING:Guide:147 - Design contains an unroutable situation due to
> existing islands. This may be caused by having an invalid NCD as input.
>   Verify that the input NCD's were implemented correctly.
>
> However eventually PAR completes without errors or more warnings.
>
> Now here's the really wierd bit - if I try to load the placed and routed
> toplevel NCD file into either fpga_editor, or even bitgen, it causes
> that program to crash.  Doing it on Linux I get a segfault, and on
> windows I get the standard "error in this application".
>
> So, somehow, the tools have build such a broken NCD file that it crashes
> the other tools.  The "progressive" NCDs produced during the various
> lead-up phases seem OK - I can load them into FPGA editor etc.
>
> A couple of questions:
>
> (1) should the active module implementation phase "fail" with unrouted
> signals?  I thought the purpose of the bus_macro was to lock all of them
> down, but seeing this behaviour in XAPP290 makes me wonder.
>
> (2) Has anyone ever seen bitgen or fpga_editor choke on an NCD produced
> by the implementation tools?
>
> (3) Is there some other step I need to take to get this going?
>
> If anyone has any ideas, please let me know.
>
> Thanks,
>
> John
>



Article: 65940
Subject: Re: iteration Vs LUT table entry vs accuracy in Cordic
From: Ken Prager <prager_me_@ieee.org>
Date: Tue, 10 Feb 2004 05:52:22 -0800
Links: << >>  << T >>  << A >>
In article <40280492$0$3199$61fed72c@news.rcn.com>,
 Jerry Avins <jya@ieee.org> wrote:

> praveen wrote:
> > 
> > Please suggest a solution
> > with regards
> > praveen
> 
> Go to my web site, http://users.erols.com/, look at my article
> "Quadratic Interpolation in Forth", and even it the article itself
> gives you no ideas, there's a link at the top that may.


That link seems to be brokken--it redirects to <http://www.rcn.com/>.

KP

-- 
Remove _me_ for e-mail address

Article: 65941
Subject: Re: Is nobody using c++ and/or plugs-lib? was Re: nios c++ and ethernet [may by ot?]
From: "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca>
Date: Tue, 10 Feb 2004 14:16:03 GMT
Links: << >>  << T >>  << A >>
> This should have been done *inside* plugs.h:

Yes, it should be.  I will file a Software Problem Report on this today.

Paul Leventis
Altera Corp.



Article: 65942
Subject: Re: Synchronization of signals
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Tue, 10 Feb 2004 14:29:51 -0000
Links: << >>  << T >>  << A >>

"Cameron, Charles B. " <cameronc@aplcenmp.apl.jhu.edu> wrote in message
news:4028D4F1.2050300@aplcenmp.apl.jhu.edu...

> There is a problem:  the logical result of your code appears
> to be that valid_90 is always '0'.

No it's not.

He's using the 90MHz clock to register the valid_48 signal
into the 90MHz domain and do a rising edge detect on it.

The only thing I would do is register it in three times and use
valid_h2 and valid_h3 for the rising edge detection to help
avoid metastability problems. If you've data in parallel with
the valid signal you can pipeline it into the 90MHz clock domain
one extra time to compensate.

>
> ENTITY synchronize IS
> PORT(
> reset, valid_48, clk_90 : IN STD_LOGIC;
> valid_90 : OUT STD_LOGIC);
> END synchronize;
> ARCHITECTURE behavior OF synchronize IS
> SIGNAL v_90 : STD_LOGIC;
> BEGIN
> synchronize_valid_90:
> PROCESS (clk_90)
> BEGIN
> IF reset = '1' THEN
>     v_90 <= '0';
> ELSIF clk_90'EVENT and clk_90 = '1' THEN
>     IF valid_48 = '1' and v_90 = '0' THEN
>         v_90  <= '1';
>     ELSIF valid_48 = '0' and v_90 = '1' THEN
>         v_90  <= '0';
>     ELSE
>         NULL;
>     END IF;
> ELSE
>     NULL;
> END IF;
> END PROCESS synchronize_valid_90;
> valid_90 <= v_90;
> END behavior;


AAAAAAAAAAAAARRRRRRRRRGGGGGGGGGHHHHHHHHH I HATE mixed lower
and upper case coding, it's very hard to read through.


Nial
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk










Article: 65943
Subject: Re: Synchronization of signals
From: "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca>
Date: Tue, 10 Feb 2004 14:46:06 GMT
Links: << >>  << T >>  << A >>
Hi Andre,

> The signal 'valid_48' is one clock_cycle (48MHz) high.
> Now I want to use it in a clock domain which has a clock of 90MHz.


There are a bunch of good references on synchronizing signals across clock
domain boundaries.  Here's one reference I've found handy in the past:

http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk_rev1_1.pdf

Going from low-speed to high-speed clock domains with a single signal is
probably the easiest cross-domain transfer that can happen.  From a quick
glance at your solution, it looks okay to me (except that another reader
thinks it is wrong).  I don't think you need "valid_90" to be a registered
signal -- it's okay to put it outside the process and leave it as a
combinational function of valid_h1 and valid_h2, unless you are using it
down-stream as an asynchronous signal and thus care about it being
glitch-free.

I *think* you should add a third shift-register stage (call it valid_h0)
before the two you have.  The reason is that the 1st register could clock
the data just as the transition in the 48-Mhz domain is occuring.  The
result is a metastable flop, which you don't want to use as input to
combinational logic.  It may very well work fine as is since even a
metastable flop will settle to a 1 or 0 at some point -- except that this
added delay for settling will not be checked by the timing analyser so you
run the risk of blowing your critical path if it happens to originate on
valid_h1.  If valid_h1 only feeds an AND and then into another flop (as in
your currnet solution), the chances of this actually being a problem are
slim.  You also run the risk that the valid_h2 sampling of the metastable
signal and the valid_90 samplings see different values since the
logic/routing/etc. could have different trip-points.  By putting an extra
stage in the shift register, by the time valid_h1 samples the output of
valid_h0, it's likely that the input has settled enough that valid_h1 will
get a stable result (either '0' or '1' -- it doesn't matter).

So this is what it looks like in the end.  Warning: Haven't coded in VHDL
for a year or so, so all of this could be wrong :-)

process (clk90, reset)
    if reset = '1' then
        valid_h0 <= '0';
        valid_h1 <= '0';
        valid_h2 <= '0';
    elsif rising_edge(clk90) then
        valid_h0 <= valid_48;
        valid_h1 <= valid_h0;
        valid_h2 <= valid_h1;
    end if;
end process;
valid_90 <= valid_h1 AND NOT valid_h2;

Regards,

Paul Leventis
Altera Corp.



Article: 65944
Subject: Re: Synchronization of signals
From: "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca>
Date: Tue, 10 Feb 2004 14:53:45 GMT
Links: << >>  << T >>  << A >>
> If you've data in parallel with
> the valid signal you can pipeline it into the 90MHz clock domain
> one extra time to compensate.

You can't use this method for more than one signal crossing a clock domain.
There is no guarentee that your control signal (valid_48) and data signals
will arrive at their synchronizers at the exact same moment in time, and
thus you could have some signals sampled before they transition and others
sampled afterwards.

It may seem at first that you could do something like wait until valid_h1 =
'0' and valid_h2 = '1' to sample the data, but I believe that you can also
get wrong data in this case since valid_48 could be held high up to < 1
48-Mhz clock cycle after it was meant to be used, and thus data could have
toggled already by the time you sample it.  Not to mention synthesis/p&r
delays from data to 90-Mhz domain will be different.

In this case, you need to start using FIFOs and other techniques I don't
recall anymore.  See my other posting for PDF reference.

Paul Leventis
Altera Corp.



Article: 65945
Subject: Re: [Altera/Quartus] Tools to regenerate block schematics from .vhd files
From: fredrik_he_lang@hotmail.com (Fredrik)
Date: 10 Feb 2004 06:56:49 -0800
Links: << >>  << T >>  << A >>
Hi Pszemol,
You have the RTL view in Quartus that will short of do this for you.
RTL means that you will see it at a very basic level, flip-flops,
Luts,muxs and soforth. Alltough the RTL viewer build up a hirachy from
your VHDL files so you are going to see the top enties in the first
view anyhow. I think also some 3:party tools have this
features.(simplify?) This is a new feature as of Quartus2_ver4 so it
might not be avalible in the free version of the tool.
Cheers
Fredrik
Rene Tschaggelar <none@none.net> wrote in message news:<4028b69a$0$708$5402220f@news.sunrise.ch>...
> Pszemol wrote:
> 
> > I am kind of new to FPGA design and I have to understand a circuit given
> > as a set of hierarchical .vhd files (top level and two-three lower levels),
> > but it would be kind of nice to see it layed out on a piece of paper...
> > Is there a tool to generate schematics from vhd files to visualize vhd?
> 
> As I understood it, the schematic approach and the VHDL approach
> are not  necessarily equivalent. Meaning not every line of code
> can be shown as schematic.
> Eg statemachines are supposed not to be displayable in schematics.
> 
> Rene

Article: 65946
Subject: Re: Synchronization of signals
From: steenkmp@sunspace.co.za (Niki Steenkamp)
Date: 10 Feb 2004 07:19:25 -0800
Links: << >>  << T >>  << A >>
Hi,

Your suggestion should work.  The ratio of clocks will only become a
problem if the asynchronous signal pulsewidth becomes close to or less
than one 90MHz period.
The valid_h1 signal will have a higher probability to enter a
metastable state, which, in theory, could be a problem.  You could
place another FF in front of the queue.

Regards,
Niki



ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0402100103.2134de7a@posting.google.com>...
> Hi everybody,
> 
> I have a question concerning the following:
> 
> 
> The signal 'valid_48' is one clock_cycle (48MHz) high.
> Now I want to use it in a clock domain which has a clock of 90MHz.
> 
> How can I synchronize it correctly?
> 
> I have thought of the following:
> 
> 
>  process(Clk_90)
>  begin
>     if Reset='1' then
>        valid_90 <= '0';
>        valid_h1 <= '0';
>        valid_h2 <= '0';
>        
>     elsif rising_edge(Clk_90) then
> 
>        valid_h1 <= valid_48;
>        valid_h2 <= valid_h1;
>        valid_90 <= valid_h1 and (not valid_h2);
>     end if;       
>  end process;
> 
> Are there some problems arising because of the clock-relation factor 48/90 ?
> 
> Thank you very much.
> 
> Kind regards
> 
> Andre

Article: 65947
Subject: Re: Quartus II taking forever to compile
From: "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca>
Date: Tue, 10 Feb 2004 15:34:43 GMT
Links: << >>  << T >>  << A >>
Hi Ken,

> Thanks for the reply.  I guess I was thinking more along the lines of
> processing the data in 64 vs. 32 bit chunks as opposed to increasing
address
> space.

Many computer algorithms don't really fall into the category of processing
"chunks" of data -- CAD algorithms included.  It's more like "look at a
piece of data.  If it's this, go do that.  If not, go do this other thing
and multiply it by some other piece of data located over where this other
thing points to...".

If we wanted to (say) perform arithmetic on multiple 16- or 32-bit values at
a time, this is different from 64-bit computing, and is known as SIMD
(Single Instruction Multiple Data).  MMX & SSE are both examples of SIMD
instruction extensions to x86, and they exist in current processors.  I
believe that some compilers (Intel's, I think) will automatically vectorize
pieces of code that are handling small values one at a time and convert them
to using MMX/SSE instructions to handle multiple pieces of data
concurrently.

Some applications such as media encoding/decoding, graphics processing, etc.
which really are just doing big array manipulations or a lot of math do get
a huge benefit from performing the same operations on multiple pieces of
data in parallel.  But CAD algorithms are totally different beasts.

Regards,

Paul Leventis
Altera Corp.



Article: 65948
Subject: Re: Xilinx training
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 10 Feb 2004 07:40:53 -0800
Links: << >>  << T >>  << A >>
Ian,

Excellent advice.

Austin

Ian Poole wrote:
> A search in Google for "VHDL training" brings up ourselves plus most of our
> rivals. I'll leave it to the rest of the group to comment on each of us and
> our various merits...
> 
> What you go for depends on your current language skills, project experience
> and what you want to achieve through the course. If you're not sure, and
> your employers don't have a standard training supplier, I'd suggest phoning
> a few of the companies and discussing your requirements with one of their
> trainers.
> 
> 
> Ian
> 
> --
> Ian Poole, Consultant and Trainer
> 
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
> 
> 
> "Jakub Dudek" <jaouque@yahoo.com> wrote in message
> news:c0889o$2mj$1@home.itg.ti.com...
> 
>>Hi,
>>
>>    Has anyone here taken VHDL training classes from Xilinx?
>>http://www.xilinx.com/support/training/abstracts/adv-vhdl.htm
>>
>>Are they any good?/worth the money?
>>
>>Any review/feedback on those classes would be appreciated
>>
>>Jakub
>>
>>
> 
> 
> 


Article: 65949
Subject: Re: iteration Vs LUT table entry vs accuracy in Cordic
From: Jerry Avins <jya@ieee.org>
Date: Tue, 10 Feb 2004 10:45:27 -0500
Links: << >>  << T >>  << A >>
Jerry Avins wrote:

> praveen wrote:
> 
>> Hello,
>> I wanted the relationship between the number of iteration vs LUT table
>> entry.
>> Because i wanted to estimate the arc tan to a accuracy of 1
>> microradians.
>> In my simulation i found that even if the iteration is around 25
>> iteration i could not achieve the 1 microradian accuracy.
>>
>> My LUT i have represented using 32 bit and the two number whos atan is
>> to be obtained is also 32 bit(all fixed point).
>>
>> Please suggest a solution
>> with regards
>> praveen
> 
> 
> Go to my web site, http://users.erols.com/, look at my article
> "Quadratic Interpolation in Forth", and even it the article itself
> gives you no ideas, there's a link at the top that may.
> 
> Jerry

Copy/paste mysteriously failed. (Operator error, but how?) The correct
URL is http://users.erols.com/jyavins/ or http://users.rcn.com/jyavins/
or even http://users.starpower.net/jyavins/

Jerry
-- 
Engineering is the art of making what you want from things you can get.
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ




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