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Messages from 66050

Article: 66050
Subject: Re: Spartan-3 shipping, or perhaps not!
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 11 Feb 2004 18:51:18 -0500
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> 
> Nial,
> 
> FAEs have the documents, so I would suggest they put in the request to
> find out from them.

I can say that I was promised to have parts in my hand by November and I
am still waiting. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 66051
Subject: Re: negative hold time (Typ/max)
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 11 Feb 2004 18:56:54 -0500
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> 
> Peter Alfke wrote:
> > rickman wrote:
> >
> >> For example, when I am looking for max static current
> >>draw over temperature and I am given a typical current at 25C.  What is
> >>the designer trying to tell me?
> >
> >
> > Here is an explanation for that typical number:
> > In the olden days, static current was extremely low, microamps or a few
> > milliamps, and was usually swamped out by the dynamic power consumption.
> >
> > So the argument went this way:
> > If the part is hot because it is working hard, running with a fast
> > clock, nobody really cares about the leakage current. Even if it's
> > higher than the room temp spec, it is still an insignificant part of the
> > total current that made the chip get so hot.
> >
> > When the part is not working hard, it will be near room temperature, and
> > because of the lack of dynamic power, the static current is a standby
> > value, and may be important. And everybody knows that leakage current
> > doubles for every 10 degree C increase in temperature. (The newly
> > increased leakage current is actually rising less dramatically).
> >
> > With the recent dramatic increase in leakage current (by orders of
> > magnitude), that old reasoning may have to be revised...
> 
> ... and designs need to consider complete power removal of those hungry
> devices during sleep times, which moves away from a single chip solution..
> 
> >
> > Peter Alfke
> 
>   I think rickman was asking about TYP vs MAX ?
> Typical appears on a data sheet for many reasons :
> - It's a better sounding number  (don't laugh..)
> - It's easier/quicker to derive than a MAX corner value.
> - It's also usefull for average battery life calculations.

No, I was not asking about just the difference between TYP and MAX, my
issue is TYP at 25C vs. anything at full temp range.  Static current
normally goes *way* up as you approach 85C and gets serious as you get
near 125C on automotive temp parts.  Try specing the max life of a
battery powered RTC over a temp range of -40C to 125C.  


> but sometimes, customers want to know worst case battery life,
> and they may even be using batteries good enough to spec that over
> temperature. So they need a corresponding chip value.
> 
> If the spec omits MAX, the designer could be trying to say
> any or all of :
> - The silicon is so new, we don't know this number yet

Normally they give a footnote about this saying this is "preliminary"
and will be filled out later. 

> - Our test coverage could not guarantee this on all devices

This is also normally stated when true. 


> - We do not bother to test it

Same as above. 

> - A few devices have this very high, and we are unsure why

Now we are getting to my concern. 

> - Why does that number matter again ?

If they are saying that, then I need a new supplier. :)

 
>   The new Lattice 4000 family, and Xilinx Coolrunner II do seem
> to have good Typ, and Max static Icc specs, so perhaps
> those customers are more demanding ?
> 
>   Personally, I prefer to see Icc vs Temp plots, and in the old
> days of data sheets, they would plot Typ and Max on the same graph!

This was just one example of poorly spec'd data.  I have also seen poor
specs in timing and functionality.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 66052
Subject: Re: Spartan-3 shipping, or perhaps not!
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 11 Feb 2004 16:10:38 -0800
Links: << >>  << T >>  << A >>
Rick,

What part, and by whom?

I like to check on things when I see an issue such as yours,

Austin

rickman wrote:
> Austin Lesea wrote:
> 
>>Nial,
>>
>>FAEs have the documents, so I would suggest they put in the request to
>>find out from them.
> 
> 
> I can say that I was promised to have parts in my hand by November and I
> am still waiting. 
> 


Article: 66053
Subject: Re: negative hold time (Typ/max)
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 11 Feb 2004 16:17:16 -0800
Links: << >>  << T >>  << A >>
There is another aspect: 
When we spec the max value, we have to guarantee it. That can hurt when
one of a thousand pins has a leakage current of 11 uA. It feels bad to
throw away a multi-$100 part for that reason especially when it is in
short supply.
On the other hand, a 10 uA per pin spec looked silly on the XC3000L,
where the max Icc was spec'ed as 50 uA. We solved this by connecting all
pins together in the tester, and still guaranteeing 10 uA total for all
of them together.  Some specifications have a very wide margin, but it
is expensive to measure extremely low currents. That's where "typical" helps...

I was pointing out that high junction temperature and a tight leakage
current spec hardly ever are meaningful together.
Peter Alfke

Jim Granville wrote:
> 
> Peter Alfke wrote:
> > rickman wrote:
> >
> >> For example, when I am looking for max static current
> >>draw over temperature and I am given a typical current at 25C.  What is
> >>the designer trying to tell me?
> >
> >
> > Here is an explanation for that typical number:
> > In the olden days, static current was extremely low, microamps or a few
> > milliamps, and was usually swamped out by the dynamic power consumption.
> >
> > So the argument went this way:
> > If the part is hot because it is working hard, running with a fast
> > clock, nobody really cares about the leakage current. Even if it's
> > higher than the room temp spec, it is still an insignificant part of the
> > total current that made the chip get so hot.
> >
> > When the part is not working hard, it will be near room temperature, and
> > because of the lack of dynamic power, the static current is a standby
> > value, and may be important. And everybody knows that leakage current
> > doubles for every 10 degree C increase in temperature. (The newly
> > increased leakage current is actually rising less dramatically).
> >
> > With the recent dramatic increase in leakage current (by orders of
> > magnitude), that old reasoning may have to be revised...
> 
> ... and designs need to consider complete power removal of those hungry
> devices during sleep times, which moves away from a single chip solution..
> 
> >
> > Peter Alfke
> 
>   I think rickman was asking about TYP vs MAX ?
> Typical appears on a data sheet for many reasons :
> - It's a better sounding number  (don't laugh..)
> - It's easier/quicker to derive than a MAX corner value.
> - It's also usefull for average battery life calculations.
> 
> but sometimes, customers want to know worst case battery life,
> and they may even be using batteries good enough to spec that over
> temperature. So they need a corresponding chip value.
> 
> If the spec omits MAX, the designer could be trying to say
> any or all of :
> - The silicon is so new, we don't know this number yet
> - Our test coverage could not guarantee this on all devices
> - We do not bother to test it
> - A few devices have this very high, and we are unsure why
> - Why does that number matter again ?
> 
>   The new Lattice 4000 family, and Xilinx Coolrunner II do seem
> to have good Typ, and Max static Icc specs, so perhaps
> those customers are more demanding ?
> 
>   Personally, I prefer to see Icc vs Temp plots, and in the old
> days of data sheets, they would plot Typ and Max on the same graph!
> 
> -jg

Article: 66054
Subject: Re: Xilinx Platform Flash Prom
From: Lasse Langwadt Christensen <langwadt@ieee.org>
Date: Thu, 12 Feb 2004 01:30:40 +0100
Links: << >>  << T >>  << A >>
Pete wrote:
> This may be an odd question but here goes... 
> 
>   I would like to use the JTAG chain to program Xilinx's Virtex-II
> fpga and the Platform Flash ISP Configuration PROM.  OK, that's not a
> problem as it's detailed in document DS123 (v2.2).  However, I would
> like to add a second Platform Flash PROM in the same chain as the
> Virtex-II and it's config PROM.  This second PROM would be used to
> hold general purpose data (ie. not FPGA config data).  I would like to
> connect this PROM to unused I/O of the FPGA which would then reset the
> PROM and pull data out of it serially to be used in other parts of the
> product we're developing.
> 
> Each "box" we're designing will have analog control bits that need to
> be tweaked when the unit is sealed up.  The only access I have to the
> PROM is through the JTAG interface.  I was wondering if anyone has
> seen any app notes detailing this sort of interface/design.
> 
> Pete

Should be straight forward, not much different from using two small
proms to configure one FPGA, except that one of the proms isn't 
connected to the configuration pins of the FPGA.

 From the JTAG side it'll just be a chain of 2 proms and an FPGA, one
programmed with the fpga configuration the other with you general
purpose data.

The prom connected to the configuration pins on the FPGA configures
the FPGA, the prom connected to I/O's does nothing unless  you drive
the pins  ..

-Lasse


Article: 66055
Subject: Re: negative hold time (Typ/max)
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 12 Feb 2004 14:05:48 +1300
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> There is another aspect: 
> When we spec the max value, we have to guarantee it. That can hurt when
> one of a thousand pins has a leakage current of 11 uA. It feels bad to
> throw away a multi-$100 part for that reason especially when it is in
> short supply.
> On the other hand, a 10 uA per pin spec looked silly on the XC3000L,
> where the max Icc was spec'ed as 50 uA. We solved this by connecting all
> pins together in the tester, and still guaranteeing 10 uA total for all
> of them together. 

Sounds a good solution..

 > Some specifications have a very wide margin, but it
> is expensive to measure extremely low currents. That's where "typical" helps...
> 
> I was pointing out that high junction temperature and a tight leakage
> current spec hardly ever are meaningful together.
> Peter Alfke

It depends on the process, and device.
Here are some real numbers, as an example (appologies for the brand)

ispMACH 4032Z
ICC  Standby Power Supply Current
                         TYP  MAX
Vcc = 1.8V, TA =  25C  10    - A
Vcc = 1.9V, TA =  70C  13   20 A
Vcc = 1.9V, TA =  85C  15   25 A
Vcc = 1.9V, TA = 125C  22    - A

My Comments :
These are  micro-amp figures, so are in the region of
what was considered classic leakage, but they are a little
better behaved - not log related.

Here, Iq only climbs slowly with temp,
and the ratio or margin of MAX:TYP is relatively low.
( under 2:1 )

That means either the process control is very good, or
that there is a yield hit in meeting the MAX corner.

To me this is (unusually) well spec'd. One can see a
room temp/average Vcc value, for nominal calculations,
and one can also see a choice of upper corner values,
that show both the temp/Vcc effect alone, and
also the process corner effect.

-jg



Article: 66056
Subject: Re: Xilinx Platform Flash Prom
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 11 Feb 2004 17:13:19 -0800
Links: << >>  << T >>  << A >>
Have you thought of using only one common FlashROM ?
Alternatively, you could use a little 32 kbit EEPROM in an 8-pin minidp,
using a 2-wire interface for reading and writing. 
A friend of mine did that, controlled by an FPGA-internal PicoBlaze that
is performing many other control functions already...
Peter Alfke

Lasse Langwadt Christensen wrote:
> 
> Pete wrote:
> > This may be an odd question but here goes...
> >
> >   I would like to use the JTAG chain to program Xilinx's Virtex-II
> > fpga and the Platform Flash ISP Configuration PROM.  OK, that's not a
> > problem as it's detailed in document DS123 (v2.2).  However, I would
> > like to add a second Platform Flash PROM in the same chain as the
> > Virtex-II and it's config PROM.  This second PROM would be used to
> > hold general purpose data (ie. not FPGA config data).  I would like to
> > connect this PROM to unused I/O of the FPGA which would then reset the
> > PROM and pull data out of it serially to be used in other parts of the
> > product we're developing.
> >
> > Each "box" we're designing will have analog control bits that need to
> > be tweaked when the unit is sealed up.  The only access I have to the
> > PROM is through the JTAG interface.  I was wondering if anyone has
> > seen any app notes detailing this sort of interface/design.
> >
> > Pete
> 
> Should be straight forward, not much different from using two small
> proms to configure one FPGA, except that one of the proms isn't
> connected to the configuration pins of the FPGA.
> 
>  From the JTAG side it'll just be a chain of 2 proms and an FPGA, one
> programmed with the fpga configuration the other with you general
> purpose data.
> 
> The prom connected to the configuration pins on the FPGA configures
> the FPGA, the prom connected to I/O's does nothing unless  you drive
> the pins  ..
> 
> -Lasse

Article: 66057
Subject: Re: debug with opb mdm for microblaze system
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Thu, 12 Feb 2004 12:57:47 +1000
Links: << >>  << T >>  << A >>
Frank van Eijkelenburg wrote:
> Hi,
> 
> I am trying to debug a microblaze system with use of the opb mdm device. I
> am able to connect to the mdm target and after being connected, I start a
> gdb session:
> 
>  XMD% start mb-gdb my_mblaze/code/executable.elf

> What is the relation between gdb and xmd?

XMD connects with the microblaze hardware, either via the JTAG or serial 
port.  It can be used in two main ways for debugging.

1- As a manual debugging interface, with commands like load, run, stop, etc.

2. As a remote server to gdb.  In this role, you start XMD and connect 
it to the microblaze hardware.  Then, you start mb-gdb, which connects 
to XMD.  You then do all of your debugging through the gdb interface.

Try starting XMD and mb-gdb from different xygwin shells, I remember 
having problems with that in the past.

Hope this is useful,

John


Article: 66058
Subject: Re: Partial reconfig flow - Aaaarrrrgggghhhh! I am dead!!!
From: "Tungsten-W" <kelvin8157@hotmail.com>
Date: Thu, 12 Feb 2004 12:48:29 +0800
Links: << >>  << T >>  << A >>
Hi, Sean:

Have you seen this type of error or not? I call it Error Of Ghost...

My design is simple, A+B and A+C...A has 3000+ slices, A's AREA_GROUP has 1
DCM, 14 BUFG, plus A.
B & C uses two clocks from BUFG...

A, B, C were implemented and published...A+C was assembled, HOWEVER! A+B
gave me this error...I have
seen this errors every now and then but I simply can't find an answer.

ERROR:Place - The following 1 components are required to be placed in a
specific
   relative placement form. The required relative coordinates in the RPM
grid
   (that can be seen in the FPGA-editor) are shown in brackets next to the
   component names. Due to placement constraints it is impossible to place
the
   components in the required form.     SLICE modulator/_n0030 (0, 0)
            Constrained by statement: COMPGRP "MODULATE.SLICE" LOCATE = SITE
   "SLICE_X0Y191:SLICE_X43Y0" LEVEL 4 ;

Thank you for reading...

Best Regards,
Kelvin


Sean Durkin <23@iis.42.de> wrote in message news:40289598$1@news.fhg.de...
> John Williams wrote:
> > A couple of questions:
> > (1) should the active module implementation phase "fail" with unrouted
> > signals?  I thought the purpose of the bus_macro was to lock all of them
> > down, but seeing this behaviour in XAPP290 makes me wonder.
> This is normal. When you implement a single module with the routing
> restricted to module boundaries by the "MODE = RECONFIG"-constraint, you
> can't route signals that belong to other modules or to the toplevel.
> E.g., if you have bus macro communication from lets say the left module
> to the right, and try to implement the left module, you can't route the
> signals coming out of the bus macro on the right side, hence these are
> reported as unrouted. Same applies to open signals (like not connected
> busmacro pins) and top-level-logic signals, if any. So at least that is
> nothing to worry about.
>
> You can open the corresponding .NCD in FPGA Editor and let it list the
> unrouted nets. You'll find that all these signals are either not
> connected, or belong to another module in some way.
>
> > (2) Has anyone ever seen bitgen or fpga_editor choke on an NCD produced
> > by the implementation tools?
> Yes, this happens to me regularly... the entire design flow runs through
> without any error messages or unusual warnings, but in the end I get an
> .NCD that can neither be opened in FPGA Editor nor be converted to a
> bitfile. The main problem is that I cannot reproduce this behaviour, so
> I haven't opened a webcase for this yet. I think that even though the
> Xilinx support guys are without a doubt very competent, it's best if you
> can give them a simple as possible test design to reproduce the problem
> reliably. That way, they can get into it more easily.
>
> > (3) Is there some other step I need to take to get this going?
> Yes: Pray to the gods of Virtex, and a human sacrifice every now and
> then has been known to help was well... :)
>
> I've been working on partial reconfiguration for some months now, and
> run into new problems on a daily basis. I've seen so many "FATAL_ERROR"
> and "INTERNAL ERROR"-messages, that I could probably keep all of Xilinx
> support busy for a decade. The biggest problem is that there is no
> pattern behind this. Sometimes it works, most of the time it doesn't. If
> I find a combination of modules and cores inside the modules that works,
> it stops working as the moon shifts phases or I change the tiniest of
> things.
>
> Let's just face it: Partial reconfiguration is a market niche, purely
> academical, and the support in the tools just plain sucks. It works for
> simple designs with few modules, but as soon as it gets a little
> interesting the tools simply can't cope. It gets a tiny little bit
> better from ISE to ISE, but unfortunately new bugs are introduced as
> well. Just found one in ISE6.1 that sometimes causes top level logic to
> be placed incorrectly und makes par fail in the final assembly stage. No
> workaround available, no general rules as to what you can do to avoid
> it. Will probably be fixed in one of the first service packs for ISE6.2,
> which isn't even released yet. Bugger...
>
> But enough rambling and let's get back to your problem: The error
> message you get occured to me once. Basically it suggests that some
> components of a module have been placed outside of module boundaries
> somehow. I think this happened to me when I changed the area constraints
> of my modules causing the bus macros to be completely inside one of the
> modules. If that's not the problem in your case, I suggest you check the
> .NCD-files for each of the modules in PACE or Floorplanner and see if
> any components may have been misplaced.
>
> Other than that, it might help to just start over. If you do exactly the
> same thing twice with the same settings, results will vary considerably.
>
> --
> Sean Durkin
> Fraunhofer Institute for Integrated Circuits (IIS)
> Am Wolfsmantel 33, 91058 Erlangen, Germany
> http://www.iis.fraunhofer.de
>
> mailto:23@iis.42.de
> ([23 , 42] <=> [durkinsn , fraunhofer])



Article: 66059
Subject: Re: Sine Wave Generation
From: Ray Andraka <ray@andraka.com>
Date: Thu, 12 Feb 2004 00:13:03 -0500
Links: << >>  << T >>  << A >>
Depends on the number of phase angles you need to have.  For example, if you
sample the sine so that its frequency is 1/4 the sample rate, you only have 1,0,
and -1 for values.  If your sample rate is not phase locked to the sine,
however, you may need a very large number of phase angles.  In that case, it may
be better to use a computed sine using either CORDIC or one of several other
approximation methods.

SneakerNet wrote:

> Hi all
>
> I need some help with regards to generating a sine wave. I thought abt this
> problem and some thoughts that came to mind are as follows:
> 1. Generate sine values using spreadsheet
> 2. Store these values either in ROM or make a table withing VHDL
> 3. Write VHDL code and output these values.
>
> My question is:
> Is it better to store these values in ROM (eg. LUT) or directly hardcode the
> values.
> Is there a website that will explain or give more explanation in this area.
>
> Cheers

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 66060
Subject: Re: Xilinx Platform Flash Prom
From: ramntn@yahoo.com (ram)
Date: 11 Feb 2004 21:33:32 -0800
Links: << >>  << T >>  << A >>
Pete,
 Have you looked at the schematic for the board,sometimes you might
get a way to access the PROM ;other than that,I dont think it is
possible to access PROM.
I was once trying to do that to load two different config bits and use
them as and when needed, but the solution i got was using System ACE
controller.
you might want to check that out.
Ram

Article: 66061
Subject: Re: XC2V2000 + System Ace + Reconfig
From: ramntn@yahoo.com (ram)
Date: 11 Feb 2004 21:45:35 -0800
Links: << >>  << T >>  << A >>
Joerg,
  you might want to have a look at the c file at the following
location in your hard drive
<home Dir>:\EDK\sw\iplib\drivers\sysace_v_1_00_a\examples.
I used the low level config example to reconfigure the board.
Hope this helps
Ram
Joerg Ritter <ritter@informatik.uni-halle.de> wrote in message news:<c02qqe$img$1@mlucom4.urz.uni-halle.de>...
> Hi,
> we tried to reconfigure a VirtexII using the Xilinx Multimedia Demoboard.
> 
> The configuration can be done using CF-Card and System-ACE (bye the way, 
> how do you pronounce ACE, A-C-E ? ) or via JTAG.
> 
> The MPU port of the System-ACE is connected to the Virtex device.
> We want to initiate a reconfiguration from the FPGA itself. In order to 
> do that, we send a byte to the CONTROLREG register of the System-ACE 
> using the MPU port.
> In this way we set the FORCECFGMODE bit and the CFGSTART bit to 1 at the 
> same time.
> 
> Unfortunately the reconfiguration doesn't start.
> 
> Any ideas?
> 
> 
> Thanks
> 
> Joerg

Article: 66062
Subject: regarding opto isolators
From: praveenkn123@yahoo.com (prav)
Date: 11 Feb 2004 22:05:28 -0800
Links: << >>  << T >>  << A >>
Hi all,

I was studying some board schematics. In this there are some clocks
coming from external world . Before these clocks are connected to the
FPGA pins they pass through an opto isolator.Could any body help me
out why the opto isolators are really required .

rgds,
prav

Article: 66063
(removed)


Article: 66064
Subject: Re: JAM and Xilinx/Altera CPLDs
From: armcc@lycos.com (Andre)
Date: 11 Feb 2004 23:56:40 -0800
Links: << >>  << T >>  << A >>
rkruger@altera.com (Rob Kruger) wrote:
> 
> The free Quartus II Web Edition software does output .jam files. You
> enable this by selecting Assignments -> Device -> Device and pin
> options -> programming files tab.
> 

Hmmm, I'm sure I tried that but the check boxes were always grayed out
??

I even tried to manually edited the project file to enable the missing
programming file formats, but never managed to generate a .jam or .jbc
file.

Article: 66065
Subject: Re: negative hold time
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 12 Feb 2004 08:28:14 GMT
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> Let me blame T.I. for inventing (in the late 'sixties) the stupid name
> "Hold Time", when we are really talking about the latest possible
> instant of Set-Up Time.

(snip)

> The earliest possible position is specified as Set-up-time. The latest
> possible position is (unfortunarely) specified as Positive Hold Time if
> it is later than the clock edge, and as Negative Hold Time if it is
> before the clock edge.

> It would be so much nicer if we used only one parameter name, and called
> the two extremes the max and the min value of the set-up time. I lost
> that battle 30 years ago. It still smarts every time I hear "Hold Time"

By having two parameters you can have a typical for both, and also
a max/min (whichever is applicable).

Now, I suppose the names could be more symmetric.  What is the opposite 
of setup?  Maybe takedown, or something like that?   Maybe release is
the opposite of hold.  I don't think setup/takedown or release/hold make
very good pairs.   It might be that I am too used to setup/hold by now.

-- glen


Article: 66066
Subject: How many PCB layers ?
From: armcc@lycos.com (Andre)
Date: 12 Feb 2004 00:29:48 -0800
Links: << >>  << T >>  << A >>
How many layers are normally needed for PCBs using low cost FPGAs ??

I've just been told by a supposed board layout expert that the 256 pin
BGA version of a Cyclone EP1C6 would require an 8 layer board
(apparently having the entire underside of the device covered by balls
with no free space at the centre makes signal routing a big problem).

Is this really true ??

Article: 66067
Subject: Re: How many PCB layers ?
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Thu, 12 Feb 2004 08:36:06 +0000 (UTC)
Links: << >>  << T >>  << A >>
Andre <armcc@lycos.com> wrote:
: How many layers are normally needed for PCBs using low cost FPGAs ??

: I've just been told by a supposed board layout expert that the 256 pin
: BGA version of a Cyclone EP1C6 would require an 8 layer board
: (apparently having the entire underside of the device covered by balls
: with no free space at the centre makes signal routing a big problem).

With 0.3 mm drills, 0.6 mm vias and 0.14 mm lines spaces, the FBGA256 should
be routable with a ground plane on 4 layers...

More layers will give you supply layers while with four layers you have to
route the supplies with what is left after the signal routing.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 66068
Subject: debug sdram application with use of xmdstub (microblaze)
From: "Frank van Eijkelenburg" <someone@work.com>
Date: Thu, 12 Feb 2004 09:39:53 +0100
Links: << >>  << T >>  << A >>
Hi,

I am trying to debug my application in sdram with use of the "xmdstub
method". After downloading the application with "dow", I can not single step
through my code. I even can't read from memory. Output in xmd:

XMD% dow appl/appl.elf 0x80000000
Unable to Open File : appl/appl.elf
XMD% pwd
c:/
XMD% dow proj/ATM03001/example_7/appl/appl.elf 0x80000000
start addr in the ELF program hdr is 0x80000000
XMD% stp
Unable to Read register : R1
Unable to Read register : R1
Unable to Read register : R1
Unable to Read register : R1
Cannot read from target

XMD% mrd 0x80000000
Cannot read from target

XMD% mrd 0
Cannot read from target

XMD%

Any suggestions of what could be the reason for this behaviour?? BTW, my
final application (appl.elf) is compiled with option:

LFLAGS = -Wl,-defsym -Wl,_TEXT_START_ADDR=0x80000000

TIA,
Frank



Article: 66069
Subject: Re: Sine Wave Generation
From: "Gregory C. Read" <readgc.invalid@hotmail.com.invalid>
Date: Thu, 12 Feb 2004 08:56:33 GMT
Links: << >>  << T >>  << A >>
If you need more than a few points, a ROM would be a better idea. I did this
to generate a sine wave (via a D/A) for an all digital LVDT synchronous
demodulation circuit. The beauty of using ROM is you can store many points,
including multiple frequencies by using the upper address lines to select a
different set of values.

BTW, I used C and/or Visual Basic to generate the values, writing them
directly to a binary file, then using the file to program the ROM.

-- 
Greg
readgc.invalid@hotmail.com.invalid
(Remove the '.invalid' twice to send Email)


"SneakerNet" <nospam@nospam.org> wrote in message
news:PdzWb.41614$9k7.859740@news.xtra.co.nz...
> Hi all
>
> I need some help with regards to generating a sine wave. I thought abt
this
> problem and some thoughts that came to mind are as follows:
> 1. Generate sine values using spreadsheet
> 2. Store these values either in ROM or make a table withing VHDL
> 3. Write VHDL code and output these values.
>
> My question is:
> Is it better to store these values in ROM (eg. LUT) or directly hardcode
the
> values.
> Is there a website that will explain or give more explanation in this
area.
>
> Cheers
>
>



Article: 66070
Subject: Re: Sine Wave Generation
From: Andrew Greensted <ajg112@ohm.york.ac.uk>
Date: Thu, 12 Feb 2004 08:58:11 +0000
Links: << >>  << T >>  << A >>
You could use a single digital output to produce a square wave at the 
fundamental frequency, then filter out the harmonics to produce a sinewave.

It wouldn't be the most flexible solution, i.e. Frequency variation is 
dependant on the filter, but it would save you a lot of hardware on your 
FPGA.

Ray Andraka wrote:
> Depends on the number of phase angles you need to have.  For example, if you
> sample the sine so that its frequency is 1/4 the sample rate, you only have 1,0,
> and -1 for values.  If your sample rate is not phase locked to the sine,
> however, you may need a very large number of phase angles.  In that case, it may
> be better to use a computed sine using either CORDIC or one of several other
> approximation methods.
> 
> SneakerNet wrote:
> 
> 
>>Hi all
>>
>>I need some help with regards to generating a sine wave. I thought abt this
>>problem and some thoughts that came to mind are as follows:
>>1. Generate sine values using spreadsheet
>>2. Store these values either in ROM or make a table withing VHDL
>>3. Write VHDL code and output these values.
>>
>>My question is:
>>Is it better to store these values in ROM (eg. LUT) or directly hardcode the
>>values.
>>Is there a website that will explain or give more explanation in this area.
>>
>>Cheers
> 
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
> 
> 


-- 
Andrew Greensted            Department of Electronics
Bio-Inspired Engineering    University of York, UK

Tel: +44(0)1904 432379      Mailto: ajg112@ohm.york.ac.uk
Fax: +44(0)1904 433224      Web: www.bioinspired.com

Article: 66071
Subject: Re: How many PCB layers ?
From: "John Adair" <newsreply@loseinspace.co.uk>
Date: Thu, 12 Feb 2004 08:59:40 -0000
Links: << >>  << T >>  << A >>
If you were using Xilinx I would point you here
http://support.xilinx.com/bvdocs/appnotes/xapp157.pdf .

John Adair
Enterpoint Ltd.

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.

"Andre" <armcc@lycos.com> wrote in message
news:ae5c06e9.0402120029.4ea5405d@posting.google.com...
> How many layers are normally needed for PCBs using low cost FPGAs ??
>
> I've just been told by a supposed board layout expert that the 256 pin
> BGA version of a Cyclone EP1C6 would require an 8 layer board
> (apparently having the entire underside of the device covered by balls
> with no free space at the centre makes signal routing a big problem).
>
> Is this really true ??



Article: 66072
(removed)


Article: 66073
Subject: Re: Pricing, 101
From: steve41@totalise.co.uk (Steve)
Date: 12 Feb 2004 01:07:57 -0800
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote in message news:<402AA3E9.E5A27166@xilinx.com>...
> The Columbia Encyclopedia describes oligopoly as: 
> ...the control of supply by a few producers...or by agreements among
> members of an industry to restrain price competition...
> 
> Does that describe your impression of the relationship between X and A ?
>  Wow !


I prefer the majority of the definitions on here:

http://www.onelook.com/?w=oligopoly&ls=a

The quick definition on that page sums up my understanding:

"noun:   (economics) a market in which control over the supply of a
commodity is in the hands of a small number of producers and each one
can influence prices and affect competitors"

You don't describe the relationship between X and A like the above
definition? Wow!


--
Steve

Article: 66074
Subject: Re: Pricing, 101
From: steve41@totalise.co.uk (Steve)
Date: 12 Feb 2004 01:23:36 -0800
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> wrote in message news:<402ABE46.861C779A@yahoo.com>...

> Hey Steve, why don't you get off the soapbox.  What you are doing is not
> getting you anywhere and is starting to tick me off.  Until you give a
> call to your distributor and *ask* what price you can get, I don't want
> to listen to your rants.  


So far in this thread I've been accused of not understanding
economics, pricing or capitalism; seemingly just because I've had the
audacity to question Xilinx's low quantity prices. Basically, if
they're going to patronise me then I'm not going to just sit here
quietly and take it.


--
Steve



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