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Messages from 65225

Article: 65225
Subject: systemc download page?
From: "T. Irmen" <tirmen@gmx.net>
Date: Thu, 22 Jan 2004 16:52:50 +0100
Links: << >>  << T >>  << A >>
Hi,

I tried to register at www.systemc.org .

There is no email to confirm .

Does all the OSCI members delete the O in their name?

Does anybody know whats going on there?

kind regards,
thomas



Article: 65226
Subject: Why is router software not multi-threaded?
From: petersommerfeld@hotmail.com (Peter Sommerfeld)
Date: 22 Jan 2004 08:01:56 -0800
Links: << >>  << T >>  << A >>
Excuse my ignorance if there is an obvious answer ...

Is it true that the routing algorithms used in Altera's and Xilinx'
tools are single-threaded? If so, what is the primary difficulty with
making them multi-threaded? Is the algorithm particularly difficult to
partition into parallel units? Or has it simply not been a priority
for companies making the tools?

Now that some of the projects I am working on are taking quite a while
to fit, I'm thinking it would be nice to parcel out a fit between 5
machines sometime in the future when/if the software supports it.

-- Pete

Article: 65227
Subject: Re: How can I have multiple drivers of one inout port?
From: Ralf Hildebrandt <Ralf-Hildebrandt@gmx.de>
Date: Thu, 22 Jan 2004 17:05:18 +0100
Links: << >>  << T >>  << A >>
f'up comp.lang.vhdl set

cruzin wrote:

> I am trying to connect the bidirectional ports of two components to
> one bidirectional set of pins on my FPGA. Is it possible to do this in
> VHDL?

Take tri-state drivers

process(enable,some_signal)
begin
if (enable='1') then
	target_signal<=some_signal;
else	target_signal<=(others=>'Z');
end if;
end process;

target_signal has to be of std_logic(_vector), because it has to be 
resoled (multiple drivers).

Take care, that *only one* of these tri-state-drivers are activated at a 
time.

Take care, that everytime *at least one* driver is active (otherwise 
target_signal would float).


Think about providing these enable-signals to the tri-state-drivers. 
E.g. if you have several memory blocks, the address may decide, which 
block is allowed to drive target_signal -> the enable-signals can be 
generated thorugh combinational logic out of the address.


Ralf


Article: 65228
Subject: Re: Post-Place & Route simulation with MicroBlaze
From: PO Laprise <pl_N0SP4M_apri@cim._N0SP4M_mcgill.ca>
Date: Thu, 22 Jan 2004 16:16:56 GMT
Links: << >>  << T >>  << A >>
arkaitz wrote:

> configuration testbench_conf of system_tb_system_vhd_tb is
>   for behavior
>     for uut1 : top_level
>       for structure
>         for uut2: mb_blaze
>           for structure
>             for all: instr_mem_wrapper use configuration
> work.instr_mem_conf;
>             end for;
> 	  end for;
> 	end for;
>       end for;
>     end for;
>   end for;
> end testbench_conf;
> 
> 
> The problem comes here. When I ask ISE to simulate the P&R model it
> generates a file called "top_level_timing.vhd" which hasn't got any
> hierarchy, so obvioulsy the configuration block generates some
> compilation errors.
> 
> Is there any other way to assign the contents of the instruction set
> to the  blockram of MicroBlaze?

If you ask XPS to generate the timing model for you, you can use their 
configuration to know what the hierarchical names of the BRAMs are (and 
their contents).  When you synthesize this in PNav, chances are that the 
hierarchy will simply get flattened out by replacing (for example) 
"system/sub" with "system_sub".  You can therefore retrace the instances 
in "top_level_timing.vhd" and "flatten" your configuration accordingly.

Take the appended code for example (pulled from an actual project). 
System_top is my my system wrapper, system is the timing model generated 
by XPS.  My MBlaze was the top module, but I expect all this should 
change is that your blockRAMs would be called "mb_blaze_bram1_bram1..." 
instead of "bram1_bram1...".  Good luck :)

-- 
Pierre-Olivier

-- to email me directly, remove all _N0SP4M_ from my address --

--------------------------------------------------------------------
library simprim;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ddr_fsl_v1_00_a;
use ddr_fsl_v1_00_a.ddr_sdr_conf_pkg.all;

entity system_top is
end system_top;

architecture struct of system_top is

   component MT46V16M16
   (...)
   end component;

   component system
   (...)
   end component;

begin
   (...)
   inst_MT46V16M16: MT46V16M16
     port map(
     (...)
     ); --end MT46V16M16;

   inst_system: system
     port map(
     (...)
     ); --end system;
end struct;

configuration system_conf of system_top is
   for struct
     for inst_system : system
       use entity work.system(STRUCTURE);
       for STRUCTURE
         for bram1_bram1_ramb16_s4_s4_0 : x_ramb16_s4_s4
           use entity simprim.x_ramb16_s4_s4(x_ramb16_s4_s4_v)
           generic map(
             INIT_00 =>
             (...)
         end for;
           for bram1_bram1_ramb16_s4_s4_1 : x_ramb16_s4_s4
             use entity simprim.x_ramb16_s4_s4(x_ramb16_s4_s4_v)
             generic map(
             (...)
         end for;
       (multiple bram instances follow...)
       end for;
     end for;
   end for;
end system_conf;


Article: 65229
Subject: error in Quartus
From: "chris" <mithr@hotpop.com>
Date: Thu, 22 Jan 2004 18:32:46 +0200
Links: << >>  << T >>  << A >>
First of all i would like you to apologize if what i am going to ask has
been answered before.Although i searched until now i didn't find anything
helpful.
My problem is that when i try to compile a package in Quartus which has only
components i receive the error : node instance instantiates undefined entity
float_pkg.
The same file has been compiled successfully in Modelsim withous changing
any line.Does Altera have any forum to ask them about that?
I would be much appreciated if anyone can tell me anything about that.



Article: 65230
Subject: Re: xilinx 70% tracking rule
From: russelmann@hotmail.com (Rudolf Usselmann)
Date: 22 Jan 2004 08:56:13 -0800
Links: << >>  << T >>  << A >>
"Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote in message news:<7gKPb.46671$lGr.8430@twister01.bloor.is.net.cable.rogers.com>...
...
> 
> But this is why FPGA companies have timing modeling and characterization
> groups, and part of why FPGAs are slowly taking over the world (or so I hope
> :-) -- imagine having to worry about all this stuff when doing your ASIC?

Yes, imagine working with a part that comes with a data
sheet with 100% clearly defined timing for each cell !
Just open the data sheet and get 100% clear information.

(Routing delays are undefined until Synthesis and P&R for both.)

> Regards,
> 
> Paul Leventis
> Altera Corp.

This BS marketing from FPGA companies is 80% nonsenseand
5% Truth. The remaining 15% are pure lies.

Regards,
rudi
========================================================
   ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
..............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/  <- FREE EDA Tools

Article: 65231
Subject: Lining up data...
From: David Nyberg <eng4hire@excite.com>
Date: Thu, 22 Jan 2004 17:16:58 GMT
Links: << >>  << T >>  << A >>
I'm trying to implement a big MUX.  This MUX will switch 6 bits of 
high-speed digital data along with its CLK @ ~ 300MB/s!  There are 6 
input ports and one output port.  The output must contain the selected 
ports CLK (of course) as well as provide the selected ports data.  I'm 
having trouble understnading how to make sure the data lines up at the 
output port!  Timing simulations show a significant skew between data 
bits.  I have a register at the output but that is not my problem.  My 
problem is the path from the input pads tp the input of the register.  I 
am using Foundation 6 / schematic entry because I am not up to speed in 
VHDL. (Yet)  I have 7 STD MUX's on the page one for each data bit (0-5) 
and a MUX for the CLK's.  All of the outputs according to the SEL lines 
provide data bits from ports 1-6 one at a time via the SEL lines.  Any 
help would be great!  I though about connecting the selected ports CLK 
to the EN pin of the input MUX's but I cant see how thats going to help 
with the data bit skew from bit to bit.  I do not care if port 1 has a 
longer delay through the part (which I have not settled on yet) than any 
other port selected.  How long it takes the data to get from the input 
pads to the output pads is of no concern to me because the data is DVI 
and the monitor will simply display what it gets when it gets it! 
Making sure that the data and the CLK is aligned all the way through the 
silicon seems to be very important.

Thanks,

Dave


Article: 65232
Subject: Re: OT: liability insurance
From: Ray Andraka <ray@andraka.com>
Date: Thu, 22 Jan 2004 12:24:26 -0500
Links: << >>  << T >>  << A >>
The P.E. license is issued by the state where you do business.  All the states
prescribe to the standards set by NSPE.  Basically, it involves a combination of
experience and sitting for some exams.  The most used route is to sit for the
Fundamentals in Engineering exam soon after you graduate from college.  When you
pass that exam (also known as the EIT) you are an "engineer in training".  In
order to sit for the PE exam, you need to have taken the FE exam within the past
12 years, or have 20 years of experience in your field of engineering (and
someone to vouch for it), plus at least 4 years of engineering experience.  The
FE exam is rather grueling, and I don't think I'd want to take it if I wasn't
fresh out of school, simply because it covers such a wide range of engineering
and science topics.  It is stuff that if you haven't seen it lately, you'll
probably have trouble finishing the exam in the alloted time.   I found the PE
exam to be fairly easy, although it did take some study because it requires some
breadth to your EE background...there are many sections on machines,
transformers, power etc that I hadn't seen in quite some time.   You also need
to get references from a number of P.E.s familiar with your work (the number
required varies by state), and depending on the state, some of those  may have
to be registered in the state you are applying.  I found the hardest part was
finding the references, as there are not that many P.E.s in electronic design
for manufacturing.

Note that in order to offer engineering services to the public (this includes to
other firms), you are required to have a P.E. registered to your firm in most
states.  Without it, the state can generally issue you a cease and desist order,
and fine and/or imprison you if you don't comply. This is enforced to varying
degrees in different states.  There is an exemption for engineering for
manufacturing, but it only applies to engineers on the company payroll, not to
outside consultants.  If you are consulting, you technically need to have a P.E.
or have someone on staff with a P.E.

I carry professional liability, which covers the designs my firm produces.


Blake Henry wrote:

> Hello Ray,
>
> Nice seeing your post.  Tell me, 1) what's involved in getting the P.E.
> moniker and 2) do you carry product liability?
>
> Blake
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:400ECC6F.CF29C15D@andraka.com...
> > $500/yr sounds like Commercial General Liability, which basically protects
> > you if a customer hurts himself on your premises.  It doesn't generally
> > provide any coverage for your product, in other words O&E.  My O&E runs
> > about $6000/year, and is through a different insurer than my CGL.  There
> are
> > relatively few carriers that offer O&E, and you'll likely be locked out of
> > it for certain products like medical instruments and nuclear controls.
> >
> > Robert Sefton wrote:
> >
> > > I'm a consultant/contractor. A new customer is requiring me to carry
> > > commercial general liability coverage, including contractual liability
> > > (errors and omissions). I carried a $1M policy from Hartford for several
> > > years, but let it lapse in '02 after customers quit insisting on it. I
> > > paid $500/yr back then. Any recommendations, and what should I expect to
> > > pay? I'm in California.
> > >
> > > Thanks,
> > >
> > > Robert
> > > (real email: rsefton@nextstate.com)
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 65233
Subject: Re: WTD: info on AMD palce22v10
From: Ray Andraka <ray@andraka.com>
Date: Thu, 22 Jan 2004 12:31:01 -0500
Links: << >>  << T >>  << A >>


Ralph Malph wrote:

> > Motorola (never got out of the starting gate, relied on external software...)
> I don't know that it was the software that killed this product.  They
> were using NeoCad which was pretty successful (at least technically) for
> the other vendors they supported.

Xilinx's purchase of Neocad was the nail in the coffin for Motorola's FPGA,
but they were going nowhere fast before that.

> > AMD (sold it to Lattice)
> PLDs only AFAIK.  Still being made.  It was sold off not because it was
> failling, but because it was successful and AMD needed cash to keep the
> CPU business running.

AMD also had an FPGA, which they spun out under Vantis.  IIRC, lattice has
the rights to that now.

>
> > T.I. ( stopped being second source to Actel)
> I don't remember then selling FPGAs or similar, they did CPLDs.  TI did
> a complete makeover and decided that they were all about DSP in
> telecoms.  They sold off everything that was not a key technology and
> bought a lot of stuff that was.
>

TI was a second source for Actel in the late 80's, early 90's.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 65234
Subject: Random data generator...
From: David Nyberg <eng4hire@excite.com>
Date: Thu, 22 Jan 2004 17:39:18 GMT
Links: << >>  << T >>  << A >>
Anybody ever come accross a way to design and build a random high speed 
data pattern generator?  It just dawned on me that I'm going to need a 
way to test the MUX design I posted to 300MB/s!

Dave


Article: 65235
Subject: Re: OT: liability insurance
From: "Robert Sefton" <rsefton@abc.net>
Date: Thu, 22 Jan 2004 09:53:32 -0800
Links: << >>  << T >>  << A >>
You're killing me, Ray! You seem to be an expert on all of the legal
requirements and financial costs of running an engineering services
business the right way. I hope this isn't because you learned the hard
way how to protect yourself. :) Can you provide a bullet list of the
things that must be in place to be in compliance legally and to protect
yourself financially? Business license, P.E. license, CGL and O&E
insurance ... anything else?

Thanks,
Robert

"Ray Andraka" <ray@andraka.com> wrote in message
news:4010074A.C0EC4FDE@andraka.com...
> The P.E. license is issued by the state where you do business.  All
the states
> prescribe to the standards set by NSPE.  Basically, it involves a
combination of
> experience and sitting for some exams.  The most used route is to sit
for the
> Fundamentals in Engineering exam soon after you graduate from college.
When you
> pass that exam (also known as the EIT) you are an "engineer in
training".  In
> order to sit for the PE exam, you need to have taken the FE exam
within the past
> 12 years, or have 20 years of experience in your field of engineering
(and
> someone to vouch for it), plus at least 4 years of engineering
experience.  The
> FE exam is rather grueling, and I don't think I'd want to take it if I
wasn't
> fresh out of school, simply because it covers such a wide range of
engineering
> and science topics.  It is stuff that if you haven't seen it lately,
you'll
> probably have trouble finishing the exam in the alloted time.   I
found the PE
> exam to be fairly easy, although it did take some study because it
requires some
> breadth to your EE background...there are many sections on machines,
> transformers, power etc that I hadn't seen in quite some time.   You
also need
> to get references from a number of P.E.s familiar with your work (the
number
> required varies by state), and depending on the state, some of those
may have
> to be registered in the state you are applying.  I found the hardest
part was
> finding the references, as there are not that many P.E.s in electronic
design
> for manufacturing.
>
> Note that in order to offer engineering services to the public (this
includes to
> other firms), you are required to have a P.E. registered to your firm
in most
> states.  Without it, the state can generally issue you a cease and
desist order,
> and fine and/or imprison you if you don't comply. This is enforced to
varying
> degrees in different states.  There is an exemption for engineering
for
> manufacturing, but it only applies to engineers on the company
payroll, not to
> outside consultants.  If you are consulting, you technically need to
have a P.E.
> or have someone on staff with a P.E.
>
> I carry professional liability, which covers the designs my firm
produces.
>



Article: 65236
Subject: Re: Non deterministic routing in Quartus 3.0 ?
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 22 Jan 2004 18:55:18 +0100
Links: << >>  << T >>  << A >>
giachella.g@laben.it (g. giachella) writes:

> I have launched a new compilation on a pc only and, again, the result
> is different from the previous launched on the same pc. I don't
> understand why ...

Do you have smart compilation enabled? If yes, then it will use the
result of the previous iteration as the base for the next.

Make a backup. Then delete all but your source files and start in a
fresh directory.

Petter

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 65237
Subject: Re: Random data generator...
From: Amontec Team <laurent.gauch@www.DELALLCAPSamontec.com>
Date: Thu, 22 Jan 2004 19:01:03 +0100
Links: << >>  << T >>  << A >>
David Nyberg wrote:
> Anybody ever come accross a way to design and build a random high speed 
> data pattern generator?  It just dawned on me that I'm going to need a 
> way to test the MUX design I posted to 300MB/s!
> 
> Dave
> 
You just have to write a Shift register with some XOR gates like a CRC 
generator.
If you need speed use a SPARTAN3 OR Virtex-II -> a CLB can works like a 
quick small shift register -> special function of a Xilinx CLB. :-)

Laurent
www.amontec.com


Article: 65238
Subject: Re: xilinx 70% tracking rule
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 22 Jan 2004 10:08:42 -0800
Links: << >>  << T >>  << A >>
Strong words, Rudi !
But unless you can substantiate your claims, we will ignore them as your
kind of BS.
I am an engineer, and I do not make marketing claims, and neither do I
publish 80% nonsense and 15% lies.
For some reason the world is rapidly converting to FPGA. Last year there
were less than 1500 new ASIC designs and probably 100 000  new designs
using FPGAs. Many of us in this ng are aware of the ASIC advantages, but
they come with a hefty price tag, long manufacturing time, risk and
inflexibility. That's why most of us prefer FPGAs. It is also reflected
in the name of this ng.

So, Rudi, if you want to post here, say something meaningful, and do not
just blurt out unsubstantiated insults. Hurts your reputation more than mine...

Peter Alfke,     
============================================
Rudolf Usselmann wrote:
>
> This BS marketing from FPGA companies is 80% nonsenseand
> 5% Truth. The remaining 15% are pure lies.
> 
> Regards,
> rudi
> ========================================================
>    ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
> ..............::: FPGAs * Full Custom ICs * IP Cores :::
> FREE IP Cores -> http://www.asics.ws/  <- FREE EDA Tools

Article: 65239
Subject: Re: Random data generator...
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 22 Jan 2004 10:19:12 -0800
Links: << >>  << T >>  << A >>
David, decide whether you need true randomness, or whether pseudo-random
is good enough. If it is, you can build linear-feedback shift register
structures quite easily, and make them as long and as fast ( and
parallel) as you want.

True randomness is far more complicated to achieve, is usually based on 
the statistical characteristics of some natural phenomenon like noise.

Peter Alfke
==========================
David Nyberg wrote:
> 
> Anybody ever come accross a way to design and build a random high speed
> data pattern generator?  It just dawned on me that I'm going to need a
> way to test the MUX design I posted to 300MB/s!
> 
> Dave

Article: 65240
Subject: Re: Why is router software not multi-threaded?
From: "John Retta" <jretta@rtc-inc.com>
Date: Thu, 22 Jan 2004 18:22:05 GMT
Links: << >>  << T >>  << A >>
Look at the PAR section of the dev.pdf (Developers Reference Guide)
in your Xilinx doc directory.  The -m option of par allows you to specify
a list of workstations to parse out place-and-route runs.  I used this 3
years ago in environment of Solaris workstations ..... the effort level to
get it working was minimal.

This does not mean that par is multi-threaded.  I just means that you
can run N different place-and-routes using different placement starting
points (cost table entries) across multiple machines.

-- 
Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.

email : jretta@rtc-inc.com
web :  www.rtc-inc.com


"Peter Sommerfeld" <petersommerfeld@hotmail.com> wrote in message
news:5c4d983.0401220801.700517ba@posting.google.com...
> Excuse my ignorance if there is an obvious answer ...
>
> Is it true that the routing algorithms used in Altera's and Xilinx'
> tools are single-threaded? If so, what is the primary difficulty with
> making them multi-threaded? Is the algorithm particularly difficult to
> partition into parallel units? Or has it simply not been a priority
> for companies making the tools?
>
> Now that some of the projects I am working on are taking quite a while
> to fit, I'm thinking it would be nice to parcel out a fit between 5
> machines sometime in the future when/if the software supports it.
>
> -- Pete



Article: 65241
Subject: Re: Synthesis of Loops
From: symon_brewer@hotmail.com (Symon)
Date: 22 Jan 2004 10:32:59 -0800
Links: << >>  << T >>  << A >>
Hi Jonathan,
Your post (and a subsequent trawl of comp.lang.vhdl) just lifted a
veil from my vision of VHDL arithmetic; thank you very much! No longer
will I rely on the library 'blunderbuss' technique! You should get a
job at a training company, you show some promise...  ;-)
Thanks again mate, Syms.

<jonathan.bromley@doulos.com> wrote in message news:<buop5a$jcl$1$8300dec7@news.demon.co.uk>...
> <Bochumfrau@gmx.de> wrote in message
> news:17b83bf3.0401220306.3bfbe0ed@posting.google.com...
> 
> > Why is it better to avoid the unsigned library?
> 
> std_logic_vector is simply a collection of std_logic
> bits.  The std_logic_unsigned package gives std_logic_vector
> a new meaning (unsigned binary) that can be confusing, and
> if you want to use signed numbers in the same design it
> will become very difficult.
> 
> On the other hand, std_logic_arith defines two new data
> types SIGNED and UNSIGNED, with the *same definition* as
> std_logic_vector.  Using this, you can be very clear about
> what you are trying to do.  numeric_std is even better,
> because it is properly standardised by IEEE and it has a
> more complete set of functions and operators.
> 
> > Let's assume the following assignment:
> >
> > i := conv_integer(l_vector);
> >
> > ...
> >
> > When I do not include the unsigned library I get the error message:
> > "Object cannot be indexed because it has integer type rather than
> > array type".
> 
> i := conv_integer( unsigned(l_vector) );
> 
> std_logic_vector and unsigned have the same definition, so they
> are "closely related" and you can convert from one to the
> other by using the type name as if it were a conversion function.
> The vector<->integer conversions work between integer and
> SIGNED or UNSIGNED data.

Article: 65242
Subject: Re: error in Quartus
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Thu, 22 Jan 2004 10:40:37 -0800
Links: << >>  << T >>  << A >>
chris wrote:

> My problem is that when i try to compile a package in Quartus which has only
> components i receive the error : node instance instantiates undefined entity
> float_pkg.

A package may contain component declarations, but not instances.

   -- Mike Treseler


Article: 65243
Subject: Synthesizing pipelined multipliers in Synplify Pro
From: smukthav@yahoo.com (Sandeep)
Date: 22 Jan 2004 10:48:27 -0800
Links: << >>  << T >>  << A >>
Does anyone have experience with synthesizing multipliers using "*"
operator in Synplify ? To pipleline the multiplier has anyone tried
the piplelining feature in Synplify and/or by attaching attributes to
output registers ? I know it works on a multiplier by itself. But in a
larger design the pipleline stages are reduced to 1 or 2 even though I
attached 4-5 registers to the multiplier output.

Sandeep

Article: 65244
Subject: Re: Xilinx Spartan3 Timing Problems - Whats about the chips
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Thu, 22 Jan 2004 10:56:30 -0800
Links: << >>  << T >>  << A >>
One quick thing ...

The Spartan-3 speeds files were recently updated to better reflect actual
silicon measurements.  The previous speeds files, v1.27, were considered
PREVIEW level and were based primarily on simulation data.  The recent
speeds files, v1.29, have now graduated to ADVANCE level, indicating that
the data is based on actual device characterization data measured on
Spartan-3 devices.

The particular parameter that you mentioned, Tiockon, ranged from 1.099 ns
to 6.197 ns using the -4, v1.27 speeds file.  The value reported by the
timing analyzer, 5.865 ns, is specific for the way that your application was
implemented in the FPGA.

The Tiockon parameter now ranges from 1.127 to 4.000 ns using the -4, v1.29
speeds file.  Re-running the design using the speeds files will improve the
performance.  Similarly, setting some timing constraints on the particular
path may improve the results further still.

Optionally, the v1.29 speeds files now also include a -5 speed grade, which
is about 13% to 15% faster than the new revision of the -4 speed grade.

Now for the next logical question:  Where can I obtain the new speeds file?

Please point your browser to the following web link.
http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=18557

Then please download and extract the referenced ZIP file.  Then, please
re-run the Xilinx implementation software to take advantage of the extra
performance.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC


Please check which version
"itsme" <itsme@gmx.de> wrote in message
news:buo43e$ji4$06$1@news.t-online.com...
> Hi all,
> I am actually trying to switch a virtex2 project to spartan3. While
> implementing the design I got several timing errors. One reason is that
the
> timing parameter "CLK to valid Data on Pad" (Tiockon). The data sheet of
> virtex2 gives a value of 3.51ns. The value for spartan3 is 5.865ns - which
> is much higher!!! . I got this value for spartan3 from Timing Analyzer
> (Vers. 6.1.03i). In the newest datasheet of the spartan3 the chapter
> "switching characteristics" is still quite empty.
> So I really wonder what the XILINX guys do. Selling a chip without timing
> specs? Is the spartan3 really much slower than the Virtex2?
> Any comments? Any Spartan3 Users?
>
>



Article: 65245
Subject: Spirit on Mars
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 22 Jan 2004 10:56:52 -0800
Links: << >>  << T >>  << A >>
Lest anyone spread rumors,

Spirit used a 4K QPRO part for the squibs that fired for the parachute, 
the inflatable bag, etc for the Lander.

The rover has Virtex 1000's in the wheels for position/motor control.

The fact that the Spirit has stopped sending useful data back to NASA is 
a terrible thing, but we got them there, and rolled them onto the 
surface.  Other folks parts are supposed to do the communicating with 
Earth.  Who volunteers to let us know whose components are used for 
that?  What processor did they use?

Hope those folks figure it out, as it is a tradegy for everyone to lose 
the ability to gain knowledge of our solar system.

By the way, the self checks on the FPGAs after that solar flare that 
destroyed that Japanese satellite's electronics showed that the FPGAs 
were undamaged, and had suffered not at all from the flare (as we can 
take many rads of radiation, and not be affected at all).

The reason for the failure of other parts could be that they are NOT 
FPGAs.  FPGAs are manufactured in huge volumes, and are all tested in 
the qualification for latch up under irradiation.  Many SRAM,s and other 
products do not have the volume to afford such testing, and in fact 
recent shrinks of common parts are known to latch up with a single 
event, and destroy themselves.

Austin


Article: 65246
Subject: Down Sample, FFT
From: Thomas <Demonkronos@hotmail.com>
Date: Thu, 22 Jan 2004 11:24:41 -0800
Links: << >>  << T >>  << A >>
When I simulate my System Generator design, the following error is reported: 
"Although the behavior of this block, as configured, could be simulated, it will not be possible to target it to hardware because: 

--- Cannot be synthesized and it does not map to cores because the FFT core must be run at the system clock rate" 

The problem apears when I put a Down Sample block before the FFT inputs, to obtain a zoom effect in simulation. 

Anybody can help me?



Article: 65247
Subject: Re: Post-Place & Route simulation with MicroBlaze
From: Ryan Laity <ryan_dot_laity@x-i-l-i-n-x_pleasenospam_dot_com>
Date: Thu, 22 Jan 2004 13:12:30 -0700
Links: << >>  << T >>  << A >>
Arkaitz,

If you're doing your top level development from ISE (which it sounds 
like you are), there is a fairly simple way to avoid the configuration 
statement in the testbench.

To do this, just add your executable.elf file to the ISE project as a 
source.  When you do, ISE will ask you how you want the file assigned, 
you should choose the top level file (top_level I believe you called 
it).  This will initialize the Block RAM in the .ncd file and therefore 
will be in the simulation model for the post-par simulation.  This may 
not be convenient for future revisions of your software, as you have to 
rerun implementation for an update, but this will make your simulation 
much easier to set up as everything's all in one model.

I hope this helps.

Best regards,
Ryan Laity
Xilinx Applications

arkaitz wrote:
> Hi all,
> 
> I have a design where MicroBlaze isn't the top level of it.
> 
> I have simulated the behavioral model with ModelSim SE 5.6f and it
> works fine but when I implement and download to the FGPA it doesn't
> work, so now I want to simulate the Post-Place & Route model too see
> if there's any timing wrong.
> 
> Due to my MicroBlaze desing isn't the top level, XPS doesn't allow me
> generate the behavioral model, so I have to do it manually. That's the
> way I have done the behavioral model simulation.
> 
> So I have a Project Navigator design with various components which one
> of them is the MicroBlaze designed in XPS. In the testbench I use a
> configuration block where I assign the code that needs to be inside
> the blockram of MicroBlaze.
> Since MicroBlaze isn't my top level this configuration block has the
> next aspect:
> 
> configuration testbench_conf of system_tb_system_vhd_tb is
>   for behavior
>     for uut1 : top_level
>       for structure
>         for uut2: mb_blaze
>           for structure
>             for all: instr_mem_wrapper use configuration
> work.instr_mem_conf;
>             end for;
> 	  end for;
> 	end for;
>       end for;
>     end for;
>   end for;
> end testbench_conf;
> 
> 
> The problem comes here. When I ask ISE to simulate the P&R model it
> generates a file called "top_level_timing.vhd" which hasn't got any
> hierarchy, so obvioulsy the configuration block generates some
> compilation errors.
> 
> Is there any other way to assign the contents of the instruction set
> to the  blockram of MicroBlaze?
> 
> Any other idea to avoid this error?
> 
> I am not used to working with configuration blocks, so the solution
> might be obvious.
> 
> Thanks in advance, 
> 
> Arkaitz.


Article: 65248
Subject: Re: Why is router software not multi-threaded?
From: "fabbl" <yttt@nukes.com>
Date: Thu, 22 Jan 2004 20:22:26 GMT
Links: << >>  << T >>  << A >>
> Is it true that the routing algorithms used in Altera's and Xilinx'
> tools are single-threaded? If so, what is the primary difficulty with
> making them multi-threaded? Is the algorithm particularly difficult to
> partition into parallel units? Or has it simply not been a priority
> for companies making the tools?

This would be nice...Xilinx willing comment?



Article: 65249
Subject: CHES 2004, 2nd CFP
From: cpaar@crypto.ruhr-uni-bochum.de (Christof Paar)
Date: 22 Jan 2004 12:46:22 -0800
Links: << >>  << T >>  << A >>
Dear Friends of CHES, a few updates:

- Please find the 2nd CFP bleow. 

- Please note that the submission deadline is March 2nd. 

- You can order a CD with the full proceedings of all 5 CHES 
  conferences (1999-2003) from the CHES website, see the URL below.

Regards, Christof

=========================================================================
 
 Conference on Cryptographic Hardware and Embedded Systems 2004
                           (CHES 2004)

                       www.chesworkshop.org

                     Cambridge (Boston), USA
                       August 11-13, 2004

                     Second Call for Papers

The 6th CHES Conference will be held in Cambridge, Massachusetts (next to
Boston.) Following the tradition of previous CHES conferences, it will
take place on the Wednesday-Friday immediately preceeding CRYPTO 2004,
which starts on Sunday, August 15.

The full Call for Papers is available on the CHES webpage at:
                      www.chesworkshop.org


============================================
Prof. Christof Paar
Chair for Communication Security
Dept. of Electr. Eng. & Information Sciences
Ruhr-University Bochum
44780 Bochum, Germany

URL: www.crypto.rub.de



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