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Messages from 65150

Article: 65150
Subject: References to good PCI boards and some newbie questions - please help!
From: valery@biozak.com (Valery)
Date: 21 Jan 2004 04:26:17 -0800
Links: << >>  << T >>  << A >>
Hi,

we are starting a project in our group porting several CPU intensive
but simple apps to FPGA platform. We have selected PCI as a way to
communicate with a host PC. We have some experience programming FPGAs
but not PCI-based (need PCI now due to data transfer speed
requirements).

I would be very grateful if someone can answer the folowing for us:

1. What PCI boards you would recommend containing 2-4M total gates and
32MB+ of on-board RAM? We have looked at a couple of development kits
from Altera and Xilinx and they all run over $2,000. Is there anything
cheaper?

2. Do we have to buy a license to PCI core in order to use the board?
I mean we are not going to modify any of the PCI interface functions.
For all we care, PCI could have been implemented in a dedicated chip
on our dev boards...

Thanks all in advance for your responses!

Valery.

Article: 65151
Subject: Re: changing values in a fifo
From: Marc Randolph <mrand@my-deja.com>
Date: Wed, 21 Jan 2004 12:51:42 GMT
Links: << >>  << T >>  << A >>
Patrick Klacka wrote:
>>Save some sort of CRC hash with each value push.
>>Apply correction(hash) when a value is popped.
> 
> 
> I applied this method in the original design (on a pc), but it is not
> deterministic - a value could change several times before it emerges from
> the fifo, resulting in multiple indexes into an array to find the ultimate
> answer. I can e-mail or post snippets of code to explain this better.
> 
> I tried building my own fifo, which took an input value, compare value, and
> change value. Upon inserting the input value in the fifo, if any of the
> values in the fifo were equal to the compare value, they were updated to the
> change value. Given the depth requirements of the fifo, this implementation
> will not fit in the fpga I am currently using.
> 
> I like the idea of not indexing into the fifo, and just applying some sort
> of correction to the value that is removed, but there will need to be some
> way of correcting that value in one cycle, to maintain deterministic
> performance.

Howdy Patrick,

What is the size of compare_value, change_value, and most importantly, 
how deep does the FIFO need to be?

Good luck,

    Marc


Article: 65152
Subject: microblaze reg_addr and new_reg_value outputs
From: samuel nobs <nobssa@ee.ethz.ch>
Date: Wed, 21 Jan 2004 13:54:14 +0100
Links: << >>  << T >>  << A >>
hello,

i am working with xilinx microblaze and i am trying to figure out the 
purpose of the two undocumented output signals reg_addr (5 bits wide) 
and new_reg_value (32 bits wide).

i assume that reg_addr outputs the register currently written to and
new_reg_value outputs the value written to this register.

is anyone able to confirm my assumptions?

thank you,
sam


Article: 65153
Subject: Synthesis of Loops
From: Bochumfrau@gmx.de (Bochumfrau@gmx.de)
Date: 21 Jan 2004 05:07:25 -0800
Links: << >>  << T >>  << A >>
Dear Sir or Madam,

I am trying to describe a module in VHDL which is capable of treating
incoming parallel 16 bits (data rate 30MHz).
An internal 90Mhz clock is used to nrzi-decode and to unstuff
the 16bit-words. Apart from that 
the vector "gaps" (removed stuff bits) are bridged by shifting the
adjacent
bit positions up so that a complete 16bit word can be passed on to a
next
stage when all bit positions of the cleaned 16bit vector have a valid
value.
All this should be completed after 3 clock cylces (90MHz) so that the
next
16bit-word (30MHz)can be handled.

My question: (info: I use Altera QuartusII software)

I have written some VHDL code for that module.
Because of an error message I do not know if the timing of >=90MHz
is achieved.
The error message occurs in the state "s_unstuff" of the state_machine
when trying to define a loop border which is not static. Its value
comes from the former state where the value is calculated.
Is there a possibility to define such a loop (while-loop or for-loop)
?
I have tried both: "while" and "for" but there always is the error
message that
constants have to be used. What can I do about that?
Are there other alternatives?

Thank you for your help.

Regards
Eva

--------------------------------------------
--------------------------------------------

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Decode_destuff is
port ( Reset          : in  std_logic;
       Clk            : in  std_logic;
       In_rec_enable  : in  std_logic;
       Data_in        : in  std_logic_vector(15 downto 0);
       Out_flag       : out std_logic;
       Pos1           : out std_logic_vector(4 downto 0);
       Pos2           : out std_logic_vector(4 downto 0);    
       Data_cleaned   : out std_logic_vector(15 downto 0)
     );
end Decode_destuff;


architecture behavior of Decode_destuff is

signal l_data_in_reg    : std_logic_vector(15 downto 0);
signal l_unstuff_buffer : std_logic_vector(15 downto 0);

signal l_decoded_data    : std_logic_vector(15 downto 0);
signal l_bit_position1   : integer range 0 to 15;
signal l_bit_position2   : integer range 0 to 15;
signal l_flag            : std_logic;
signal l_bit_count       : integer range 0 to 15;
signal l_mark_border     : std_logic;
signal l_position1_valid : std_logic;
signal l_position2_valid : std_logic;

type type_treat is ( s_ini,
                     s_decode,
                     s_unstuff,                     
                     s_wait                     
                   );
signal state_treat : type_treat;

begin

Data_cleaned <= l_unstuff_buffer;
Out_flag     <= l_flag;      
Pos1         <= conv_std_logic_vector(l_bit_position1, 5);
Pos2         <= conv_std_logic_vector(l_bit_position2, 5);


 process(Reset, Clk)
 variable var_decoded_data   : std_logic_vector(15 downto 0);
 variable var_unstuffed_data : std_logic_vector(15 downto 0);
 variable bit_count          : integer range 0 to 15;
 variable var_flag           : std_logic; 
 variable wert               : integer range 0 to 15;
 variable index              : integer range 0 to 15;
 begin
   if Reset='1' then
      l_data_in_reg     <= (others => '1');
      l_decoded_data    <= (others => '1');
      state_treat       <= s_ini;
      l_bit_position1   <= 0;
      l_bit_position2   <= 0;    
      l_flag            <= '0';
      l_bit_count       <= 0;
      l_mark_border     <= '0';
      l_unstuff_buffer  <= (others => '0');
      l_position1_valid <= '0';
      l_position2_valid <= '0';
      
    elsif rising_edge(Clk) then
      l_data_in_reg      <= l_data_in_reg;
      l_decoded_data     <= l_decoded_data;
      var_decoded_data   := l_decoded_data;
      state_treat        <= state_treat;
      l_bit_position1    <= l_bit_position1;
      l_bit_position2    <= l_bit_position2;          
      l_bit_count        <= l_bit_count; 
      bit_count          := l_bit_count;
      l_flag             <= l_flag;
      var_flag           := l_flag;      
      wert               := 0;
      l_mark_border      <= l_mark_border;
      l_unstuff_buffer   <= l_unstuff_buffer;
      var_unstuffed_data := l_unstuff_buffer;
      l_position1_valid  <= l_position1_valid;
      l_position2_valid  <= l_position2_valid;
      case state_treat is

           when s_ini =>
           
                if In_rec_enable='1' then
                   state_treat <= s_decode;
                end if;
           ---------------*---------------*---------------
           when s_decode => -- NRZI-Dekodierung

                if l_mark_border='1' then
                   l_mark_border   <= '0';                   
                end if;
                
                for i in 15 downto 0 loop
                   wert := i;
                   if i < 15 then  
                          if Data_in(i+1)=Data_in(i) then 
                             var_decoded_data(i) := '1';
                          else 
                              var_decoded_data(i) := '0';
                          end if;                       
                   else
                          if l_data_in_reg(0)= Data_in(15) then
                             var_decoded_data(i) := '1';
                          else
                             var_decoded_data(i) := '0';
                          end if;
                   end if;
                   ---------------
                   if var_decoded_data(i)='1' then

                      bit_count := bit_count + 1;

                      if bit_count=15 then
                         bit_count := 0;
                      elsif bit_count=6 then  
                         if i=0 then
                            l_mark_border <= '1';
                         else                                       
                            if var_flag='0' then
                               var_flag          := '1';
                               l_bit_position1   <= wert-1;
                               l_position1_valid<= '1';
                            else 
                               var_flag          := '0';
                               l_bit_position2   <= wert-1;  
                               l_position2_valid <= '1';
                            end if;
                         end if;
                      end if;   
                   else
                      bit_count := 0;
                   end if;                               
                    
                end loop; 

                state_treat    <= s_unstuff;
                l_data_in_reg <= Data_in; 

                -- Signale <= Variablen
                l_decoded_data <= var_decoded_data;               
                l_bit_count    <= bit_count;
                l_flag         <= var_flag;               
                       
           ---------------*---------------*---------------*--------
           when s_unstuff =>   
                var_unstuffed_data := l_decoded_data;
                index:=15;
                if l_mark_border='1' then
                 var_unstuffed_data(15 downto 1) := l_decoded_data(14
downto 0);
                end if;
                if l_position1_valid='1' then
                   while (index /= l_bit_position1)  loop
                      var_unstuffed_data(index) :=
var_unstuffed_data(index-1);
                      index := index - 1;
                   end loop;
                end if;
                if l_position2_valid='1' then
                 var_unstuffed_data(l_bit_position2 downto 1) :=
l_decoded_data(l_bit_position2-1 downto 0);
                end if;
                state_treat <= s_wait;

                l_unstuff_buffer <= var_unstuffed_data;
                              
           ---------------*---------------*---------------*---------
           when s_wait => 
                state_treat   <= s_decode;  
                l_position1_valid <= '0';
                l_position2_valid <= '0';
                l_flag            <= '0';
                                           
           ---------------*---------------*---------------*----------
           when OTHERS => NULL;
           
       end case;
                    

     end if;             
                 
 end process;


end behavior;

Article: 65154
Subject: Re: Synthesis of Loops
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Wed, 21 Jan 2004 13:42:01 -0000
Links: << >>  << T >>  << A >>
<Bochumfrau@gmx.de> wrote in message
news:17b83bf3.0401210507.364a8ac2@posting.google.com...

[...]
> I have written some VHDL code for that module.
> The error message occurs in the state "s_unstuff" of the state_machine
> when trying to define a loop border which is not static. Its value
> comes from the former state where the value is calculated.
> Is there a possibility to define such a loop (while-loop or for-loop)
> ?
> I have tried both: "while" and "for" but there always is the error
> message that
> constants have to be used. What can I do about that?
> Are there other alternatives?

Use a "for" loop that scans over the whole array, and
inside the loop, use an if statement to determine whether
the action should take place in that iteration.

Most synthesis tools can't handle loops with variable
bounds.

Some, however, can deal correctly with a for loop
with constant bounds but having an "exit" statement;
in this way you can make the loop terminate after
a variable number of iterations.

One minor point:

> library ieee;
>
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;

Best to avoid this.  std_logic_unsigned is not pretty.
std_logic_arith or numeric_std will do a better and
clearer job for anything you are likely to need.

I haven't looked at your code (too many lines, too
little time) so I can't comment on whether what you
are trying to do is otherwise reasonable.
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 65155
Subject: Re: microblaze reg_addr and new_reg_value outputs
From: Goran Bilski <goran@xilinx.com>
Date: Wed, 21 Jan 2004 15:00:03 +0100
Links: << >>  << T >>  << A >>
Hi Sam,

Your assumption is correct.

The values is however only valid when the signal VALID_INSTR is '1'.
A write is also only happening when REG_WRITE is '1'.

The signal PC_EX is the instruction_address for the executing instruction
MSR_REG contains the current msr register value
PIPE_RUNNING is '1' when the pipeline is running ("no stalls")
INTERRUPT_TAKEN is '1' when an interrupt is acknowledge (when MicroBlaze 
is jumping to the interrupt address)
JUMP_TAKEN is '1' when a jump is taken
PREFETCH_ADDR is showing how many instructions that has been prefetched
MB_Halted is '1' when MicroBlaze has been halted by the internal debug logic

Göran

samuel nobs wrote:

> hello,
>
> i am working with xilinx microblaze and i am trying to figure out the 
> purpose of the two undocumented output signals reg_addr (5 bits wide) 
> and new_reg_value (32 bits wide).
>
> i assume that reg_addr outputs the register currently written to and
> new_reg_value outputs the value written to this register.
>
> is anyone able to confirm my assumptions?
>
> thank you,
> sam
>


Article: 65156
Subject: Re: Trouble using ChipsCope Pro with MicroBlaze
From: arkagaz@yahoo.com (arkaitz)
Date: 21 Jan 2004 06:03:44 -0800
Links: << >>  << T >>  << A >>
Hi,

It's me again.

Looking at Erik's details I have continued the the next steps:

- Create a XPS proyect with JTAG Uart included in it.
- Export to Project Navigator.
- Include an ICON Core Disabling the BSCAN instantiation so that it
shows the pins in the instantiation file.
- Take the JTAG Uarts source core and modify so that BSCAN component
can be instantiation from the top level.
- Modify the top level so that the ICON uses the user port 1 of BSCAN.
(There some signals that need to be shared. I have used an OR gate in
those signals).


Once I have implement the final design it doesn't work neither of
both, I mean ChipScope and XMD.

Someone any Idea what am I doing wrong?

Thanks in advance,

Arkaitz.

PD. Thanks Erik for the help.

Article: 65157
Subject: Reference Designators naming standard...
From: apatni2003@yahoo.co.uk (Ash)
Date: 21 Jan 2004 06:20:11 -0800
Links: << >>  << T >>  << A >>
Can anybody let me know whether the reference designators naming
convention like U? for IC's, R? for resistors, C? for capacitors etc.
is based on some standard from IEEE or ANSI or IPC...?

Thanks in advance.
Regards,
Ash

Article: 65158
Subject: Re: QUES: Where can I find Xilinx M1 tools
From: JoeG <JoeG@yahoo.com>
Date: Wed, 21 Jan 2004 15:18:58 GMT
Links: << >>  << T >>  << A >>
Ted wrote:
> I have to make a change to a XC4005pc84-5 part but I don't have the tools that
> support XC4000 parts.  I've gone all the way back to Alliance Series 1.5i
> and XC4000E's are supported but not XC4000's.  I believe I need an old set
> of M1 tools but I don't know where to find them.  Does anyone know where I
> can get an old set of Xilinx tools that can supports XC4000 parts (not
> XC4000E parts).
> 
> Thanks for any info.
> 
> Ted


Ted -- I feel for you! Xilinx has dropped all support on their newer 
tools (as you've discovered) for legacy parts such as the XC4005! I have 
    made several trumpet blasts on this newsgroup about this very 
problem. Just do a google search in the groups category on XACT.

XC4005(non E) devices are ONLY support by XACT 5.2.1 software -- a CD 
was offered by Xilinx which contained the tools which could either be 
hosted on a PC supporting Win 3.1 or on a Sun Workstation supporting 
SUNOS 4.1.

A Xilinx or a Xilinx distributor should assist you in getting the CD. 
Regarding the license(dongle for the PC) -- Xilinx will help you with 
that as well.

I hope this helps.

JoeG


Article: 65159
Subject: Re: Trouble using ChipsCope Pro with MicroBlaze
From: Goran Bilski <goran@xilinx.com>
Date: Wed, 21 Jan 2004 16:20:01 +0100
Links: << >>  << T >>  << A >>
Hi,

What version of EDK and ChipScope are you using?

Göran Bilski

arkaitz wrote:

>Hi,
>
>It's me again.
>
>Looking at Erik's details I have continued the the next steps:
>
>- Create a XPS proyect with JTAG Uart included in it.
>- Export to Project Navigator.
>- Include an ICON Core Disabling the BSCAN instantiation so that it
>shows the pins in the instantiation file.
>- Take the JTAG Uarts source core and modify so that BSCAN component
>can be instantiation from the top level.
>- Modify the top level so that the ICON uses the user port 1 of BSCAN.
>(There some signals that need to be shared. I have used an OR gate in
>those signals).
>
>
>Once I have implement the final design it doesn't work neither of
>both, I mean ChipScope and XMD.
>
>Someone any Idea what am I doing wrong?
>
>Thanks in advance,
>
>Arkaitz.
>
>PD. Thanks Erik for the help.
>  
>


Article: 65160
Subject: How can I have multiple drivers of one inout port?
From: cruiser144@hotmail.com (cruzin)
Date: 21 Jan 2004 08:14:49 -0800
Links: << >>  << T >>  << A >>
Hi,

I am trying to connect the bidirectional ports of two components to
one bidirectional set of pins on my FPGA. Is it possible to do this in
VHDL? The following example does not appear to read the bidir port:

entity whatever
 port (
  signal choice   : in    std_logic;
  signal my_bidir : inout std_logic
 );
end;

architecture rtl of whatever is

signal x0_bidir,
       x1_bidir  : std_logic;

begin

 xInstOne : x
  port map (
    my_bidir_port => x0_bidir );

 xInstTwo: x
  port map (
    my_bidir_port => x1_bidir );

 my_bidir <= x0_bidir when choice='0' else x1_bidir;

end;

==========================

Is there any way to modify this to make it work, or am I stuck with
exporting both input and output ports from the components and muxing
them at the top level?

Article: 65161
Subject: EDK - Desinging system with C++
From: ramntn@yahoo.com (ram)
Date: 21 Jan 2004 08:25:47 -0800
Links: << >>  << T >>  << A >>
Hi Group Members,
  Xilinx claims it supports C++ system design(s/w part ) with EDK tool
kit.
I am having virtex 2 pro board from Insight, i would like to design
systems with c++, one way i could think of is by building the c++
appliction on top of c functions given for the peripherals.But in
doing so, if i am not wrong i should have linker script specifying how
to map the data on memory, as a newbie i am not sure how to do that.
My questions are 
1.is the linker script the same for both c/c++
2.Is there an advantage in designing C++ applicatoin on top of C
functions.
3.Is there any document that details the nuances of how to design
system using C++.

Thank you for your suggestions and replies.
Regards
Ram

Article: 65162
(removed)


Article: 65163
Subject: Re: SDRAM Controller timing problem
From: widding@birger.com (Erik Widding)
Date: 21 Jan 2004 08:54:36 -0800
Links: << >>  << T >>  << A >>
etraq@yahoo.fr (etrac) wrote in message news:<c99b95c7.0401070133.38f7e294@posting.google.com>...
> I have implemented my own SDRAM controller in a Virtex II component in
> order to use SDRAM modules Sodimm-PC133 (133 MHz frequency).
> 
> My problem is that this block seems to work very well with MICRON
> Sdram modules, but it is not fully stable with SMART modules. It seems
> to be the burst reading which causes some bit errors (not many, we
> have at worst 25 bit errors on 32Mb files).

Sounds to me like you are on the edge of your timings.  Which could
spell disaster in production.  Not all memory modules from the same
manufacturer will hae the exact same chips, especially as time passes.

The last few boards that we have brought up with SDRAM (both SDR and
DDR), we have not only done the paper & pen timing analysis, but we
have also verified the timings on the board.  We do not do this with a
logic analyzer, as this tends to effect the signal timing, regardless
of how "good" the analyzer is.

The Xilinx DCM will allow you to shift the clock in 50ps increments,
so you can affectively build an analyzer into your SDRAM controller. 
We make sure that the phase relationship of the outputs is correct by
design, from doing basic timing analysis and reading the data sheets. 
We verify the timing for the capture of the data read back from the
SDRAM by doing a memory test, incrementing the DCM phase, and
repeating, until all DCM phases (or a reasonable subset) have been
exhausted.  Basically, there will be a first DCM phase at which the
memory test passes, and a subsequent first phase at which the memory
test fails.  You will see MANY phases where the test passes if your
design is okay (power distribution, layour, etc.)  Set the DCM phase
to the middle of this window, for optimal results.

The best pattern to test for input phase is an increasing address
checkerboard pattern.  This will make the data pins on the FPGA
alternate every other clock cycle during a burst.  The test should
burst write the entire checkerboard, and then burst read the entire
pattern back.  This may seem obvious, but I have seen software
programmers write all kinds of meaningless patterns that really tested
nothing.

On some of our production boards we perform this test at power up to
dynamically set the phase of the DCM.  This might make sense for your
application, given the use of memory modules, and their inherent
replaceability.


Regards,
Erik Widding.

---
Birger Engineering, Inc. -------------------------------- 617.695.9233
100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com

Article: 65164
Subject: Re: BIST FPGA testing - Applying a test vector
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 21 Jan 2004 09:13:43 -0800
Links: << >>  << T >>  << A >>
I think I gave you the Xilinx perspective already.
We configure each device multiple times, and apply millions of test vectors.
How we figured out these configurations and test vectors is beyond an
e-mail message. It's the result of many engineers working for over 15
years on this problem, and continuously refining it. Our goal is 100%
test coverage, and we are very, very close to that goal.

Peter Alfke
=============================
BrakePiston wrote:
> 
> Thank you very much for all your replies.
> 
> I think I better clarify a few statements! :-)
> 
> First of all: I have been looking at academic research in the fault
> and defect tolerance field.
>  - Defect tolerance is aimed at, say, yield improvement whereby a chip
> with a specific defect can still be used in certain types of
> applications. Xilinx's Easypath solution is seen by academics as a
> defect tolerance problem. Or so I seem to understand.
>  - Fault tolerance is aimed at dynamic faults, these are faults
> developed during the lifetime of a device, as Thomas Stanka explained
> in his post.
> 
> All of the project I have looked at have described a way to detect and
> diagnose (locate) a fault. For what I have understood, there are 3
> different ways of conducting these tests, with an unprogrammed FPGA.
> 
> - Reconfigure the FPGA to implement a test circuit
> - Design for Testability (introduce extra hardware into the FPGA with
> the sole aim of testing)
> - Iddq testing
> 
> I am interested exclusively in the first of these options. Now, these
> tests can be further subcategorized into BIST and non-BIST tests.
> Non-BIST tests require an external "test driver" which generates and
> analyses the test vectors. BIST, on the other hand, uses different
> configurations (stored in a ROM outside teh chip) to do all the
> testing on-chip without need for extra hardware.
> 
> Now, a possible scenario where I would like to carry these tests is in
> mission critical applications, where I need to know that the device is
> working properly. I am not, at this stage, interested in having the
> chip on- or off-line during testing. Another possible scenario is
> (very unrealistic, of course) if I buy a Easypath device from Xilinx
> and want to use it for a different design than the original one. I
> would then have to test the device, and find where the defect is.
> 
> So my original question was: if I want to test a wire between CLB A
> and CLB B, how would I configure CLB A to force a 1 (or a 0) onto the
> wire? All the work I have seen (academic research) does not tell me
> how the test vectors are applied, the only say how they are analysed.
> 
> I would like to point out that I understand the limitations of these
> types of tests, and I do not want in any way breach any copyright from
> any manufacturer. I am just an FPGA enthusiast.
> 
> Best regards to all
> 
> Nick C
> 
> On Tue, 20 Jan 2004 17:05:50 +0000, BrakePiston
> <brakepiston@REMOVEyahoo.co.uk> wrote:
> 
> >Hi there, I am trying to gain a deeper understanding of the way
> >testing is conducted on FPGA devices. I am interested in BIST testing
> >for dynamic faults, not manufacturing testing.
> >
> >My question is: how exactly can you apply a test vector (or even just
> >a 1 or 0) to an interconnect line? Can you just connect the output of
> >a LUT to the wire and observe the output?
> >
> >I am asking this because of all the documentation I have read, nobody
> >mentions where they get the test vectors from.
> >
> >Am i just being stupid and failing to see the obvious here?
> >
> >Thanks very much
> >

Article: 65165
Subject: Re: spartan3 power supply
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 21 Jan 2004 09:19:32 -0800
Links: << >>  << T >>  << A >>
Avi, are you serious or just kidding?
Of course you have to use two regulators to generate the supply
voltages. Where do you think they would come from, and why do you think
we mention these requirements in the data sheet ?
And since the dynamic power consumption is proprtional to the clock
speed, the 80% figure tells nothing about power consumption.

Peter Alfke

Avi Halfon wrote:
> 
> Hi
> 
> i'm going to use spartan3 50K fpga .
> If i have a 3.3 input voltage to my card
> do i have to create 2.5V and 1.2V .
> i was wandering also what is the evarage current that the spartan3
> consume from those powers.
> 
> i will use something like 80% from the chip CLB's
> 
> Regards
> Avi Halfon

Article: 65166
(removed)


Article: 65167
Subject: mapping issues => Re: par problems with modular design for partial reconfiguration
From: nachikap@yahoo.com (Nachiket Kapre)
Date: 21 Jan 2004 09:38:28 -0800
Links: << >>  << T >>  << A >>
ok, i am trying to get the module placed manually but and am
encountering the following problems in map:-

1. if i try to place all the components in the module (i have a
structural code with xilinx library components) i get an error in map
saying "active module missing". so when to get arond that if i remove
even a single constraint from the ucf, the active module magically
reappears. the par still fails saying unroutable design with 38 nets.
2. if i try to assign constraints to internal nets that connect
modules together using the PIN constraint (is this really
necessay?....the modular design doc. refers to these signals as pseudo
logic in the ucf). i did seem to get better routing results with only
9 unrouted nets as against 38 unrouted in case.(1)

i still am completely at a loss to understand why a design with 16 2:1
muxes with 16 flops given an area constraint of half a column of width
4 SLICEs struggles with routing. also, when doing modular design, does
the router try to route the upper level signals?..because the router
quotes a large number of 134 unrouted nets to start off for the above
design. how does the modular design methodology deal with having to
route the top-level signal like clk,reset of fpga-io?..i sure hope it
doesn't bother itself with those signals while routing a module.

regards,
nachiket.

Ray Andraka <ray@andraka.com> wrote in message news:<400CB198.E254D27D@andraka.com>...
> take a look at what the placer did by opening the floorplanner.  I'll guarantee it ain't
> pretty.
> 
> Nachiket Kapre wrote:
> 
> > Ray Andraka <ray@andraka.com> wrote in message news:<400C5C7F.CABB1A2C@andraka.com>...
> > > Try constraining them to particular places.
> > I'm working on creating new constraint files to nail the muxes down to
> > specific slices within the column. hope it works..
> >
> > Depending on your
> > > constraints, it may be taking the placer some time to come up with a
> > > satisfactory placement, or may be taking the router a long time to route
> > > the mess the placer made.
> >
> > So the placer seems to be finishing off its job in abt 10 seconds.
> > I still dont understand how badly can a placer mess up on a design
> > this simple!...8 2:1 muxes?
> >
> > Also, you'll want to organize them as a column
> > > to minimize the reconfiguration time (reconfig happens by column), as well
> > > as to match up to any arithmetic you might have in the design.
> > >
> > point noted.
> >
> > thanks,
> > nachiket.
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Article: 65168
Subject: Re: BIST FPGA testing - Applying a test vector
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 21 Jan 2004 09:44:47 -0800
Links: << >>  << T >>  << A >>


Thomas Stanka wrote:
>
> Well, I believe you're achieving 100% of stuck-at failures, but do you
> really do some tests to achieve a 100% coverage for delay faults? I'm
> just curios because I know no way doing propper delay tests without a
> lot of additional testing hw on chip. But maybe there are some
> improvements made the last three years.

We do test the delay parameters very carefully and very thoroughly, by
many means, including on-chip oscillators. Instead of expensive on-chip
hardware, we use reconfiguration to reach the many subcircuits on the chip.

Don't forget, making and testing FPGAs is our livelihood. We have
invested many hundred man-years in the development and fine-tuning of
our test procedures. We must guarantee functionality and performance
over temperature and voltage extremes for each single part shipped. 

Apparently we know how to test our devices, otherwise we would not be in
business anymore.
> 
> Anyway, you can't do tests before selling a fpga, that replaces Bist
> for dynamic faults in the way I understood dynamic faults. Dynamic
> faults will occure sometime during lifetime of the fpga due to
> material aging or (especially in SRam based Fpgas) due to single event
> effects.

All Xilinx FPGAs support configuration readback, which can be performed
at any time, without any impact on the device operation. That's a BIST function.

The affect of aging is described in our reliability reports, and is
quantified in a number called FIT = failure in time. 1 FIT is one
failure in one thousand million ( american billion) device hours. This
is all well understood and documented. It is amazing that the FIT value
has remained fairly constant over the years, while device complexity has
increased thousandfold. Of course, that was necessary for the
penetration of ever more complex ICs into almost every aspect of
civilization. 

Single-event upsets are soft failures, mostly caused by various
radiation types. They can only be described in statistical terms, and
they disappear once data is re-written.  
This is a totally different subject...

Peter Alfke
>================================= 
> bye Thomas

Article: 65169
Subject: Re: SDRAM Controller timing problem
From: etraq@yahoo.fr (etrac)
Date: 21 Jan 2004 10:02:38 -0800
Links: << >>  << T >>  << A >>
Hi,

I think I have found the problem !! 
In fact my fpga was generating too much Refresh commands, I had a
period of 1.6µs instead of 15.6µs.
I did this to make sure datas will be good, but the fact is that it is
not the right way !

Peter > I already have a feedback for my DCM block. Otherwise I think
it will not work. What I was trying to say is that I already saw loops
that were external to the fpga, in order to deskew the external wires
that go to the Sdram clock pin. But like Pierre-Olivier said, if we
have one period of latency there is not any delay issue, even at
133MHz.

So thank you all trying to help me it is so greate to have such
support when we are in trouble, so much interesting suggestions have
been said here, and fpgas are very capricious when we begin using them
(even if this time it was not its fault :)

Etrac.


Ray Andraka <ray@andraka.com> wrote in message news:<400DCED6.3B9D5AB0@andraka.com>...
> Offset constraints have been around for a while, not new.  Anyway, if you
> register
> your I/O at the IOB, then the offset constraint isn't going to do anything for
> you except
> tell you when a flip-flop got pushed out of the IOB or that you set the drive
> strength/slew
> rate wrong.
> 
> SDRAM can be tricky, especially if you don't have external terminations.
> Higher slew
> rates and drive strengths can result in some nasty reflections that will sink
> even the most
> carefully executed FPGA design.  Use the minimum drive strength consistent with
> your
> timing analysis.  If possible use external terminations on the lines to the
> SDRAM (you can
> use DCI, but I've found that in addition to pushing the limits on package power
> dissipation,
> it is also slows the I/O down too much for SDRAM, especially without doing
> stuff with the
> DCM).
> 
> 
> 
> PO Laprise wrote:
> 
> > Once you've "pen and papered" your timing as Peter suggests, you might
> > want to look into the "OFFSET OUT" constraint in the constraint guide.
> > This allows you to give minimum "clock to off-chip" delays.  The router
> > will then take into account clock skew AND pad delays.  To constrain
> > your inputs, use the "OFFSET IN" constraint.  If your delays are already
> > minimal, it may not help, but at least you'll know.  Of course, you
> > still have to take all board delays into account yourself, which is why
> > it's important to pen-and-paper first.
> >
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Article: 65170
Subject: xilinx 70% tracking rule
From: guillerodriguez@terra.es (guille)
Date: 21 Jan 2004 10:07:42 -0800
Links: << >>  << T >>  << A >>
Hi there,

Sorry for another Xilinx-specific question :)

Peter Alfke mentioned this 70% tracking rule for timing parameters,
which basically says that if a parameter is at its max value, then all
other parameters are between 70% and 100% of their guaranteed maximums.
For Xilinx CPLDs, at least.

This makes a lot of sense from a physical standpoint, and I've seen
it mentioned in other posts too.

I have only one question, if somebody can help. How is this 70% figure
calculated, or estimated? Is it based on lab results only, or was it
first derived analytically in some way or another and then verified
experimentally? (I believe the latter). I'm curious about the physics
involved.

Thanks,
Guillermo Rodriguez

Article: 65171
(removed)


Article: 65172
(removed)


Article: 65173
Subject: Re: Tristate buffer
From: Tobias =?iso-8859-1?Q?M=F6glich?= <Tobias.Moeglich@gmx.net>
Date: Wed, 21 Jan 2004 19:35:16 +0100
Links: << >>  << T >>  << A >>
I can't see the coherence between a 3-state-buffer for a bus and a multiplexer.

What I want to design is following:

The data bus of  a microcontroller shall be connected to a true dual port RAM
of the Spartan-IIE.
The dual port RAM (generated by the CoreGenerator) has an input port (dina) and
an output port (douta)
because the data port  of the DPRAM is not bidirectional. So I try to put a
3-state buffer between the
data port lines of the controller and the data output port of the DPRAM
(douta).
The pins of the input port of the DPFRAM (dina) can be connected directly with
the data lines of the controller.(??)
I think this should work. Or?
But how to implement it? How is it expressed  in VHDL?

What has a 3-state-buufer to do with a multiplexer?
A multiplexer always chooses one out of 4,8, 16 (what ever) lines and directs
it with the output of the mux.
Isn't that the way a multiplexer works?? I thought so.
How can I use a mux instead of a 3-state buffer ??

Greatings, Tobias.



Article: 65174
Subject: Re: changing values in a fifo
From: PO Laprise <pl_N0SP4M_apri@cim._N0SP4M_mcgill.ca>
Date: Wed, 21 Jan 2004 18:37:31 GMT
Links: << >>  << T >>  << A >>
Eric Crabill wrote:
> I prefer the brute force method.  You could start by designing
> a FIFO using standard D flip flops, using the same type of design
> model that is used with RAMs (circular buffer with two pointers,
> move the pointers, not the data -- otherwise the problem gets more
> complicated).

If the FIFO is always full, does he even need to keep pointers?  Why not 
just a sort of "vector shift-register"?

-- 
Pierre-Olivier

-- to email me directly, remove all _N0SP4M_ from my address --




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