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Messages from 65075

Article: 65075
Subject: Re: par problems with modular design for partial reconfiguration
From: nachikap@yahoo.com (Nachiket Kapre)
Date: 19 Jan 2004 18:41:17 -0800
Links: << >>  << T >>  << A >>
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<400b1764@news.starhub.net.sg>...
> is it becuase the area is way too big for your codes?

wel actually it is! the muxes hardly take up 5-10 SLICEs whereas i
give an area constraint that spans the entire column! I' trying to
pack in more l;ogic into this column and will see what happens from
there on.


> 
> I also found that, Route Phase 1 takes most of the time, while other 8
> stages takes only a fraction of the total time...

Yeah that was my experience as well..wonder how the router works ?


> 
> In the tutorials I created at home, the slice numbers are 759(fixed) out of
> 1536, 292/338(reconfigurable) out of 1,536,
> the whole flow, from synthesis to assembly, only took 20 minutes...

So some runs of the router on certain mux columns in my design takes
seconds while the rest of the runs take about half an hour.. i think i
should try running them as separate designs with the same area
constraints without modular design flow to see if it takes just as
much time to do the routing..

> 
> Hope you could share your experiences after you finished the project...

certainly...

nachiket.

Article: 65076
Subject: Re: par problems with modular design for partial reconfiguration
From: nachikap@yahoo.com (Nachiket Kapre)
Date: 19 Jan 2004 18:43:41 -0800
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> wrote in message news:<400C5C7F.CABB1A2C@andraka.com>...
> Try constraining them to particular places.  
I'm working on creating new constraint files to nail the muxes down to
specific slices within the column. hope it works..

Depending on your
> constraints, it may be taking the placer some time to come up with a
> satisfactory placement, or may be taking the router a long time to route
> the mess the placer made.  

So the placer seems to be finishing off its job in abt 10 seconds.
I still dont understand how badly can a placer mess up on a design
this simple!...8 2:1 muxes?

Also, you'll want to organize them as a column
> to minimize the reconfiguration time (reconfig happens by column), as well
> as to match up to any arithmetic you might have in the design.
> 
point noted.

thanks,
nachiket.

Article: 65077
Subject: Re: par problems with modular design for partial reconfiguration
From: Ray Andraka <ray@andraka.com>
Date: Mon, 19 Jan 2004 23:42:00 -0500
Links: << >>  << T >>  << A >>
take a look at what the placer did by opening the floorplanner.  I'll guarantee it ain't
pretty.

Nachiket Kapre wrote:

> Ray Andraka <ray@andraka.com> wrote in message news:<400C5C7F.CABB1A2C@andraka.com>...
> > Try constraining them to particular places.
> I'm working on creating new constraint files to nail the muxes down to
> specific slices within the column. hope it works..
>
> Depending on your
> > constraints, it may be taking the placer some time to come up with a
> > satisfactory placement, or may be taking the router a long time to route
> > the mess the placer made.
>
> So the placer seems to be finishing off its job in abt 10 seconds.
> I still dont understand how badly can a placer mess up on a design
> this simple!...8 2:1 muxes?
>
> Also, you'll want to organize them as a column
> > to minimize the reconfiguration time (reconfig happens by column), as well
> > as to match up to any arithmetic you might have in the design.
> >
> point noted.
>
> thanks,
> nachiket.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 65078
Subject: Re: AFX BG560 board
From: "Adam" <unreal@rpi.edu>
Date: Tue, 20 Jan 2004 04:56:13 GMT
Links: << >>  << T >>  << A >>
> Thanks for ur reply in Google.com for my question about AFX Board.I
> have few more Doubts and it would be great if u would help me with
> that.Sorry more bothering you.
>
> 1.Now Once i download the configuration file to the fpga then i can use
> the area surrounding the Chip for reading out values in each pin
> through those area with logical analyzer.But why do we need the prototype
> area in the board on the left side.How can i use that.

You use the prototype area for any other circuitry you may want to interface
to the FPGA.  My design had no other circuits so this area was unused.  Plus
returning the board back to its original condition after solding to it isn't
easy.

> 2. Then to specify the I/O type.What is that.I am not clear.(your
> design must
> specify the I/O type to use(LVTTL, LVDS, etc)).If possible can u send
> me an simple code like showing this.

Many modern FPGAs support multiple I/O standards.  For instance, LVTTL uses
one 3.3 volt signaling line while LVDS uses the voltage difference between
two lines to carry one signal.  Here is an app note that describes what each
I/O standard uses:  http://www.xilinx.com/bvdocs/appnotes/xapp133.pdf.
So far in my designs with HDLs I use the vendor's schematic entry to do the
top level design.  So in my case I created a schematic symbol from my VHDL
design and then placed the symbol along with the I/Os in a schematic.  In
the ECS you should see the I/O category and then the various I/O buffers.
In an HDL I believe you have to instantiate the specific primitive available
in the FPGA and then set the attributes.  I'm in the process of learning
this way myself.



Article: 65079
Subject: Why doesn't NGDBuild recognize some UCF formatting?
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Tue, 20 Jan 2004 14:23:01 +0800
Links: << >>  << T >>  << A >>
Try out these few constraints, I don't understand NGDBuild allows space in
the LOC
while not in the signal name.

NET "out_bus( 9  )"  LOC = " AA2 ";
NET "out_bus( 8  )"  LOC = " C2 ";
NET "out_bus( 0  )"  LOC = " D2 ";

NET "out_sig      "  LOC = " B2 ";
NET "out_sig_1    "  LOC = " A2 ";
Kelvin




Article: 65080
Subject: Re: Memory Initialization Files in Modelsim
From: ALuPin@web.de (ALuPin)
Date: 19 Jan 2004 23:46:26 -0800
Links: << >>  << T >>  << A >>
Hello,

thank you for your answer.
I've tried out the following MACRO:

cd H:/EDA/Altera/USB/Packetfile_Ctrl/simulation/modelsim 
vlib modelsim_work
vmap work modelsim_work
vsim TB_CHECK_TRANSFER
vcom -93 -work work {D:/Programme/QuartusII/eda/sim_lib/220pack.vhd} 
vcom -explicit -work work
{D:/Programme/QuartusII/eda/sim_lib/220model.vhd}
vcom -work work {D:/Programme/QuartusII/libraries/vhdl93/altera_mf_components.vhd}
vcom -93 -work work {D:/Programme/QuartusII/eda/sim_lib/altera_mf.vhd}
vcom -work work {H:/EDA/Altera/USB/Check_Transfer/CHECK_TRANSFER.vhd}
vcom -work work {H:/EDA/Altera/USB/Check_Transfer/simulation/modelsim/TB_CHECK_TRANSFER.vhd}
view signals
view wave
vsim work.TB_CHECK_TRANSFER
run 15000ns

I get the following error message when executing the MACRO:

# -- Compiling architecture lpm_syn of lpm_ram_dq
# ** Error: D:/Programme/QuartusII/eda/sim_lib/220model.vhd(3586):
FILE declaration using 1076-1993 syntax.  Recompile using -93 switch.
# ** Error: D:/Programme/QuartusII/eda/sim_lib/220model.vhd(3586):
VHDL Compiler exiting
# ERROR: D:/Programme/win32aloem/vcom failed.
# Error in macro H:\EDA\Altera\USB_Extender\Check_Transfer\simulation\modelsim\tb_run.do
line 6
# D:/Programme/win32aloem/vcom failed.
#     while executing
# "vcom -work work {D:/Programme/QuartusII/eda/sim_lib/220model.vhd}
# "

Regards
Andres Vazquez
G & D
System Development


sdatta@altera.com (Subroto Datta) wrote in message news:<ca4d800d.0401191717.3ead4ea5@posting.google.com>...
> ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0401182339.27407c4f@posting.google.com>...
> > Dear Sir or Madam,
> > 
> > I want to simulate a VHDL design. It includes RAM structures
> > with .mif  files  (memory initialization files in QuartusII).
> > Modelsim seems not to support that kind of files.
> > So I use .hex files.   
> > In QuartusII they can be included in the MegaWizard-
> > PlugInManager.
> > But how do I involve these .hex files when simulating in Modelsim? 
> > Do they have to be compiled additionally to the
> > design VHDL files or do they have to be linked to in the testbench?
> > When trying to simulate after compiling the VHDL modules I get 
> > an error message "Fatal error ... altera_mf.vhd ... not found".
> > 
> > Kind regards
> > Andres Vazquez
> > G & D
> > System Development
> 
> If you have used the Megawizard PlugIn Manager and specified that the
> memory should be initialized along with the correct hex file, there is
> no additional step needed, to specify the memory files to Modelsim.
> You can verify this by opening the VHDL or Verilog file written out
> the Megawizard and check the INIT_FILE parameter. Its value should be
> the path to the hex file.
> 
> If you are using Modelsim SE/PE then use the following vcom commands
> in Modelsim (This is taken from the Quartus online help)
> 
> For VHDL 87-compliant designs: 
> 
> vcom -work work <path to library>\220pack.vhd 
> vcom [-87] -explicit -work work <path to library>\220model_87.vhd 
> vcom -work work <path to library>\altera_mf_components.vhd 
> vcom [-87] -work work <path to library>\altera_mf_87.vhd 
> vcom -work work <design name>.vhd 
> vcom -work work <test bench>.vhd 
> 
> For VHDL 93-compliant designs:
> 
> vcom -93 -work work <path to library>\220pack.vhd 
> vcom -explicit -work work <path to library>\220model.vhd 
> vcom -work work <path to library>\altera_mf_components.vhd 
> vcom -93 -work work <path to library>\altera_mf.vhd 
> vcom -work work <design name>.vhd 
> vcom -work work <test bench>.vhd 
> 
> where path to library would look like d:\quartus30\eda_simlib.
> 
> Hope this helps.
> 
> - Subroto Datta
> Altera Corp.

Article: 65081
Subject: Re: Memory Initialization Files in Modelsim
From: ALuPin@web.de (ALuPin)
Date: 20 Jan 2004 00:01:41 -0800
Links: << >>  << T >>  << A >>
Hi again,

sorry I have made an mistake in my MACRO:
Now I can execute the MACRO correctly, but nevertheless
the output of the RAM structure is 'X' in the simulation,
that is no initialization has be made on the RAM.

Kind regards
Andres Vazquez
G & D
System Development

cd H:/EDA/Altera/USB/Packetfile_Ctrl/simulation/modelsim 
vlib modelsim_work
vmap work modelsim_work
vsim TB_CHECK_TRANSFER
vcom -93 -work work {D:/Programme/QuartusII/eda/sim_lib/220pack.vhd} 
vcom -explicit -work work
{D:/Programme/QuartusII/eda/sim_lib/220model.vhd}
vcom -work work {D:/Programme/QuartusII/libraries/vhdl93/altera_mf/altera_mf_components.vhd}
vcom -93 -work work {D:/Programme/QuartusII/eda/sim_lib/altera_mf.vhd}
vcom -work work {H:/EDA/Altera/USB/Check_Transfer/CHECK_TRANSFER.vhd}
vcom -work work {H:/EDA/Altera/USB/Check_Transfer/simulation/modelsim/TB_CHECK_TRANSFER.vhd}
view signals
view wave
vsim work.TB_CHECK_TRANSFER
run 15000ns

Article: 65082
Subject: ISE 6.1 and Win2000 sp4
From: "Giuseppe³" <miaooaim.REMOVETHIS@tiscali.it>
Date: Tue, 20 Jan 2004 09:21:10 +0100
Links: << >>  << T >>  << A >>
Hi,
I'm running ISE6.1 on Win2000 sp2 system.
There is any problem if I install the sp4 ? Is ISE6.1 compatible with sp4?

Thank you
-- 
.
Ciao
Giuseppe



Article: 65083
Subject: Re: Good/Affordable Stater kits
From: "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com>
Date: Tue, 20 Jan 2004 10:21:21 +0200
Links: << >>  << T >>  << A >>
You may evaluate ActiveHDL . This is a extra user-friendly HDL
development/simulation environment and works with many synthesis tools
including WebPack XST. Sinthesis tools give an idea of how HW structure
looks like and programmable devices that can fit your design. When choosing
a board look at the devices it has.



Article: 65084
Subject: Re: Trouble using ChipsCope Pro with MicroBlaze
From: arkagaz@yahoo.com (arkaitz)
Date: 20 Jan 2004 00:36:26 -0800
Links: << >>  << T >>  << A >>
Thanks a lot for your help!!!

Best regards,

Arkaitz.

Article: 65085
Subject: Re: Send Ethernet traffic from an FPGA
From: "Jean Nicolle" <j.nicolle@sbcglobal.net>
Date: Tue, 20 Jan 2004 08:52:20 GMT
Links: << >>  << T >>  << A >>
Thanks for the *detailed* answer.
I used 3.3V IOs, so I need an 1:1.3 transformer to meet both amplitude and
return loss.
I guess that if I want to use common 1:1 transformers, I need 5V IOs and
50ohms resistors.

For the equalization and harmonic requirements, couldn't I use a filter?
27dB is pretty sharp though, doesn't seem easy.
Looking at some PHY/transformer schematics doesn't show any filter. Is it
usually provided inside the PHY?

Thanks,
Jean



Article: 65086
Subject: Re: Good/Affordable Stater kits
From: "Sumit Gupta" <do_not_reply_to_this_addr@yahoo.com>
Date: Tue, 20 Jan 2004 08:57:16 GMT
Links: << >>  << T >>  << A >>
Look at

http://www.c-nit.net

for a Spartan-II board.

Sumit

"x86asm" <isaac_8e@hotmail.com> wrote in message
news:45YOb.12249$7JB1.3852@news04.bloor.is.net.cable.rogers.com...
> Hi guys, I was wondering if there were any good starter kits you know of
> and where I am able to purchase them, I want to dip into VHDL a bit and
> try out my creations on a FPGA, nothing too fancy as I'm no engineer,
> just a hobbyist :) I saw one on Xilinx's online store for ~$50 US is
> that a good choice?
>



Article: 65087
Subject: Non deterministic routing in Quartus 3.0 ?
From: giachella.g@laben.it (g. giachella)
Date: 20 Jan 2004 03:12:34 -0800
Links: << >>  << T >>  << A >>
I have launched the place & route of the same project on two different
machines, a PC 2.6 GHz (WIN 2000) and a COMPAQ XEON 700 MHz
Workstation (WIN NT 4). Same project means same .vhd, .edf, .csf,
.psf, .ssf, .esf, .quartus files.
The QUARTUS release is the same (same build, same SP).
I obtained two different placements and two different compile times
(PC = 1h 40 min, Workstation = 5h 22 min): the file ..fit.rpt
evidences that the options "Use Local Routing Input" and "Use Local
Routing Output" were set differently between them during the
compilation.
As the project are the same and the seed is also the same, I would
expect identical place and route.

Any comment ? Am I missing somenthing ?

Thanks in advance

Article: 65088
Subject: Re: Help on qu@rtus memory initialization file
From: "Jeroen" <dev@null.com>
Date: Tue, 20 Jan 2004 12:57:07 +0100
Links: << >>  << T >>  << A >>

"sunroof" <sunroof_2002@yahoo.com> wrote in message
news:dadfb052.0401191302.2c1bce51@posting.google.com...
> In qu@rtus I could not find how to change the memory initialization
> file during simulation without re-compile.  As I remembered, in
> Max-Plus you just need to reload the new .mif file, no need to
> re-compile the project.
> Who knows how to do it in qu@rtus?
>
> Thx a lot.

if you turn on smart-complilation if will only run the assembler



Article: 65089
Subject: Re: Which version of ISE Webpack has FPGA Editor on it?
From: jacky Renaux <renaux.jacky_nospam@wanadoo.fr>
Date: 20 Jan 2004 11:59:07 GMT
Links: << >>  << T >>  << A >>

I 

I still use webpack 4.1 version (due to win98) and I have
fpga editor .. 

regards 

jacky


-- 
Ce message a ete poste via la plateforme Web club-Internet.fr
This message has been posted by the Web platform club-Internet.fr

http://forums.club-internet.fr/

Article: 65090
Subject: Small bit manipulation on two designs with routing differences...
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Tue, 20 Jan 2004 21:46:37 +0800
Links: << >>  << T >>  << A >>
Hi, everybody:

I have two similar designs the only difference is filtering(involving
registers and logic differences),
while the rest are same...Now I P& R them with the same guide file
containing the fixed portion...

If I do a bitgen to generate the difference bitstream of these two routed
designs, will it work on
hardware? The BitGen allows me to generate a 1kb bitstream...while the fixed
logic is 100kb+...

The wording in the XAPP290 is "not recomended", but does the contention
cause temporarily
mulfunction in the logic (which can be recovered with my design) or will the
contention burn the
FPGA chip?

Thanks for your advice.
Kelvin




Article: 65091
Subject: ERROR:HDLParsers:164
From: charlesg77@yahoo.com (chuk)
Date: 20 Jan 2004 06:30:38 -0800
Links: << >>  << T >>  << A >>
I have a corgen generated component in part of my design, when I go to
synthesize it, it comes up with this error:

ERROR:HDLParsers:164  &#8230;&#8230;. unexpected $

However when I synthesise the sub sections of the design that use this
same core, this works fine.  It seems to have a problem when I compile
the whole design.  Can any one help??

Article: 65092
Subject: Re: WTD: info on AMD palce22v10
From: pildistaja@hotmail.com (Raivo Nael)
Date: 20 Jan 2004 06:43:26 -0800
Links: << >>  << T >>  << A >>
I too think that FPGA-s in small packages would be great things. I
also think that this secrecy politics that programmable logic
manufacturers use, has made FPGA very imaginationless component. Look
at microcontrollers, how many different packages, architectures and so
on. And hunderds of different manufacturers.

Returning to original question - i too are interested in programmer or
programming algorithm for PALCE-s. GAL algorithms are available but
these can't be used here.

regards,
Raivo

Article: 65093
Subject: Re: Which version of ISE Webpack has FPGA Editor on it?
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 20 Jan 2004 15:24:53 +0000 (UTC)
Links: << >>  << T >>  << A >>
jacky Renaux <renaux.jacky_nospam@wanadoo.fr> wrote:

: I 

: I still use webpack 4.1 version (due to win98) and I have
: fpga editor .. 

At least 6.1 sp1 worked again with win98, according to rumors and my tests
with wine running as win98 incarnation.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 65094
Subject: Re: SDRAM Controller timing problem
From: etraq@yahoo.fr (etrac)
Date: 20 Jan 2004 07:41:30 -0800
Links: << >>  << T >>  << A >>
Hi,

   I have tried to apply your advices, but I still have the some bit
errors on my SDRAM modules.

   Jonathan > The SDRAM datasheets announce a Data presence from -2.1
to 2.7ns on rising edge. The fpga synchronizes Data directly in the
IOB but how can I know the pad timing ? Nevertheless I have tried to
change the IOB attributes (FAST, 24mA, DELAY=NONE, LVTTL). The SDRAM
clock is much better when I have 24mA, but the result is the same :(

   Manfred > I have checked the voltage, 3.280V with 0.130Vpkpk when
working, I have tried to rise up the voltage to 3.400V. the board has
a ground plane, short wires < 10cm, bypass capacitors for the fpga and
the sdram. I have a good LA and I can connect it to the fpga. I have
tried to see the SDRAM datas. I can see my bit errors in the SDRAM
read bursts, but not in single access writing mode.

   "Verilog USER" > I already have a Digital Clock Manager (DCM) on my
2x clock. I think one of its function is to deskew the clock. Do you
mean I must have a feedback from the clock ? I mean another pin which
is dedicated to feedback the SDRAM clock.

   I have only one DCM that generates the clock for the internal
controller and the external sdram. Do you think this may cause a
problem ? I have checked at the oscilloscope and sdram clock is
synchronized with the fpga oscillator. Is that mean the DCM works
correctly ?

   I spent many time to this problem and I have tried many
configurations without success. Could you eventually show me how you
have defined your pads, your clocks and your timing constraints ?

   Thank you,

   Jerome


"Verilog USER" <anonymous@xxx.com> wrote in message news:<se1Lb.8075$5k.3016@newssvr25.news.prodigy.com>...
> You may need to "deskew" the clock that you feed to the SDRAM to get it to
> work
> by using a DLL in the Xilinx FPGA
> 
> 
> "etrac" <etraq@yahoo.fr> wrote in message
> news:c99b95c7.0401070133.38f7e294@posting.google.com...
> > Hello,
> >
> > I have implemented my own SDRAM controller in a Virtex II component in
> > order to use SDRAM modules Sodimm-PC133 (133 MHz frequency).
> >
> > My problem is that this block seems to work very well with MICRON
> > Sdram modules, but it is not fully stable with SMART modules. It seems
> > to be the burst reading which causes some bit errors (not many, we
> > have at worst 25 bit errors on 32Mb files).
> >
> > I think the FPGA block is OK, routing timings are correct, and I think
> > my problem may be on SDRAM timings. I used 180° phase of my DCM to
> > generate control signals and bring back datas, in fact I work on the
> > falling edge of the SDRAM clock. I have tried to work on the rising
> > edge but then results are much uncertain !
> >
> > So my question is : Do you had some timing problems when controlling a
> > Sdram ? On which edge do you work ?
> >
> > etrac

Article: 65095
Subject: Re: ISE 6.1 and Win2000 sp4
From: "Hernán Sánchez" <hernan.sanchez@iname.com>
Date: Tue, 20 Jan 2004 10:51:02 -0500
Links: << >>  << T >>  << A >>
I have Webpack 6.1 Servicepack 3 on Windows 2000 SP4 and it's working Ok.  I
think it's something related.


Hernán Sánchez

"Giuseppe³" <miaooaim.REMOVETHIS@tiscali.it> escribió en el mensaje
news:buioe7$heakb$1@ID-61213.news.uni-berlin.de...
> Hi,
> I'm running ISE6.1 on Win2000 sp2 system.
> There is any problem if I install the sp4 ? Is ISE6.1 compatible with sp4?
>
> Thank you
> -- 
> .
> Ciao
> Giuseppe
>
>



Article: 65096
Subject: BIST FPGA testing - Applying a test vector
From: BrakePiston <brakepiston@REMOVEyahoo.co.uk>
Date: Tue, 20 Jan 2004 17:05:50 +0000
Links: << >>  << T >>  << A >>
Hi there, I am trying to gain a deeper understanding of the way
testing is conducted on FPGA devices. I am interested in BIST testing
for dynamic faults, not manufacturing testing.

My question is: how exactly can you apply a test vector (or even just
a 1 or 0) to an interconnect line? Can you just connect the output of
a LUT to the wire and observe the output?

I am asking this because of all the documentation I have read, nobody
mentions where they get the test vectors from.

Am i just being stupid and failing to see the obvious here?

Thanks very much



Article: 65097
Subject: Re: SDRAM Controller timing problem
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 20 Jan 2004 09:06:55 -0800
Links: << >>  << T >>  << A >>
See my comments below:
> I already have a Digital Clock Manager (DCM) on my
> 2x clock. I think one of its function is to deskew the clock. Do you
> mean I must have a feedback from the clock ? I mean another pin which
> is dedicated to feedback the SDRAM clock.

It seems to me that you are not really familiar with the functionality
of the DCM:
Yes, you need to drive the CLKFB. The DCM is a "servo"-controller. It
inserts the right amount of delay into its outputs, such that CLKIN and
CLKFB coincide in time. (It's kind of like an op-amp, where the
amplifier makes sure that there is no voltage between the two inputs.
The DCM makes sure that there is no delay between the two inputs.  But
in either case, this only works when you close the feedback loop.)
I think you need to analyze your timing "with pencil and paper", to
figure out the best approach. Just trying it out with and without
inverters is never going to get you a reliable design.
The DCM has terrific capabilities, including phase shifting with 50
picosecond increments, but you must first study its description.
One tip: Read the Spartan-3 description. Its DCM is practically
identical with the one in Virtex-II, but the text is newer and better,
in my opinion.

Peter Alfke, Xilinx Applications 
=================================
> 
>    I have only one DCM that generates the clock for the internal
> controller and the external sdram. Do you think this may cause a
> problem ? I have checked at the oscilloscope and sdram clock is
> synchronized with the fpga oscillator. Is that mean the DCM works
> correctly ?
> 
>

Article: 65098
Subject: Re: BIST FPGA testing - Applying a test vector
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Tue, 20 Jan 2004 10:16:22 -0800
Links: << >>  << T >>  << A >>
BrakePiston wrote:
> Hi there, I am trying to gain a deeper understanding of the way
> testing is conducted on FPGA devices. I am interested in BIST testing
> for dynamic faults, not manufacturing testing.

FPGA *devices* are tested at the factory.
The FPGA design function is tested using simulation.
Dynamic faults are eliminated by using
synchronous design style and by meeting static timing requirements.
> 
> My question is: how exactly can you apply a test vector (or even just
> a 1 or 0) to an interconnect line? Can you just connect the output of
> a LUT to the wire and observe the output?

In theory you can shift any pattern you like into the boundary scan
registers on any compliment device. In practice, this requires lots
of software to do anything useful. Here we license boundary scan software,
but use it only in production for the purpose of
finding solder opens and shorts on circuit boards.

> I am asking this because of all the documentation I have read, nobody
> mentions where they get the test vectors from.
> 
> Am i just being stupid and failing to see the obvious here?

I expect that the number of people actually doing functional test
of fpgas using boundary scan vectors is near zero. It would be
very difficult and very slow.


         -- Mike Treseler


Article: 65099
Subject: Re: Non deterministic routing in Quartus 3.0 ?
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Tue, 20 Jan 2004 10:27:30 -0800
Links: << >>  << T >>  << A >>
g. giachella wrote:
> I have launched the place & route of the same project on two different
> machines, a PC 2.6 GHz (WIN 2000) and a COMPAQ XEON 700 MHz
> Workstation (WIN NT 4). Same project means same .vhd, .edf, .csf,
> .psf, .ssf, .esf, .quartus files.
> The QUARTUS release is the same (same build, same SP).
> I obtained two different placements and two different compile times
> (PC = 1h 40 min, Workstation = 5h 22 min): the file ..fit.rpt
> evidences that the options "Use Local Routing Input" and "Use Local
> Routing Output" were set differently between them during the
> compilation.
> As the project are the same and the seed is also the same, I would
> expect identical place and route.
> 
> Any comment ? Am I missing somenthing ?

Your win2k box is faster than your nt box.

Lets assume that place & route is mostly compute bound.
In that case, if I didn't know the answer, I would
estimate the NT test time as:

(100 min) (2.6/.7) = 371 min = 6 hours


So you are doing better than I would expect.


     -- Mike Treseler




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