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Thanks, I appreciate it. It would be helpful to have a comprehensive readback
appnote that detailed all of the gotchas, both the ones that are by design and the
'ah-shits'. I know we stumbled on one or two during some of the radiation testing
experiments. In any event, I haven't seen anything that documents it as a complete
package. Readback induced problems can be subtle, and I imagine could be a nightmare
to diagnose without the nice patterns we were testing with. It would be very
beneficial to have all the data available to anyone who is attempting it. I'm once
again running into a "if you show me the documentation, I'll believe you"' situations
once again.
Austin Lesea wrote:
> Ray,
>
> As we all know, I am certainly not perfect, so I could be wrong here. I
> am checking. I was pretty confident that changing the address while
> trying to read hte LUTs affected the contents as they have to share
> circuitry, but the BRAM is a two port plus the config access, or really
> a three port memory as the addressing of the config is independent.
>
> I will post as soon as I know for sure....
>
> Austin
>
> Ray Andraka wrote:
>
> > Austin,
> >
> > Are you sure this is true for BRAM? As I understood it, the readback logic for
> > the BRAM in virtex is shared with part of the operational logic and you will
> > corrupt a user read if readback is performed on a BRAM while a user read is also
> > happening, ie, you need to either shut down the clock or have the user circuit
> > ignore read data. I'm hoping this was not conveyed to me properly, but my
> > source was rather emphatic (source was involved with the radiation testing at
> > LANL).
> >
> > Austin Lesea wrote:
> >
> >
> >>>If that BRAM was storing constants/lookup info (read only), then
> >>>I can see a need to verify the table is actually still correct ?
> >>
> >>If BRAM or LUTRAM is storing constants, then you may include it in the
> >>readback verify.
> >>
> >>
> >>>-jg
> >>>
> >
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 65376Ray, I was correct (still correct). Readback does not corrupt BRAM contents. But the config logic does take over the control of BRAM, so the user may not see what they expect while you are reading back (takes total control of ports A and B). I agree that readback has not been comprehensively described, and that is something that we are working on, since reading back is now becoming so useful and interesting. Austin Ray Andraka wrote: > Thanks, I appreciate it. It would be helpful to have a comprehensive readback > appnote that detailed all of the gotchas, both the ones that are by design and the > 'ah-shits'. I know we stumbled on one or two during some of the radiation testing > experiments. In any event, I haven't seen anything that documents it as a complete > package. Readback induced problems can be subtle, and I imagine could be a nightmare > to diagnose without the nice patterns we were testing with. It would be very > beneficial to have all the data available to anyone who is attempting it. I'm once > again running into a "if you show me the documentation, I'll believe you"' situations > once again. > > Austin Lesea wrote: > > >>Ray, >> >>As we all know, I am certainly not perfect, so I could be wrong here. I >>am checking. I was pretty confident that changing the address while >>trying to read hte LUTs affected the contents as they have to share >>circuitry, but the BRAM is a two port plus the config access, or really >>a three port memory as the addressing of the config is independent. >> >>I will post as soon as I know for sure.... >> >>Austin >> >>Ray Andraka wrote: >> >> >>>Austin, >>> >>>Are you sure this is true for BRAM? As I understood it, the readback logic for >>>the BRAM in virtex is shared with part of the operational logic and you will >>>corrupt a user read if readback is performed on a BRAM while a user read is also >>>happening, ie, you need to either shut down the clock or have the user circuit >>>ignore read data. I'm hoping this was not conveyed to me properly, but my >>>source was rather emphatic (source was involved with the radiation testing at >>>LANL). >>> >>>Austin Lesea wrote: >>> >>> >>> >>>>>If that BRAM was storing constants/lookup info (read only), then >>>>>I can see a need to verify the table is actually still correct ? >>>> >>>>If BRAM or LUTRAM is storing constants, then you may include it in the >>>>readback verify. >>>> >>>> >>>> >>>>>-jg >>>>> >>> >>> >>>-- >>>--Ray Andraka, P.E. >>>President, the Andraka Consulting Group, Inc. >>>401/884-7930 Fax 401/884-7950 >>>email ray@andraka.com >>>http://www.andraka.com >>> >>> "They that give up essential liberty to obtain a little >>> temporary safety deserve neither liberty nor safety." >>> -Benjamin Franklin, 1759 >>> >>> > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 65377
Mario Ivancic wrote: > Hi! > I would like to build isp cable for lattice CPLD (ispLSI 1016), but I > don't know how. > Can you help me? > > Best Regards, > Mario > > Maybe use our Chameleon POD product. With the same POD, you will be able to config and debug all ALTERA XILINX LATTICE CPLDs and FPGAs, and debug all popular processors like ARM7 ARM9 MIPS AVR PPC ColdFire and so more ... Check on www.amontec.com for a low cost universal JTAG solution : EUR159.- Laurent www.amontec.comArticle: 65378
Mario Ivancic wrote: > Hi! > I would like to build isp cable for lattice CPLD (ispLSI 1016), but I > don't know how. > Can you help me? The schematic is on the Lattice web site. Leon -- Leon Heller, G1HSM Email: aqzf13@dsl.pipex.com My low-cost Philips LPC210x ARM development system: http://www.geocities.com/leon_heller/lpc2104.htmlArticle: 65379
Austin,
I don't think I said it corrupted the contents. I thought I said it corrupted the user
read of the contents. The point is, you can't read the BRAM while the user circuit is
running without messing up the user function. You either need to stop the clock, or the
user circuit has to somehow know it can't expect good data from the BRAM and deal with it
accordingly. One work around would be to use ECC and spread the read word width over
multiple BRAMs situated in different columns. Again, the designer has to be aware that
this behavior happens during readback. I don't think this particular one was documented
when we were looking at it, even though it was apparently an intentional behavior.
In the case of CLBRAM or SRL16's, one must be even more careful, because there, a readback
at the wrong time can actually corrupt the contents rather than just the read value. I
believe that one is a problem if the user circuit is changing the lut content (eg clocking
with WE='1') while a readback of that cell is occuring. That one seemed like it was not an
intentional behavior, and I've yet to see it documented anywhere. I've had two customers
run into this one, fortunately with the second one as soon as they told me that they were
doing readback, I knew what the problem was.
Keep up the good work. BTW, what is the latest on availability dates for the QPRO version
(space qual'd) virtexII? I've got a project right now where a V2 would save a bunch of
headache, but it has to be real relatively soon in order to make the launch schedule. I
can use which ever one comes out first. The design is currently slated for a pair of
V1000's, only because of the internal memory requirements. 75% of the logic in the V1000
prototype is SRL16's used as a delay buffer because we used up the BRAMs.
Austin Lesea wrote:
> Ray,
>
> I was correct (still correct). Readback does not corrupt BRAM contents.
> But the config logic does take over the control of BRAM, so the user
> may not see what they expect while you are reading back (takes total
> control of ports A and B).
>
> I agree that readback has not been comprehensively described, and that
> is something that we are working on, since reading back is now becoming
> so useful and interesting.
>
> Austin
>
> Ray Andraka wrote:
> > Thanks, I appreciate it. It would be helpful to have a comprehensive readback
> > appnote that detailed all of the gotchas, both the ones that are by design and the
> > 'ah-shits'. I know we stumbled on one or two during some of the radiation testing
> > experiments. In any event, I haven't seen anything that documents it as a complete
> > package. Readback induced problems can be subtle, and I imagine could be a nightmare
> > to diagnose without the nice patterns we were testing with. It would be very
> > beneficial to have all the data available to anyone who is attempting it. I'm once
> > again running into a "if you show me the documentation, I'll believe you"' situations
> > once again.
> >
> > Austin Lesea wrote:
> >
> >
> >>Ray,
> >>
> >>As we all know, I am certainly not perfect, so I could be wrong here. I
> >>am checking. I was pretty confident that changing the address while
> >>trying to read hte LUTs affected the contents as they have to share
> >>circuitry, but the BRAM is a two port plus the config access, or really
> >>a three port memory as the addressing of the config is independent.
> >>
> >>I will post as soon as I know for sure....
> >>
> >>Austin
> >>
> >>Ray Andraka wrote:
> >>
> >>
> >>>Austin,
> >>>
> >>>Are you sure this is true for BRAM? As I understood it, the readback logic for
> >>>the BRAM in virtex is shared with part of the operational logic and you will
> >>>corrupt a user read if readback is performed on a BRAM while a user read is also
> >>>happening, ie, you need to either shut down the clock or have the user circuit
> >>>ignore read data. I'm hoping this was not conveyed to me properly, but my
> >>>source was rather emphatic (source was involved with the radiation testing at
> >>>LANL).
> >>>
> >>>Austin Lesea wrote:
> >>>
> >>>
> >>>
> >>>>>If that BRAM was storing constants/lookup info (read only), then
> >>>>>I can see a need to verify the table is actually still correct ?
> >>>>
> >>>>If BRAM or LUTRAM is storing constants, then you may include it in the
> >>>>readback verify.
> >>>>
> >>>>
> >>>>
> >>>>>-jg
> >>>>>
> >>>
> >>>
> >>>--
> >>>--Ray Andraka, P.E.
> >>>President, the Andraka Consulting Group, Inc.
> >>>401/884-7930 Fax 401/884-7950
> >>>email ray@andraka.com
> >>>http://www.andraka.com
> >>>
> >>> "They that give up essential liberty to obtain a little
> >>> temporary safety deserve neither liberty nor safety."
> >>> -Benjamin Franklin, 1759
> >>>
> >>>
> >
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 65380Yes. There is an internal JTag tap that can be "tapped into" If you want to use the PPC Jtag you have to use the internal tap symbol. Also If you load via the select map you can have pins from the Xilinx route outside to the jtag pins. I sure there are other ways also. Steve "BrakePiston" <brakepiston@REMOVEyahoo.co.uk> wrote in message news:h6qs001vj8noonjnh9mbdocdsc5iu1ve16@4ax.com... > Hi everybody, just a quick question. > > Can the PowerPC in a Virtex II Pro, be routed to control the JTAG > hardware? By that I mean provide instruction and data to the TAP > > Thanks!! > > >Article: 65381
Hi Peter, The delay of the interconnect is both easy and complicated to give you. The quick answer is yes, we know the average delay of these resources (see unofficial table below). I'll enquire as to why we don't have delays or delay ranges specified in the data sheet. The long answer is that the delay of a given resource in Quartus will vary due to a variety of reasons. - # of active fanouts along the line (usually 1-2, but could be high depending on route) - # of inactive loads long the wire (doesn't vary too much) - # of partially active loads -- these can happen when a two-stage mux has multiple 1st stage inputs turned on due to sharing of configuration RAM bits. - Distance traveled. If you travel only four units along an R24 wire, you won't get the full RC delay due to resistive shielding of down-stream capacitance. - Edge rate of incoming signal. This in turn is affected by the resource used previously -- a R24 -> R4 could have different edge rate than R4 -> R4. It will also be affected by that resource's loading. - Blocks passed. An R4 wire that passes over four LABs will be different in length (physically) than an R4 that crosses an M4K block + three LABs. Also, a C4 wire next to a clock spine may have slightly greater loading than one between two LABs. - Exact wire used. Two different R4 wires that appear identical in all these ways can have different timing due to what metal layer they are routed on or due to physical proximity to other wires being different. - Rising/falling transition. Delay can vary depending on whether the input is a rising or falling transition. Quartus will give you the right answer to routing delay. All these factors do is make it a little more difficult to predict the precise delay you will see in advance of timing analysis. The allocation of delay to a particular resource in a full routing path is somewhat arbitrary and depends on measurement points and how we choose to bin the delay. The following data was extracted from the critical paths of a large number of typical user designs, and thus is representative of the types of paths that tend to occur on the critical path. It is not the maximum nor minimum delay you will see on this type of resource. Stratix -5 Routing Delays (Mux + Buffer + Wire): R4 303 ps R8 373 ps R24 503 ps C4 467 ps C8 650 ps C16 525 ps LAB Line 463 ps LE Output 231 ps Local Line 353 ps Regards, Paul Leventis Altera Corp.Article: 65382
Hi Leon, I looked on Lattice web site and did not find the schematic for the ispLSI 1016 ( or any other for that matter ). If you have a link that has a _real_schematic_, thats compatible with their software, please post it. hamilton Leon Heller wrote: > > > Mario Ivancic wrote: > >> Hi! >> I would like to build isp cable for lattice CPLD (ispLSI 1016), but I >> don't know how. >> Can you help me? > > > The schematic is on the Lattice web site. > > LeonArticle: 65383
>I would like to build isp cable for lattice CPLD (ispLSI 1016), but I >don't know how. A Google find: http://digital5.ece.tntech.edu/Public/611/Clements%20CDROM/DATA/ISP/MANUAL.PDF Page 2-12 -- http://www.iki.fi/mkl The Reply-To address is valid, but filtered against spam, spam with junk-mail, spam with bulk-email, and spam with spam.Article: 65384
>>I would like to build isp cable for lattice CPLD (ispLSI 1016), but I >>don't know how. >A Google find: >http://digital5.ece.tntech.edu/Public/611/Clements%20CDROM/DATA/ISP/MANUAL.PDF >Page 2-12 The above is from Lattice. Another google find, with minimal amount of parts: http://www.rottmerhusen.com/isplsi_dl-cable.html -- http://www.iki.fi/mkl The Reply-To address is valid, but filtered against spam, spam with junk-mail, spam with bulk-email, and spam with spam.Article: 65385
Kelvin @ SG wrote: > Hi, there: > > I am performing partial reconfiguration tutorial. How do I fix this error in > the final assembly stage? > > Thanks for your advice. > Kelvin > > > Starting Guide File Processing. > > Loading device database for application Par from file > "../../pims/iq_gen/iq_gen.ncd". > "sig_gen" is an NCD, version 2.38, device xc2v250, package fg256, > speed -4 > The STEPPING level for this design is 1. > FATAL_ERROR:Guide:basgitaskphyspr.c:255:1.28.20.2:137 - Guide encountered a > Logic0 or Logic1 signal GLOBAL_LOGIC1_32 that does not have a driver or > load > within the module boundary. This problem may be caused by having a > constant > driving the input from outside the module boundary or because a driver or > load comp did not meet the par-guiding criteria. The design will not be > completely placed and routed by Par-Guide Process will terminate. To > resolve this error, please consult the Answers Database and other online > resources at http://support.xilinx.com. If you need further assistance, > please open a Webcase by clicking on the "WebCase" link at > http://support.xilinx.com > Hi Kelvin, try checking all your constant signals. especially the ones connected to your bus macros and clock buffer(s). greets simonArticle: 65386
Hi all, I'm designing a IP core to work together with MicroBlaze. I have attached as a OPB Slave and it works fine. Now I want to add an interruption port so that it can provoke an interruption to MicroBlaze through the Interruption Controller provided by Xilinx. But, I am having some trouble when generating the libraries. Libgen gives the next error: ERROR:MDT - xget_value 16070968 27595288 NAME : A NULL handle was provided ERROR:MDT - expected integer but got "16070968 27595288" I've been looking at the Lab2 design from Xilinx because it incorporates a timer that interrupts the up. In the MSS file of the timer is defined the interruption handler with the next sentences: PARAMETER int_handler = timer_int_handler, int_port = Interrupt How do I define this for my IP core? Do I have to create a driver? Thanks in advance, Arkaitz.Article: 65388
Hi All, Has anyone had any success using a Parallel Cable III (PC3) under Linux to program a Xilinx FPGA using JTAG? I know that Impact (from ise 6.1) does not support the cable (Which is totally absurd). But is there some other software that I can use? Unfortunately I'm in a real hurry to get this sorted, so can't wait for ISE 6.2 which is supposed to support the PC3. Many many thanks Andy -- Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.comArticle: 65389
On Fri, 23 Jan 2004 00:02:19 +1100, Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote: >Hi, > >Does anyone know if XST 6.1.3 supports the "indexed part select" >feature of Verilog 2001? (It's in section 4.2.1 of the LRM.) > >The Xilinx documentation states explicitly that it does support this >feature, yet when I try to use it, I get this error message: > >ERROR:Xst:850 - foo.v line 134: Unsupported . > >Example code: > >reg [7:0] bar; >wire [31:0] foo; > >genvar j; >generate > for (j=0; j<8; j=j+1) begin : label > always @(posedge clk) > // error on next line: > bar[j] <= &foo[4*j +: 4]; > end >endgenerate > >Is there something special I have to do to enable 2001 support? > >Thanks, >Allan. The Xilinx support guy suggested this (inappropriate) code as a workaround, then closed the case before I'd had a chance to respond. :( module test_module(bar,foo,clk); output [31:0] bar; input [31:0] foo; input clk; reg [31:0] bar ; wire [31:0] foo ; genvar j; generate for (j = 0 ; j < 8 ; j = j + 1) begin : label always @ (posedge clk) bar[j] <= &foo[4*j + 2] ; end endgenerate endmodule Regards, Allan.Article: 65390
On 01/27/2004 10:41 AM, Andrew Greensted wrote: > Has anyone had any success using a Parallel Cable III (PC3) under Linux > to program a Xilinx FPGA using JTAG? > > I know that Impact (from ise 6.1) does not support the cable (Which is > totally absurd). But is there some other software that I can use? <http://groups.google.de/groups?q=linux+xilinx+programmer> I have never tried these programs, but I think it a good start. Perhaps someone else here comes up with a better solution. HTH & HAND, SteffArticle: 65391
Ray, The devices will be release by the end of Q1 (the 2V1000/2V3000/2V6000) - the only gating item is the completion of the package qual. Email me directly for more information... Thanks Jason Moore Xilinx Mil/Aero Division Ray Andraka <ray@andraka.com> wrote in message news:<4015C304.23292891@andraka.com>... > Austin, > > I don't think I said it corrupted the contents. I thought I said it corrupted the user > read of the contents. The point is, you can't read the BRAM while the user circuit is > running without messing up the user function. You either need to stop the clock, or the > user circuit has to somehow know it can't expect good data from the BRAM and deal with it > accordingly. One work around would be to use ECC and spread the read word width over > multiple BRAMs situated in different columns. Again, the designer has to be aware that > this behavior happens during readback. I don't think this particular one was documented > when we were looking at it, even though it was apparently an intentional behavior. > > In the case of CLBRAM or SRL16's, one must be even more careful, because there, a readback > at the wrong time can actually corrupt the contents rather than just the read value. I > believe that one is a problem if the user circuit is changing the lut content (eg clocking > with WE='1') while a readback of that cell is occuring. That one seemed like it was not an > intentional behavior, and I've yet to see it documented anywhere. I've had two customers > run into this one, fortunately with the second one as soon as they told me that they were > doing readback, I knew what the problem was. > > Keep up the good work. BTW, what is the latest on availability dates for the QPRO version > (space qual'd) virtexII? I've got a project right now where a V2 would save a bunch of > headache, but it has to be real relatively soon in order to make the launch schedule. I > can use which ever one comes out first. The design is currently slated for a pair of > V1000's, only because of the internal memory requirements. 75% of the logic in the V1000 > prototype is SRL16's used as a delay buffer because we used up the BRAMs. > > > Austin Lesea wrote: > > > Ray, > > > > I was correct (still correct). Readback does not corrupt BRAM contents. > > But the config logic does take over the control of BRAM, so the user > > may not see what they expect while you are reading back (takes total > > control of ports A and B). > > > > I agree that readback has not been comprehensively described, and that > > is something that we are working on, since reading back is now becoming > > so useful and interesting. > > > > Austin > > > > Ray Andraka wrote: > > > Thanks, I appreciate it. It would be helpful to have a comprehensive readback > > > appnote that detailed all of the gotchas, both the ones that are by design and the > > > 'ah-shits'. I know we stumbled on one or two during some of the radiation testing > > > experiments. In any event, I haven't seen anything that documents it as a complete > > > package. Readback induced problems can be subtle, and I imagine could be a nightmare > > > to diagnose without the nice patterns we were testing with. It would be very > > > beneficial to have all the data available to anyone who is attempting it. I'm once > > > again running into a "if you show me the documentation, I'll believe you"' situations > > > once again. > > > > > > Austin Lesea wrote: > > > > > > > > >>Ray, > > >> > > >>As we all know, I am certainly not perfect, so I could be wrong here. I > > >>am checking. I was pretty confident that changing the address while > > >>trying to read hte LUTs affected the contents as they have to share > > >>circuitry, but the BRAM is a two port plus the config access, or really > > >>a three port memory as the addressing of the config is independent. > > >> > > >>I will post as soon as I know for sure.... > > >> > > >>Austin > > >> > > >>Ray Andraka wrote: > > >> > > >> > > >>>Austin, > > >>> > > >>>Are you sure this is true for BRAM? As I understood it, the readback logic for > > >>>the BRAM in virtex is shared with part of the operational logic and you will > > >>>corrupt a user read if readback is performed on a BRAM while a user read is also > > >>>happening, ie, you need to either shut down the clock or have the user circuit > > >>>ignore read data. I'm hoping this was not conveyed to me properly, but my > > >>>source was rather emphatic (source was involved with the radiation testing at > > >>>LANL). > > >>> > > >>>Austin Lesea wrote: > > >>> > > >>> > > >>> > > >>>>>If that BRAM was storing constants/lookup info (read only), then > > >>>>>I can see a need to verify the table is actually still correct ? > > >>>> > > >>>>If BRAM or LUTRAM is storing constants, then you may include it in the > > >>>>readback verify. > > >>>> > > >>>> > > >>>> > > >>>>>-jg > > >>>>> > > >>> > > >>> > > >>>-- > > >>>--Ray Andraka, P.E. > > >>>President, the Andraka Consulting Group, Inc. > > >>>401/884-7930 Fax 401/884-7950 > > >>>email ray@andraka.com > > >>>http://www.andraka.com > > >>> > > >>> "They that give up essential liberty to obtain a little > > >>> temporary safety deserve neither liberty nor safety." > > >>> -Benjamin Franklin, 1759 > > >>> > > >>> > > > > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, 1759 > > > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 65392
Yes, I've seen this, unfortunately it doesn't use the JTAG chain for programming. It uses Slave Serial instead. Thanks though Andy Stefan Frank wrote: > On 01/27/2004 10:41 AM, Andrew Greensted wrote: > >> Has anyone had any success using a Parallel Cable III (PC3) under >> Linux to program a Xilinx FPGA using JTAG? >> >> I know that Impact (from ise 6.1) does not support the cable (Which is >> totally absurd). But is there some other software that I can use? > > > <http://groups.google.de/groups?q=linux+xilinx+programmer> > > I have never tried these programs, but I think it a good start. > Perhaps someone else here comes up with a better solution. > > HTH & HAND, > SteffArticle: 65393
Hi, I'm using pjcli to create a project file for ISE 6.1. Now I want to create libraries in my project and add some source files to it: AddLibrary(reuselib, ..\..\reuselib\vhdl_sources, true); MoveToLibrary(..\..\reuselib\vhdl_sources\async_fifo.vhd, reuselib); Now it should be possible to use this library in a vhdl file by typing: "library reuselib". However, using the above commands give an error on the path for the line AddLibrary and it looks like it doesn't support relative paths (even if I use "SetPreference(PathType, Relative)"). Does anyone know how to use these two commands. TIA, FrankArticle: 65394
Hello,
I'm supposed to set up a new VHDL/FPGA lab at our university. But I'm
unsure which operation system and programming solution to use.
Maybe some of you have experience setting up a lab and can answer some
questions.
We already have the Xilinx ISE Software 6.1i for PC/Solaris/Linux and
Synopsys Software for Solaris and Linux through a Europractice license.
We also have an "old" DLC4 and XC4005, but I guess it's not worth trying
to make that work. (As far as I could find out, DLC4 is not supported
anymore even for ISE 4.2.)
So here are my questions:
1. Which operating system supplies the best performance/environment for
Xilinx development?
I read that the supplied ModelSim II XE works only on PCs, not on
Solaris or Linux. So would you prefer a PC, because of the included
simulation environment?
2. If a Solaris/Linux environment is concerned, which simulator is
available/usable? Is Synopsys' scirocco usable?
3. Which Download Cable would you recommend? Does the Parallel Cable
only work with a PC (I read that somewhere)?
Or would you prefer the Multilinx Cable? (If so, why?)
4. Regarding the programming of the FPGA, would you recommend a separate
design/program environment (e.g. Some Solaris Workstations for
design, and one PC just for programming and testing on a FPGA)?
I hope someone can enlighten me a bit!
Regards,
Marcus
Article: 65395Ray, Excellent summary of the operation. All perfectly correct. V2P QPRO is still in progress, as we were "in the beam" at LANSCE just last week. So far, so good. Austin Ray Andraka wrote: > Austin, > > I don't think I said it corrupted the contents. I thought I said it corrupted the user > read of the contents. The point is, you can't read the BRAM while the user circuit is > running without messing up the user function. You either need to stop the clock, or the > user circuit has to somehow know it can't expect good data from the BRAM and deal with it > accordingly. One work around would be to use ECC and spread the read word width over > multiple BRAMs situated in different columns. Again, the designer has to be aware that > this behavior happens during readback. I don't think this particular one was documented > when we were looking at it, even though it was apparently an intentional behavior. > > In the case of CLBRAM or SRL16's, one must be even more careful, because there, a readback > at the wrong time can actually corrupt the contents rather than just the read value. I > believe that one is a problem if the user circuit is changing the lut content (eg clocking > with WE='1') while a readback of that cell is occuring. That one seemed like it was not an > intentional behavior, and I've yet to see it documented anywhere. I've had two customers > run into this one, fortunately with the second one as soon as they told me that they were > doing readback, I knew what the problem was. > > Keep up the good work. BTW, what is the latest on availability dates for the QPRO version > (space qual'd) virtexII? I've got a project right now where a V2 would save a bunch of > headache, but it has to be real relatively soon in order to make the launch schedule. I > can use which ever one comes out first. The design is currently slated for a pair of > V1000's, only because of the internal memory requirements. 75% of the logic in the V1000 > prototype is SRL16's used as a delay buffer because we used up the BRAMs. > > > Austin Lesea wrote: > > >>Ray, >> >>I was correct (still correct). Readback does not corrupt BRAM contents. >> But the config logic does take over the control of BRAM, so the user >>may not see what they expect while you are reading back (takes total >>control of ports A and B). >> >>I agree that readback has not been comprehensively described, and that >>is something that we are working on, since reading back is now becoming >>so useful and interesting. >> >>Austin >> >>Ray Andraka wrote: >> >>>Thanks, I appreciate it. It would be helpful to have a comprehensive readback >>>appnote that detailed all of the gotchas, both the ones that are by design and the >>>'ah-shits'. I know we stumbled on one or two during some of the radiation testing >>>experiments. In any event, I haven't seen anything that documents it as a complete >>>package. Readback induced problems can be subtle, and I imagine could be a nightmare >>>to diagnose without the nice patterns we were testing with. It would be very >>>beneficial to have all the data available to anyone who is attempting it. I'm once >>>again running into a "if you show me the documentation, I'll believe you"' situations >>>once again. >>> >>>Austin Lesea wrote: >>> >>> >>> >>>>Ray, >>>> >>>>As we all know, I am certainly not perfect, so I could be wrong here. I >>>>am checking. I was pretty confident that changing the address while >>>>trying to read hte LUTs affected the contents as they have to share >>>>circuitry, but the BRAM is a two port plus the config access, or really >>>>a three port memory as the addressing of the config is independent. >>>> >>>>I will post as soon as I know for sure.... >>>> >>>>Austin >>>> >>>>Ray Andraka wrote: >>>> >>>> >>>> >>>>>Austin, >>>>> >>>>>Are you sure this is true for BRAM? As I understood it, the readback logic for >>>>>the BRAM in virtex is shared with part of the operational logic and you will >>>>>corrupt a user read if readback is performed on a BRAM while a user read is also >>>>>happening, ie, you need to either shut down the clock or have the user circuit >>>>>ignore read data. I'm hoping this was not conveyed to me properly, but my >>>>>source was rather emphatic (source was involved with the radiation testing at >>>>>LANL). >>>>> >>>>>Austin Lesea wrote: >>>>> >>>>> >>>>> >>>>> >>>>>>>If that BRAM was storing constants/lookup info (read only), then >>>>>>>I can see a need to verify the table is actually still correct ? >>>>>> >>>>>>If BRAM or LUTRAM is storing constants, then you may include it in the >>>>>>readback verify. >>>>>> >>>>>> >>>>>> >>>>>> >>>>>>>-jg >>>>>>> >>>>> >>>>> >>>>>-- >>>>>--Ray Andraka, P.E. >>>>>President, the Andraka Consulting Group, Inc. >>>>>401/884-7930 Fax 401/884-7950 >>>>>email ray@andraka.com >>>>>http://www.andraka.com >>>>> >>>>>"They that give up essential liberty to obtain a little >>>>> temporary safety deserve neither liberty nor safety." >>>>> -Benjamin Franklin, 1759 >>>>> >>>>> >>> >>> >>>-- >>>--Ray Andraka, P.E. >>>President, the Andraka Consulting Group, Inc. >>>401/884-7930 Fax 401/884-7950 >>>email ray@andraka.com >>>http://www.andraka.com >>> >>> "They that give up essential liberty to obtain a little >>> temporary safety deserve neither liberty nor safety." >>> -Benjamin Franklin, 1759 >>> >>> > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 65396
Hi I want to make a project that uses an image sensor (any perhaps a low power cmos from Micron or Kodak) connected to a FPGA (or CPLD). with the apropriate VHDL or Veralog code. Has anyone done this who would be willing to share there hardware and/or software designs to get me started? Or is there any examples on the web that I can explore? Martin mart NO inb SPAM AT magma DOT ca Remove the NO SPAM and put no spaces. Also replace the AT for @ and the DOT for . or post replies ThanksArticle: 65397
Andrew Greensted <ajg112@ohm.york.ac.uk> wrote: : Yes, I've seen this, unfortunately it doesn't use the JTAG chain for : programming. It uses Slave Serial instead. Have a look at http://www.nahitech.com/nahitafu/naxjp/naxjp-e.html and at Rudolf Usselman tool http://www.asics.ws/tools/ljp.c.gz Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 65398
Hi, I would like to use a file. rif in a functional Simulation (VHDL) with ModelSim-Altera Software. (RAM initialisation). Does anyone have information, or better an example to use this file ?. Thanks. H.Article: 65399
Hello, Is anyone out there experienced in building macros. As soon as my macros contain external pins I cannot reopen them in "FPGA Editor". "FPGA Editor" crashes displaying the following message: FATAL_ERROR:Ncd:basncmacrodef.c:1470:1.31 - Mangled nmc file start property read <0xfffcacc>. Process will terminate. To resolve this error, please consult the Answers Databas and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com I'm a student, so I am not allowed to open a webcase... Regards Simon
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