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Messages from 66525

Article: 66525
Subject: Re: Serial ATA with Xilinx RocketIO (Virtex 2 Pro)??
From: =?iso-8859-1?Q?Michael_Sch=F6berl?= <MSchoeberl@ratnet.stw.uni-erlangen.de>
Date: Sat, 21 Feb 2004 10:06:54 +0100
Links: << >>  << T >>  << A >>
> as much as I got informatiom from Xilinx then, well ML300 board has SATA
> connectors but they are unuseabel as SATA :(
> so, NO there is no OOB support and SATA with RocketIO in V2Pro.

have you found an other way to use serial ata with an FPGA?

Silicon Image hat a 2port serial ata phy (Sil3012) but I have not seen 
a datasheet yet. It has a 150MHz DDR interface and about the same
pin count as parallel ata :-(


bye,
Michael


Article: 66526
Subject: Lead Free Packages
From: news@sulimma.de (Kolja Sulimma)
Date: 21 Feb 2004 01:45:23 -0800
Links: << >>  << T >>  << A >>
Were do I need to turn to purchase lead free Xilinx parts?
Insight in Germany tells me that there are no 
XC2Sxx-PQG208 parts and no
XC3Sxx-FTG256 parts listed.

The problem is the following: 
http://europa.eu.int/eur-lex/pri/en/oj/dat/2003/l_037/l_03720030213en00190023.pdf

In the EU no electronic equipment containing lead may be sold by july
2006.
My most important product has very low volume and therefore a single
charge of products is in stock for more than a year. With manufacturer
lead times of 16 week (take from a recent distributor quote) I will
need to start ordering lead free parts this summer.
It makes me a little nervous that the distri never heard about the
Xilinx -G packages.
It doesn't help, that the lead free parts are not listed in the
datasheets.

What are your experience? 
Did anybody order lead free Xilinx FPGAs yet? 
What about other manufacturers?

Kolja Sulimma

BTW: 
Networking equipment is excempt from the directive so that there will
still be millions of leaded FPGAs be sold in europe.

Article: 66527
Subject: Re: GZIP algorithm in FPGA
From: =?iso-8859-1?Q?Michael_Sch=F6berl?= <MSchoeberl@ratnet.stw.uni-erlangen.de>
Date: Sat, 21 Feb 2004 10:49:51 +0100
Links: << >>  << T >>  << A >>
> Isn't there a variation that generates the table on the fly?
Yes there is ... it is called Golomb Rice coding ... 

Its a Huffman-variation and it assumes a geometric distribution 
At the moment im still simulating in C to estimate the coding
performance - FPGA implementation should be easy ...
it seems to work quite well on dpcm-images ...


bye,
Michael


Article: 66528
Subject: Re: Dhrystone figures - Was: Microblaze instruction timings
From: jon@beniston.com (Jon Beniston)
Date: 21 Feb 2004 04:46:26 -0800
Links: << >>  << T >>  << A >>
> That said, I agree what you're seeing is a bit high - we've seen 0.4
> (SDRAM + cache) to 0.5DMips/mhz (on-chip mem) for 32-bit "classic"
> Nios. It makes me wonder if there is some difference in code?

When I said simulator, I meant the software simulator that comes as
part of the GNUPro tools. I don't have access to the RTL.

Do you have any idea what the performance is for a 16-bit core?
 
> I would also recommend that in what ever benchmark you do, to have the
> memory (program/data/cache) as you will have it in your final
> application to get the most realistic results possible.

Sure.

Cheers,
JonB

Article: 66529
Subject: Re: Spartan 3 - avaliable in small quantities?
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Sat, 21 Feb 2004 09:31:41 -0500
Links: << >>  << T >>  << A >>
On Fri, 20 Feb 2004 19:44:40 +0100, Thomas Heller wrote:

> I have read several posts here about the difficulties to get Spartan 3
> parts in small quantities.
> 
> Is it realistic to start a project using spartan 3 (actually the XC3S50
> in the VQ100 package is what I probably want to use) when I only need
> small quantities - starting with getting some 10 samples, in full
> production lets say 100 to 500 pieces per year?
> 
> Thanks for opinions,
> 
> Thomas

Spartan 3s are hard to get but they are available, I'm using XC3S400s in a
new design and we were able to get sample quantities. If you are just
starting the project put your sample order in now, the lead times are
long. My client waited until a week before the boards showed up and they
ended up having to buy the parts from a broker on the other side of the
world. I wouldn't worry about production quantities, Xilinx claims their
yields are good. The problem is that demand unexpectedly spiked so there
is a shortage this quarter.



Article: 66530
Subject: Re: Serial ATA with Xilinx RocketIO (Virtex 2 Pro)??
From: "Antti Lukats" <antti@case2000.com>
Date: Sat, 21 Feb 2004 06:41:02 -0800
Links: << >>  << T >>  << A >>

"Michael Sch÷berl" <MSchoeberl@ratnet.stw.uni-erlangen.de> wrote in message
news:c15m49$1dt7uc$1@ID-40811.news.uni-berlin.de...
> Hi ...
>
> Xilinx still claims in various documents that you could
> use RocketIOs for Serial ATA.
>
> Half a year ago there was the same question - the
> problem seems to be with the "Out-of-Bound" (OOB)
> message creation and detection ...
>
> has anyone found a solution yet?

as much as I got informatiom from Xilinx then, well ML300 board has SATA
connectors but they are unuseabel as SATA :(
so, NO there is no OOB support and SATA with RocketIO in V2Pro.

antti
www.openchip.org



Article: 66531
Subject: Re: Dual-stack (Forth) processors
From: hugo2h@aol.com (Hugo2H)
Date: 21 Feb 2004 15:03:58 GMT
Links: << >>  << T >>  << A >>
>ology.com  (Jeff Fox)
>Date: 2/18/04 11:45 PM Pacific Standard Time
>Message-id: <4fbeeb5a.0402182345.3a2f3fa0@posting.google.com>

>I spent a lot more years
>working with P21, I21 and F21 and have a much better memory of
>the bit level details there, it was also more recent.
>

Is  any chance, or possibility  to have HDL or VHDL  for  F21  or I21 or P21. 
that  would  make real  portablebility  of  those  processors  Silicon 
Foundrywise.  This because  If  you have  over  100k volume  product design
with  F21 to design on single source,  F21 may be idal low cost wise, but 
depent on  one foundry, seems  lilltle bit  risky on now a day way of life.  
But  if FPGA  chosed for  foundry portability at cost more than  F21 style
pruduct.  as long you have  vertical  room  on a board you may make it by
piggybag  for different  FPGA  family for 2nd source, if  plan  a head at borad
design time.     

    Since  F21 or I21  samall counts in  gates  wise,  HDL  or VHDL  may  be
not  huges  codewise as  other  processor  compare  to  8051,  (  was  there a
HDL or  VHDL  for  8051  mention  on this  FPGA or  on the sister  newsgroup 
CAD newsgroup ? )    Hope  this  give you some  incentive  to have  HDL  or
VHDL  for  I21 or  F21.  Is  any  Angles  may help  you  out on that  in  U.S.
Sicon  Valley, or you have to go  off shore for the  angles ? 

   Also  is  there  a  chance  of  HDL or VHDL  in  Forth,   Since  HDL or VHDL
 so  wordy and long,   so Forth  may reduce those  WORDY world  to less
volumewise for  easy  debug  on those big  processors,
This  is a big  SW  project..

Article: 66532
Subject: FPGA info from Embedded World 2004/Nuerrnberg
From: "Antti Lukats" <antti@case2000.com>
Date: Sat, 21 Feb 2004 07:06:04 -0800
Links: << >>  << T >>  << A >>
Embedded World 2004. Nuernberg, Review:

First impression, FPGA vendors had very little presence there.
Altera Xilinx, Triscend, Lattice where there, but in really small booths.

Altera: the Quartus Suite CD was available for immediate pick-up, this CD
should containt all the tools to work with NIOS evaluation version (Altera
webdownloads do not include NIOS eval ASFAIK at the moment). Quartus 4 web
edition is due soon.

Xilinx: booth was so boring for me that didnt spend any time at all there.
Tried to get Spartan 3 info, only answer was that Xilinx shipped S3 samples
to disties last week.

Triscend, they had some new (for me) A7 family demos, thats a FPGA with MAC,
USB, A/D converters.

MIND had ML300 board to show, so I was able to demonstrate MicroBlaze
booting uClinux from CompactFlash at least for one person :), Mind seems to
be a little disappointed with the regard to the use of Linux on Virtex2Pro,
as Xilinx is only pushing Montavista and seems to ignore all the other
players.

Atmel: new FPGA configuration memories (new for me, maybe all others know
them), also MMC cards with Dataflash serial memories, so ideal bootstrap
media for FPGAs. Atmel has some ideas of having new MCU+FPGA style of
products, but nothing known what they will be. I repeated my plea to have:

* RISC + self programmable flash
* small FPGA (mcu reprogrammable)
* all packages from SO-8 to TQFP-100
lets see if the make this.
(I told Microchip that I like MCU in SO-8, and they did it, but forgetting
to pay royalties)

SSV had the demo of the NIOS -ucLinux module in DIP64 "package" it is
available only as development kit at $999 at the end of march.

Parallax had their Cyclone and Statix modules they do look qute not only on
pictures.

There was a company advertizing USB OTG IP Core, and they had a PHYTEC
compatible module with OTG support. And the guy at that boot was 100% that
the board has Xilinx FPGA and USB OTG PHY on the board. When I told it is
impossible, we looked at the board and found ISP1362, so there was no USB
PHY - as there is none shipping yet (except ISP1301 that is not obtainable).

USB OTG: tried to hard to squeeze the info from Philips - result: ISP1504
samples should be available from end of march. (all other info is under NDA
or Adopters agreement only). Motorola also had a OTG demo but that was also
using ISP1362. Motorola did promise MUCs with OTG.

Protel: the NEXUS was there, but CD was not available, I had to enter my
info and was promised that they send the CD. The Nexus evaluation version
should be fully working (30 days) except the functions that work with
hardware. Those it should be possible to evaluate the IP cores and see how
the SOC builder works etc...


maybe there was more FPGA "news" but I did not have so much time, as I was
primarily looking for a job, as my work contract ends on 31.03.2004

antti
www.openchip.org









Article: 66533
Subject: Re: Random logic verilog gate netlist generator
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Sat, 21 Feb 2004 11:06:57 -0500
Links: << >>  << T >>  << A >>
On Fri, 13 Feb 2004 19:53:32 -0800, Simon S.  IBM wrote:

> We have a need to create hundreds of non proprietary digital test structures, 
> each which would fit a pre-determined pinouts for a pre-determined 
> block size & a pre-determined block shape (e.g., rectilinear).
> 
> Can you provide a pointer to a good random logic verilog gate netlist generator?
> 
> I'd expect to feed it technology & macro LEF; the input & output
> pins; and either a gate count, or a block area (most likely a gate count). 
> 
> After running this random-logic verilog-gate generator, we would
> then place & route the results. The easy part is the place & route.
> The hard part is to come up with hundreds of non-proprietary
> sets of random (well mixed) gates to fill the blocks up with.
> 
> Any pointers would be appreciated.
> Simon

Try HDLmaker

http://www.polybus.com/hdlmaker/users_guide/

HDLmaker has a C like language that will allow you to generate this sort
of thing. Also HDLmaker can generate Xilinx floorplanning statements. 

BTW It looks like you are looking for Xilinx FPGA test patterns. I have an
extensible set of Xilinx FPGA test patterns that I offer as a product. 

http://www.polybus.com/xilinx_test_patterns/



Article: 66534
Subject: Re: Lead Free Packages
From: "John Adair" <newsreply@loseinspace.co.uk>
Date: Sat, 21 Feb 2004 17:01:42 -0000
Links: << >>  << T >>  << A >>
Have a look here
http://www.xilinx.com/system_resources/lead_free/pb-free_custpres.pdf . This
is public domain, I know more but I might have to shoot you if I told.
Somebody from Xilinx may wish to elaborate the detail. Also push your disti
a bit harder for detail, I would talk to a FAE rather than a sales person.
Often a sales person only knows what is on their database. and if a part has
not been ordered before then it might not be on the database, a catch 42
situation if ever there was one. The FAE may also be able to give you more
detail under a NDA.

John Adair
Enterpoint Ltd.

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.


"Kolja Sulimma" <news@sulimma.de> wrote in message
news:b890a7a.0402210145.2c246b88@posting.google.com...
> Were do I need to turn to purchase lead free Xilinx parts?
> Insight in Germany tells me that there are no
> XC2Sxx-PQG208 parts and no
> XC3Sxx-FTG256 parts listed.
>
> The problem is the following:
>
http://europa.eu.int/eur-lex/pri/en/oj/dat/2003/l_037/l_03720030213en00190023.pdf
>
> In the EU no electronic equipment containing lead may be sold by july
> 2006.
> My most important product has very low volume and therefore a single
> charge of products is in stock for more than a year. With manufacturer
> lead times of 16 week (take from a recent distributor quote) I will
> need to start ordering lead free parts this summer.
> It makes me a little nervous that the distri never heard about the
> Xilinx -G packages.
> It doesn't help, that the lead free parts are not listed in the
> datasheets.
>
> What are your experience?
> Did anybody order lead free Xilinx FPGAs yet?
> What about other manufacturers?
>
> Kolja Sulimma
>
> BTW:
> Networking equipment is excempt from the directive so that there will
> still be millions of leaded FPGAs be sold in europe.



Article: 66535
Subject: Re: Can FPGA bootstrap itself?
From: "Manfred Kraus" <makra7960@tiscali.de>
Date: Sat, 21 Feb 2004 18:38:40 +0100
Links: << >>  << T >>  << A >>
Here you can download the schematics of a FPGA board that is bootloaded
using USB.
http://www.cesys.com/english/ebene3/usb2fpga.htm
Just klick on the link named  "Schaltplan"
-Manfred Kraus

"Marius Vollmer" <mvo@zagadka.de> wrote in message
news:87ad3hp6w2.fsf@zagadka.ping.de...
> Imagine you want to have an FPGA board that has a USB port and no
> other connection (i.e., no other way to upload a bitstream).  Can that
> FPGA bootstrap itself over the USB port?
>
> There would be a 'boot' bitstream in some flash on the board and the
> FPGA would be configured initially with that bitstream.  The function
> of that bitstream would be to make the FPGA listen on the USB port for
> another bitstream that is then used to configure the FPGA for its real
> function.
>
> Can this be done?  Without external memory (other than the boot
> flash)?
>
> Just curious...
>
> -- 
> GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3  331E FAF8 226A D5D4 E405



Article: 66536
Subject: Re: Spartan 3 - avaliable in small quantities?
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 21 Feb 2004 14:30:56 -0500
Links: << >>  << T >>  << A >>
Hal Murray wrote:
> 
> >Is it realistic to start a project using spartan 3 (actually the XC3S50
> >in the VQ100 package is what I probably want to use) when I only need
> >small quantities - starting with getting some 10 samples, in full
> >production lets say 100 to 500 pieces per year?
> 
> Where would you buy them?  What do they say?  Can you get
> samples now?
> 
> Are there any features on the Spartan 3 that you absolutely need?
> (Can you use some other chip?)
> 
> What are the costs of alternatives?  What are the costs of
> not being able to get the chips when you need them?
> 
> How long is it going to take you to do the design?  (When
> do you absolutely need the samples?)  Can you work on the
> design with two plans in mind and make the choice a month
> or two from now?
> 
> My rule of thumb is to not design in a chip unless I have parts
> in hand or a distributor has stock that I'm sure I can get.
> 
> If an interesting chip has some features that would make a
> project a lot better (or even possible), then you have to decide
> if you want to stick your neck out.  Do you like fighting with
> not-quite-debugged tools?  Do you have good contacts at the vendor?

I don't know that the Spartan 3 parts are a major step forward in
FPGAs.  From what I can see, the main difference is the elimination of
the huge startup currents on power up.  The marketing claim is that
these will be much cheaper parts because of the small die.  But so far,
I don't think anyone has seen the results of this.  

If you design in a Spartan 3 based on quoted pricing today, you are not
likely to see that price drop at any time through the life cycle of the
part.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 66537
Subject: Re: Dual-stack (Forth) processors
From: Bengt Larsson <bengtl4.net@telia.NOSPAMcom>
Date: Sat, 21 Feb 2004 19:57:48 +0000
Links: << >>  << T >>  << A >>
In comp.arch, "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote:

>Jon Harris wrote:
>
>> Ctrl-End.  I guess it's 2 key strokes, and you still have to click within
>> the message, though Tab will also move the focus from the tree view to the
>> preview pane.
>
>If focus is in the preview pane just "End" will get you to the bottom.
>
>Sorry for the off-topic nature of this. I scan-through and read hundreds of
>emails and newsgroup posts per day and just a few extra keystrokes can be a
>pain in the you-know-what.

Well, Outlook Express is crap as a newsreader. Most newsreaders have a
"single-read key" key that pages through a message, then skips to the
next unread one at the end. This is why you don't see users of other
newsreaders complain so much about skipping some text. Trimming the
quotes is a good thing, nevertheless.

Outlook Express is crap as a newsreader. I could go on and on about
it, but I bet you didn't know. 

Article: 66538
Subject: Re: Can FPGA bootstrap itself?
From: Marius Vollmer <mvo@zagadka.de>
Date: Sat, 21 Feb 2004 22:55:49 +0100
Links: << >>  << T >>  << A >>
"Manfred Kraus" <makra7960@tiscali.de> writes:

> Here you can download the schematics of a FPGA board that is bootloaded
> using USB.
> http://www.cesys.com/english/ebene3/usb2fpga.htm
> Just klick on the link named  "Schaltplan"

Thanks, but this is not exactly what I had in mind.  Of course you can
connect a microcontroller to the USB port and then connect the FPGA to
the microcontroller (and the one you used seems pretty cool in that it
can give the whole USB Hi-Speed bandwidth to the FPGA).

The solution with the FTDI bit-bang chip is cool in that you don't
need _any_ bootstrap code on the board.


But can you do it without any external 'intelligent' parts,
theoretically?  (Independent of whether or not that would be
practical)?  I'm mostly interested in his out of curiosity.

All 'intelligence' should be in the FPGA: You want a microcontroller?
Put one in the FPGA.  You want USB?  Put the controller in the FPGA.
You want a different controller, more USB endpoints, larger buffers?
Reconfigure the FPGA.

When my FPGA is large and fast enough, I shouldn't need any external
logic (theroretically).  Just adapt the USB (or Ethernet) wires
electrically for the FPGA IOs and you should be ready to go.

Except when you want to configure the FPGA over a path that is
implemented in the FPGA itself.

One way to do this would be to have two bitstreams and the FPGA can
configure itself from any of the two and it can also overwrite them.
One bitstream could be the boot configuration that would just be able
to write the second bitstream from data received on the external port.
Then reboot with the second bitstream.

This seems clumsy, especially during development.  Is there a way to
reboot with a second bitstream without having to write it to a
external flash memory?  Can you 'boot' from an internal block RAM, for
example?


I don't really _need_ the answer, of course, but I know too little
about how FPGAs configure themselves to be able to answer this myself.
I'll lookup the ICAPs that Adam mentioned...

-- 
GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3  331E FAF8 226A D5D4 E405

Article: 66539
Subject: Re: Dual-stack (Forth) processors
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Sat, 21 Feb 2004 22:49:43 GMT
Links: << >>  << T >>  << A >>
Bengt Larsson wrote:

> Outlook Express is crap as a newsreader. I could go on and on about
> it, but I bet you didn't know.

What's a good newsreader?



-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 66540
Subject: Re: Can FPGA bootstrap itself?
From: hmurray@suespammers.org (Hal Murray)
Date: Sat, 21 Feb 2004 22:56:07 -0000
Links: << >>  << T >>  << A >>
>This seems clumsy, especially during development.  Is there a way to
>reboot with a second bitstream without having to write it to a
>external flash memory?  Can you 'boot' from an internal block RAM, for
>example?

The internal RAMs are not big enough to configure the whole chip.
That's easy to see if you think of using the RAMs as ROMs which
need to get initialized and that would take the whole RAM.

You might be able to do some interesting partial reconfiguration
work that way.  The internal RAMs are still pretty small.  You
could (maybe) use them several times.  But if you could do that
you could probably do the partial reconfiguration directly.


>I don't really _need_ the answer, of course, but I know too little
>about how FPGAs configure themselves to be able to answer this myself.
>I'll lookup the ICAPs that Adam mentioned...

Probably best to go read the configuration section in the data sheet.
Don't be surprised if you have to read it a few times.  It's simple
after you get it.


I think any sort of dual boot scheme is going to require some external
hardware.  Are you interseted in minimizing cost, board space, or
inelegance?

Various one chip micros are now available in tiny packages.  That would
be my starting point. The FTDI chips look good.  I think PIC has some
chips with USB interfaces.  (I haven't used them, but they use one
in their demo board to program other PICs.)

You can probably reduce the external logic to a single PAL or
a few gates/FFs if you are trying to reduce cost.  The best approach
I can think of would be to use two serial ROMs and a mux to select
which one.  The power on reset would reset the mux select FF.  The
FPGA could set it.

I say "serial ROMs" to explain the idea.  That's probably expensive.
With a smart enough PAL, you could replace the expensive serial ROMs
with a less expensive Flash chip.  (maybe using a high address bit
as the mux select)

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 66541
Subject: Re: GZIP algorithm in FPGA
From: user@domain.invalid
Date: Sat, 21 Feb 2004 23:08:18 GMT
Links: << >>  << T >>  << A >>
Florian-Wolfgang Stock wrote:
>>Isn't there a variation that generates the table on the fly?  I don't
>>know any details, but wouldn't they have this same problem in modem
>>compression, you can only see the data once?  Or do they buffer up a
>>block before compressing?  Back in the early days, an engineer talked to
>>me about the possibility of patenting a method that worked like this.  
> 
> 
> That isnt possible. At least not with Normal Huffman Coding. With the
> ZIP Alogrithm it is possible to build a dictonary on the fly, so you
> need only one pass. 
> The Huffman coding bases on the fact that it replaces often appearing
> characters with short bitstrings, seldom ones with long bitstrings. To
> know which character is often/seldom you need to count it.

I've never played with this problem before but I fail to see why you 
couldn't do it adaptively - at the cost of more memory of course.  Just 
maintain a heap of occurence count of codes up until this point.  To 
emit a word search for it the heap (hashing would do) and it's position 
in the heap directly translates into it's Huffman code. Then update it's 
count which could cause the code to move up in the heap and thus update 
a bunch of word -> code mappings.

To decode you'd do almost exactly the same, except you're looking up 
Huffman codes in the heap and translating them to words. (Of course I 
assume that previously unseen words are emitted escaped in some way, eg. 
prefixed with a reserved code.)

Improvements include starting with a good default dictionary and 
heuristics for resetting the dictionary when attained compression is too 
low.

Is anything wrong with this obvious approach?

/Tommy


Article: 66542
Subject: Re: Dual-stack (Forth) processors
From: Bengt Larsson <bengtl4.net@telia.NOSPAMcom>
Date: Sun, 22 Feb 2004 00:32:00 +0000
Links: << >>  << T >>  << A >>
In comp.arch, "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote:

>Bengt Larsson wrote:
>
>> Outlook Express is crap as a newsreader. I could go on and on about
>> it, but I bet you didn't know.
>
>What's a good newsreader?

That's a good question. Outlook Express has a pretty good interface,
but it isn't very good for scanning newsgroups quickly.

You may try the reader I use - Agent - you can find it at
www.forteinc.com. It's payware, but there is a 30 day free trial. 

Unfortunately, Agent is a kind of opposite to Outlook Express, not
easy to learn, hard to get into. It's also limited in some ways. But
it does the "core newsreading" extremely efficiently.

I have tried almost all newsreaders available for Windows, and a
number of them for Unix. I haven't found the be-all and end-all. 

If you want more information, you may want to check the newsgroup
news.software.readers.


Article: 66543
Subject: Re: Dual-stack (Forth) processors
From: fox@ultratechnology.com (Jeff Fox)
Date: 21 Feb 2004 17:58:53 -0800
Links: << >>  << T >>  << A >>
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<TTdZb.27845$9j2.1957@newssvr25.news.prodigy.com>...
> Davka wrote:
> 
> > Is there a community that is actively involved in discussing and/or
> > developing FPGA-based Forth chips, or more generally, stack
> > machines?

Davka asked about FPGA-based Forth chips.  He has a right to have
an interest and ask a question, but he probably also expected some
of the usual flame bait in response.

> I've thought about this in terms of internal use.  As much as I like FORTH
> (used it extensively in the 80's and early 90's) the reality seems to be
> that C is the way to go.

The subject of the question was about FPGA-based Forth chips.
The reason from the question is that they are a good fit to FPGA
as they can provide higher performance with fewer gates than
many other designs, especially when used as the control processor
to interface to other user defined custom circuitry in an FPGA
application.

Given that Davka obviously knows this already and is interested in
using some language on an application that may include a dual-stack
(Forth) processor in an FPGA he really didn't ask if he should just
give up the idea because it is not what everyone else is doing.

Given the context it seems strange to suggest that 'the reality
seems to be that C is the way to go.'  That sounds rather strange
since he asked about a particular type of FPGA-based dual-stack
(Forth) chip.  Are you suggesting that C would be a better choice
for the software for this type of chip than Forth?  What C
compiler will produce better code for a Forth chip than Forth?
I realize that you were probably just trying to flame Davka and 
trying to change the subject from asking about where people can
discuss the subject of dual-stack (Forth) processors and make
it clear that you don't like that subject broached in any of
the above newsgroups.  But after all, it wasn't cross posted
to c.advocacy etc.
 
If you stick to the technical details that Davka was interested
in you find lots of examples of very small dual-stack processors
implmented in programmable gate array that had very high performance.
In 1988 it was 50 mips on a 32-bit processor in PGA when Intel was 
selling full custom VLSI 80286 that got substantially less.  And
today's FPGA are pretty cheap, fast, and/or big compared to what
was available sixteen years ago.

> It's a matter of the business equation more than a technical
> rationalization.  

What do you know about Davka's business plans regarding his
use of dual-stack processors in FPGA?  I suspect that you know
nothing about it and were just trying to change the subject to
popularity. I think he asked because he was interested in technical
details on the subject, not in lectures about your idea of 
business equations or popularity comparisons.

> FORTH is very cryptic for non-FORTH programmers and
 
Duh. (insert programming language name) is very cryptic for non-
(insert same programming language name) programmers.  C is very cryptic
for non-C programmers.  The average person is not a programmer and
can't read C programs.  Should we conclude that because that is
what the majority of people think of C that everyone who uses C
should stop using a language that is cryptic to people who haven't
learned it?  Duh.

(APL is so cryptic looking to non-APL programmers that it 
looks like it came from outer space! Take over the world? ;-)

> finding skilled FORTH programmers is not as easy as C programmers.  

Duh.  Finding skilled (insert language name) programmers is not
as easy as (insert other language name) programmers.  The keyword
there is skilled.  Sure, not all programmers in a given language
are really the ones who are labeled skilled. The qualifier makes
the statement language independent.  

It is easier to find C programmers than programmers of languages
used by smaller numbers of people. Duh.  But after all this thread
was about Davka's interest in finding people who could rationally
discuss the design and use dual-stack processors implemented in FPGA.  
I don't think that this group of people is going to be larger than 
the group that includes skilled and unskilled C programmers. It
really has nothing to do with what he asked about.

> And,
> while productivity with FORTH can be substantially greater than with C or
> Assembly,

It is interesting that you think Forth can be substantially more
productive than C or assembly.  Not everyone would agree with you,
but in the context of the software that Davka will use with a
dual-stack processor in FPGA it certainly seems like a quite
reasonable statement.  Maybe you were just baiting.

> you are, eventually, forced to contend with code maintenance,
> reuse and changes in design teams (Oh, no! Our only FORTH guy left!).

Davka may be only guy involved in his work, he may have a team of
people, and after all he only asked were to find people who
knew about the subject.  He didn't ask if Forth was more popular
than C in systems written in C or with programmers who prefer C.

Maintenance is generally more of an issue of code quality than
anything else.  There are plenty of unskilled programmers who
have written, and will continue to write, code that is hard
to maintain because it was baddly written in the first place.
That certainly includes C and Cobol and assembler and Forth
or whatever.  As you say not all programmers are skilled
programmers.

Well written Forth programs are as easy to maintain as any other
well written programs.  Some consultants who use Forth complain
that they have to keep it a secret because if they tell the
client that their well written program was written in Forth they
won't be called in to do the maintenance, even the non-technical
vice-president can read and modify their code if they know it
is written in something as easy as Forth.  In the cases where
development 'productivity with Forth can be substantially greater
than with C or Assembly' any maintenance productivity comparison
would hopefully be similar.  Of course there are always examples
of bad and unmaintainable code being written in any language.
Often unskilled programmers point to their own code as examples
of code that they wrote but other people had difficulty understanding
or maintaining.  That is really a skill issue, or a managment issue
more than a language issue.

Best Wishes,
Jeff Fox

Article: 66544
Subject: Re: GZIP algorithm in FPGA
From: Sander Vesik <sander@haldjas.folklore.ee>
Date: Sun, 22 Feb 2004 02:13:10 +0000 (UTC)
Links: << >>  << T >>  << A >>
user@domain.invalid wrote:
> 
> I've never played with this problem before but I fail to see why you 
> couldn't do it adaptively - at the cost of more memory of course.  Just 
> maintain a heap of occurence count of codes up until this point.  To 
> emit a word search for it the heap (hashing would do) and it's position 
> in the heap directly translates into it's Huffman code. Then update it's 
> count which could cause the code to move up in the heap and thus update 
> a bunch of word -> code mappings.

Adaptive huffman codes have been around since at least the early 1980s.

> 
> To decode you'd do almost exactly the same, except you're looking up 
> Huffman codes in the heap and translating them to words. (Of course I 
> assume that previously unseen words are emitted escaped in some way, eg. 
> prefixed with a reserved code.)
> 
> Improvements include starting with a good default dictionary and 
> heuristics for resetting the dictionary when attained compression is too 
> low.
> 
> Is anything wrong with this obvious approach?

You may want to read the following:

	igm.univmlv.fr/~mac/DOC/C10.ps
	http://www.cs.duke.edu/~jsv/Papers/Vit87.jacm.ps.gz

If you are interested in (adaptive) huffman codes 

> 
> /Tommy
> 

-- 
	Sander

+++ Out of cheese error +++

Article: 66545
Subject: Re: Dual-stack (Forth) processors
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Sun, 22 Feb 2004 02:42:28 GMT
Links: << >>  << T >>  << A >>
Jeff Fox wrote:

> Davka asked about FPGA-based Forth chips.  He has a right to have
> an interest and ask a question, but he probably also expected some
> of the usual flame bait in response.
<SNIP>

Jeff,

Very good post.  Please rest assured that my posts were made with the best
of intentions and "flame baiting" isn't even close to anything in my life.
I don't know which of the newsgroups you have read this from.  I'm a
frequent participant in comp.arch.fpga and folks in that NG can tell you
that I'm not some kid getting off by starting controversy.  Hell, I'm not
even a kid!

Anyhow.  Maybe I got off topic with my detour into the business issues
involved.  I'm sorry for that.  I simply wanted to point out that there are
issues --business issues-- with regards to using Forth (or APL, or whatever)
in your work.  Of course, nothing anyone says in these NG's is universally
applicable.  It is left to the reader to decide whether or not to attach
validity and/or waste any time pondering what was said.

My own perspective is that, while I would love to use Forth for my work, I
have not found that the effort required jusifies the excercise.  You can
almost say the same thing about assembler.  You can't make such statements
without explaining why.  My reasoning has to do with non-technical issues.
With the realities of business.

Regarding using C with an FPGA.  Implementing something as simple as an 8051
core opens the door to using a large number of C compilers, tools, libraries
and capable programmers to write your control code.

If efficiency or execution speed (in the context of an FPGA) is paramount,
maybe a custom state-machine solution makes more sense.  All of these
options have advantages and disadvantages, of course.



-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 66546
Subject: Re: Can FPGA bootstrap itself?
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Sun, 22 Feb 2004 02:55:23 GMT
Links: << >>  << T >>  << A >>
Marius Vollmer wrote:

> I know too little
> about how FPGAs configure themselves

Maybe that's the key here.  FPGA's don't "configure themselves".  They are
either force-fed by a PROM/microprocessor/FLASH/whatever (in "slave" mode)
or issue a signal saying "feed me" after which an external
PROM/microprocessor/FLASH/whatever, well, feeds the bitstream in.

What you have is a chicken and egg situation.  The only code-less mechanism
(which seems to be what you want) is to, well, have a prom with code on the
board.  Actually, that's not true.  A $6 USB chip (the FTDI device) can sit
there and run an otherwise blank board from code on a PC.  That's how you
break the chicken/egg loop.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 66547
Subject: Re: GZIP algorithm in FPGA
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 22 Feb 2004 01:37:35 -0500
Links: << >>  << T >>  << A >>
user@domain.invalid wrote:
> 
> Florian-Wolfgang Stock wrote:
> >>Isn't there a variation that generates the table on the fly?  I don't
> >>know any details, but wouldn't they have this same problem in modem
> >>compression, you can only see the data once?  Or do they buffer up a
> >>block before compressing?  Back in the early days, an engineer talked to
> >>me about the possibility of patenting a method that worked like this.
> >
> >
> > That isnt possible. At least not with Normal Huffman Coding. With the
> > ZIP Alogrithm it is possible to build a dictonary on the fly, so you
> > need only one pass.
> > The Huffman coding bases on the fact that it replaces often appearing
> > characters with short bitstrings, seldom ones with long bitstrings. To
> > know which character is often/seldom you need to count it.
> 
> I've never played with this problem before but I fail to see why you
> couldn't do it adaptively - at the cost of more memory of course.  Just
> maintain a heap of occurence count of codes up until this point.  To
> emit a word search for it the heap (hashing would do) and it's position
> in the heap directly translates into it's Huffman code. Then update it's
> count which could cause the code to move up in the heap and thus update
> a bunch of word -> code mappings.
> 
> To decode you'd do almost exactly the same, except you're looking up
> Huffman codes in the heap and translating them to words. (Of course I
> assume that previously unseen words are emitted escaped in some way, eg.
> prefixed with a reserved code.)
> 
> Improvements include starting with a good default dictionary and
> heuristics for resetting the dictionary when attained compression is too
> low.
> 
> Is anything wrong with this obvious approach?

Maybe.  If I understand what you are saying, initially a sequence will
be sent unencoded until enough information is saved up to assign codes
to various strings that occur.  But the xmitting end sees the raw stream
while the rxing end sees the encoded end.  How does the rxing end know
when the first code is sent and what it stands for?  Each time a new
code is sent, the rxing end needs to know what is happening.  Or does
the decision to send a code instead of the data depend only on the
history and not on the present data?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 66548
Subject: Re: GZIP algorithm in FPGA
From: hmurray@suespammers.org (Hal Murray)
Date: Sun, 22 Feb 2004 06:59:21 -0000
Links: << >>  << T >>  << A >>
>Maybe.  If I understand what you are saying, initially a sequence will
>be sent unencoded until enough information is saved up to assign codes
>to various strings that occur.  But the xmitting end sees the raw stream
>while the rxing end sees the encoded end.  How does the rxing end know
>when the first code is sent and what it stands for?  Each time a new
>code is sent, the rxing end needs to know what is happening.  Or does
>the decision to send a code instead of the data depend only on the
>history and not on the present data?  

Some compression schemes have a way to indicate that the next N bytes
are raw data, don't look in the dictionary.

You can also use the data stream (the part you have sent already)
as a dictionary, encoding things like copy X bytes starting -Y bytes
back from here.

In general, most good compression techniques are a tradeoff on memory
CPU/cache usage, and compression efficiency.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 66549
Subject: Comparator and minimum value address
From: sunil_iitg_dsp@yahoo.co.in (sunil)
Date: 22 Feb 2004 05:10:09 -0800
Links: << >>  << T >>  << A >>
Hi all,
       I have 16 values. I ahve to compare those values and i have to
get minimum value and it's address. I am comparing those all 16 avlues
with by 8 comaprators, next the 8 output values by 4 comparator and so
on......
    at last i am getting minimum value but how i can get address of
that value. I tried by moving back which means if output deciison is 0
,then previous decision's 0 bit.... and so on..
 but VHDL program is giving error.
     
whether any other choice is there, please help me.
                    -sunil



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