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Leon Heller <aqzf13@dsl.pipex.com> wrote in message news:<40220c16$0$21303$cc9e4d1f@news.dial.pipex.com>... > Yuri Tregubov wrote: > > > Dear friends, > > > > Could your check and then post your BIOS LPT port settings for me ? > > I just dug out my home-made ByteBlaster clone and an old Flex10K10 board > of mine and checked that they still worked with MaxPlus 10.2. > Configuration with a simple test function worked OK. I'm using WinME > with the port configured for EPP operation. Further to the above, I'm actually using an ISA EPP parallel port card for the ByteBlaster. The motherboard parallel port is connected to my printer. I use the EPP port for other devices like Xilinx and ARM JTAG interfaces.Article: 65726
Hello, Anyone knows any site or online book about Introduction to the FPGA architecture ? Regards, AhmedArticle: 65727
I am doing my thesis in artificial intelligence, and wish to create a "proof of concept". It has been a long time since I have been working with FPGAs directly and wish to know the following: 1 - What software and hardware tools are available that operate well under Windows (compilation, etc...)? 2 - Has anyone had any experience with programming AI's on FPGAa? Are there tools available for FPGA development? 3 - Are there any programmable logic devices out there that have a ADC built in? 4 - Are there any "tricks" that I would be able to use in order to generate uniform, gaussian or Cauchy noise with a minimal of external hardware? Thank you in advance, I have posed many questions for a single posting! John.Article: 65728
Hi,
I've been asked to develop software applications for a company who's
main product is silicon IP, implemented on ~40k logic cells on Altera
or Xilinx.
Their current development environment is the ARM Integrator, which,
for the applications I've been asked to develop, is *way* overkill
(and overpriced).
So, what platforms are available for such development? My ideal
platform would have the following:
1. FPGA with ~40k cells available for programming
2. ARM9 CPU
3. Linux BSP (VxWorks and WindowsCE nice-to-have)
4. Color LCD display (PDA-style)
Instead of (1) above, I'll also settle for an AMBA bus interface, so
that I can plug in a small daghterboard with our own FPGA.
TIA,
ronys@gmx.net
Article: 65729
JohhnyNorthener wrote:
> Any advice please.
>
> I am creating a parallel uP interface to my fpga and i have separate
> 'processes' for the read and write functions.
Unless you need to do both at once,
consider procedures in the same process.
> My question is : Will
> quartus synthesise separate address decoders - one for the read and
> one for the write,
Only if your code tells it to.
> or is it 'clever' enough to munge the two together
> in the same decoder when synthesising ? (not sure of the tech term but
> is this resource sharing ?)
> Any help will be much appreciated
Learn simulation.
-- Mike Treseler
Article: 65730
I've been looking for historical prices of FPGAs to try and get an
idea of what I might expect to get for a given price for small
quantities and came across this post:
http://tinyurl.com/36blb
which has a price table for small quantities (<=25) for January 2000:
Spartan
XCS05 3PC84C 10.00
XCS10 3PC84C 18.10
XCS20 3PQ208C 40.40
XCS30 3PQ208C 45.35
XCS40 3PQ208C 49.15
Virtex
XCV50 4PQ240C 55.40
XCV100 4PQ240C 104.00
XCV150 4PQ240C 128.00
XCV200 4PQ240C 157.00
XCV300 4PQ240C 244.00
XCV400 4HQ240C 344.00
XCV600 4HQ240C 581.00
XCV800 4HQ240C 860.00
I compared the above prices with the prices on these web pages, that I
assume are up to date because they stock up to date chips:
Spartan: http://www.plis.ru/price.html?ID=121
Virtex: http://www.plis.ru/price.html?ID=111
and all of the prices on the Russian website are exactly the same
price today as they were from a different supplier in January 2000.
Why are they exactly the same price?
Do Xilinx tell their resellers what to charge? And if so, isn't this
illegal?
Also, why is there such an enormous price difference per part between
massive quantities and smaller quantities? Xilinx make X million of
part Y, so why do they charge so many hundred percent higher prices
for small quantities than very large quantities?
As there is such a huge difference in prices between large and small
quantities, why isn't there a supplier that buys largish quantities to
sell in smaller quantities so that the supplier makes a profit and the
purchaser of small quantities gets chips cheaper?
Also, what does happen to FPGA prices over time? Do they just reach a
final value and they never get any cheaper? That would explain why
prices would be very similar in 2000 and 2004, but not why they're
identical. You can get a Spartan 2E XC2S150E-6PQ208C for $20.45 from
the above Russian website today. What might you expect to be able to
get for $20 in, say, 2 years' time?
--
Steve
Article: 65731
MM wrote:
> I think it is the core, however I can't say that for sure.
Synthesize the core all by itself, and see if that works.
Next time, get source code, or write your own.
> memory and puts into an onboard buffer. Then the core takes it from that
> memory, decodes and puts into the output buffer memory.
How is the data synchronized from buffer to core?
> Finally, data from
> the output buffer is DMA'ed into the host memory.
How is the output buffer synchronized to the cpu?
> What I see is that
> sometimes data in the board output buffer is slightly corrupted (usually in
> the LSB of one of a 1000 words). If I simply read my buffer in a loop, the
> data is always the same, it fails only when run through the decoder. It
> doesn't fail every time, it can go fine for over 100 cycles sometimes...
Smells like a synchronization problem.
-- Mike Treseler
Article: 65732Yes, just download the Complete Programming Tools from the Webpack page (you have to be registered) http://www.xilinx.com/webpack/index.htm /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca") "Thomas Kurth" <thomas.nospam@gmx.net> wrote in message news:MPG.1a8c3af2a0e70cd69896e9@127.0.0.1... > Heyho NG, > > is there a possibility to install the xilinx download tool as a stand > alone application for our production line? It is a little bit urgent, > because they just put in the XC18V01 without programming them before. So > they need a possibility to install just the download-tool. Can anyone > help? > > Thanks, > > Thomas > -- > > No matter if you are going on-piste or off-piste, just hit the slope and > stay healthy! > > For mail reply replace "nospam" with "kurth" and "net" with "de". > The above mentioned adress is valid, but ignored.Article: 65733
Steve, As for older parts, they do not get any less expensive to make. So the price drops until the yields are stable, and then stops dropping. Happens to everyone. At some point, they get more expensive to make as their quantities go down, and the fab line equipment gets more expensive to run (obsolete processes). That is why we send out notices for the end of life of a product (eventually). That is also why we then go to a new and less expensive technology as soon as we can! If we can make an FPGA for less, our business increases as the number of applications that can afford FPGAs increases. If the ASIC business had 20,000 ASIC starts in a 20 billion dollar market three years ago, and only 2000 starts least year, you can easily see where increased business for FPGAs comes from. The parts you mention here, in Peter's scale of FPGA 'life' of 15 years for every 1 year makes these parts very old (>90 years) and just plain old (75 years). Definitely parts that are in the "retired" phase (still playing golf actively, but not recommended for new designs). As for why things cost less in quantity, that is Econ 101 (for non majors). AustinArticle: 65734
I have found the example at: http://sise.ttu.ee/users/nalle/etf99/annotation.html The most interesting thing is that it is my university teacher's project.Article: 65735
valentin tihomirov wrote:
> I would like to accelerate a data conversion task. We just send a stream
> of data to converter that produses a response stream. Actually, this
> converter is an emulator of a system we are going to simulate efficiently
> accelerating simulation task. As the goal is a number of simulations per
> time unit, the high performance channels are needed to communicate between
> application running on PC and emulator running on FPGA.
Consider 100/1000 Ethernet.
-- Mike Treseler
Article: 65737"Mike Treseler" <tres@fluke.com> wrote in message news:402282CE.6050905@fluke.com... > MM wrote: > Synthesize the core all by itself, and see if that works. I can't really test it without the rest of the design. In simulation all seems fine. > Next time, get source code, or write your own. Not always our choice... Besides, it is truly a big and complex core... > > memory and puts into an onboard buffer. Then the core takes it from that > > memory, decodes and puts into the output buffer memory. > > How is the data synchronized from buffer to core? The core is designed to work with BRAM. It puts out read enable when it needs data. The clock is common for the core and the read side of the buffer. > > Finally, data from > > the output buffer is DMA'ed into the host memory. > > > How is the output buffer synchronized to the cpu? It sits on the PCI controller's local bus. A state machine in the FPGA programs a DMA channel in the PCI controller and it starts reading the buffer... > Smells like a synchronization problem. It sure does... /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca")Article: 65738
Miguel Silva wrote: > Virtex II and Virtex II Pro allow internal reconfiguration through the ICAP > module, the application note XAPP662 as an example that shows how this could be > done I remember a discussion on this newsgroup a while back touching ICAP and its performance. I believe it was triggered by the fact that ICAP would not be in the Spartan3 chips. You might want to check the archives... -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 65739
Greetings, this is my first posting to this group, but I've been following the discussions for some time. I have a small problem which I'm trying to solve: My design has a Virtex E, and I need to generate a 1MHz clock and a 4MHz clock from a single clock source. The are to be used internally and they need to be synchronized. My problem is that the CLKDLLE primitive needs a CLKIN of at least 25MHz. I can supply that, I have an external oscillator tunable from 0 (or very low at least) to 40MHz. But the CLKDLLE can divide by 16 at maximum, thus I cannot use it to create the 1MHz clock. Do I have any options? Are there any other techniques I may apply to perform division and get a minimal clock skew between the two clocks? What would happen if I tried to use a CLKIN of 16MHz? No DLL lock? Thank you, -Geir BotterliArticle: 65740
Let me answer some of your questions: The IC business is not so much different from other businesses. We ( i.e. any IC manufacturer, this is all not Xilinx-specific) sell largely through distributors, who are independent companies. We tell them a recommended retail price ( in the US auto stores this is called MSRP), but -just like the car salesman- they can sell it for any price they think is appropriate to optimize their profit. (Same as every grocery store does, too) Selling in large quantity is always cheaper than selling in small quantity. The world is full of examples. Somewhat unique to the IC business is the fast-paced innovation that allows us to make better and faster new chip designs at ever lower price per function. But that is due to smaller geometries, larger wafers, better defect density etc. Once a specific device has been in production a few years, there is little chance to lower its manufacturing cost, once the ramp-up problems are overcome, the yield has been stabilized and the testing effort has been optimized. The cost per quare inch of silicon is not going down. Cost reduction comes from smaller geometries and thus higher packing densities possible in the new designs. That's why you see no cost reductions for mature chips. Real old ones actually go up in price, as their manufacturing volume decreases. (You pay more for a 74161 today than we did 30 years ago). This is a very competitive business. Peter Alfke Steve wrote: > > I've been looking for historical prices of FPGAs to try and get an > idea of what I might expect to get for a given price for small > quantities and came across this post: > > http://tinyurl.com/36blb > > which has a price table for small quantities (<=25) for January 2000: > > Spartan > XCS05 3PC84C 10.00 > XCS10 3PC84C 18.10 > XCS20 3PQ208C 40.40 > XCS30 3PQ208C 45.35 > XCS40 3PQ208C 49.15 > > Virtex > XCV50 4PQ240C 55.40 > XCV100 4PQ240C 104.00 > XCV150 4PQ240C 128.00 > XCV200 4PQ240C 157.00 > XCV300 4PQ240C 244.00 > XCV400 4HQ240C 344.00 > XCV600 4HQ240C 581.00 > XCV800 4HQ240C 860.00 > > I compared the above prices with the prices on these web pages, that I > assume are up to date because they stock up to date chips: > > Spartan: http://www.plis.ru/price.html?ID=121 > Virtex: http://www.plis.ru/price.html?ID=111 > > and all of the prices on the Russian website are exactly the same > price today as they were from a different supplier in January 2000. > > Why are they exactly the same price? > > Do Xilinx tell their resellers what to charge? And if so, isn't this > illegal? > > Also, why is there such an enormous price difference per part between > massive quantities and smaller quantities? Xilinx make X million of > part Y, so why do they charge so many hundred percent higher prices > for small quantities than very large quantities? > > As there is such a huge difference in prices between large and small > quantities, why isn't there a supplier that buys largish quantities to > sell in smaller quantities so that the supplier makes a profit and the > purchaser of small quantities gets chips cheaper? > > Also, what does happen to FPGA prices over time? Do they just reach a > final value and they never get any cheaper? That would explain why > prices would be very similar in 2000 and 2004, but not why they're > identical. You can get a Spartan 2E XC2S150E-6PQ208C for $20.45 from > the above Russian website today. What might you expect to be able to > get for $20 in, say, 2 years' time? > > -- > SteveArticle: 65741
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<14XTb.20607$ws.2742532@news02.tsnz.net>... > > One thing that was not obvious in a quick trawl thru their info, > was the relative NIOS sizes (Stratix / Stratix II). > You'd think that would make a good benchmark, but maybe it's still a > 'work in progress' as they tune the SW. > > Anyone seen actual numbers or NIOS or NIOS II ? > > -jg Jim, Nios v3.2 is the final release of "classic" Nios. It is slated to be released very soon, and will offer a couple of tweaks for Stratix II support. For another data point: I ran the "minimal_32" example through QII 4.0 for both device families and got 2011LEs (Stratix) vs. 1393ALUTs (Stratix II). Again, Nios 3.2 will officially support Stratix II. As for Nios II... I cannot comment on that yet, but stay tuned, its worth waiting for. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 65742
Use a single clock for the FPGA. Use enables to clock the 4 MHz flops and/or the 1 MHz flops at every nth (or 4*n-th) edge. One simple clock. No DLL. All flops synchronous with no skew. Apply the multi-cycle constraint through the enables to get your timing at 4 MHz or 1 MHz. A thing of beauty. "Geir Botterli" <geirb@fokk.org> wrote in message news:308520dbkbv5fm4m3h0ap35n21rrgbqn8e@4ax.com... > Greetings, this is my first posting to this group, but I've been > following the discussions for some time. > > I have a small problem which I'm trying to solve: > > My design has a Virtex E, and I need to generate a 1MHz clock and a > 4MHz clock from a single clock source. The are to be used internally > and they need to be synchronized. My problem is that the CLKDLLE > primitive needs a CLKIN of at least 25MHz. I can supply that, I have > an external oscillator tunable from 0 (or very low at least) to 40MHz. > But the CLKDLLE can divide by 16 at maximum, thus I cannot use it to > create the 1MHz clock. > > Do I have any options? Are there any other techniques I may apply to > perform division and get a minimal clock skew between the two clocks? > > What would happen if I tried to use a CLKIN of 16MHz? No DLL lock? > > Thank you, > -Geir BotterliArticle: 65743
Do you need 500-700 pins at 10 Gb/s ? How about 622 Mb/s ? Do you need speed (heavily pipelined design) or low latency (less tolerable to register delays)? There are many ways to skin your cat. "Griva" <griva@poczta.onet.pl> wrote in message news:bvt5a3$i44$1@nemesis.news.tpi.pl... > Użytkownik "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> napisał w > wiadomości news:bvt49f$k8h$1@news.tu-darmstadt.de... > > Griva <griva@poczta.onet.pl> wrote: > > : Hi, > > > > : I'm looking for the fastest interface/standard between two FPGAs. > > : Have You got any suggestions? > > > > It depends on reuirements: > > - Uni/Bidirectional > > - Distance between chips > > - Number of connections allowed > > ... > > > > I think that nearly always it is best to get a bigger FPGA and put > > everything into one package. > > > > Bye > > -- > > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > Reqiurements: > - Uni/Bi - for me it doesn't matter, could be this and this > - Distance - about 3-5 cm > - Number - about 500 - 700 pins > > The biggest FPGA is too small, I have to use 2 or 3 FPGAs and I want to have > the fastest transfer between these chips. > > Best Regards, > Griva > >Article: 65744
> Dear Altera Corp, > > could you please also confirm is SOPC Builder that is bundled with Altera > Quartus II 3.0 Web Edition useable at all or not. > > so far all our attempts todo something with it have failed: > NIOS is supplied (white icon?), after requesting NIOS evaluation license and > installing it, nothing changes, the NIOS in SOPC is not enabled. > and if there is no Avalon master then the SOPC doesnt do anything at all. > SOPC list DF6811 as Avalon master, so obtained eval license for DF6811 (from > provider DCD) - unfortunatly there is some problem as per DCD on Altera side > so DF6811 is not enabled in SOPC, so no way. > No Processor enabled, no avalon master no system can be built :( > > I dont get it - if SOPC is included in free edition there should be > something that can be done with it ??? > > In previous versions of Altera free software I think the NIOS evaluation was > possible, unfortunatly I had very little time then and now this older > version probably would not recon the new license. > > Ok, the long story short - is there any way to evaluate NIOS without paying > up front ? > > Thanks > Antti Lukats > altera.openchip.org Hi Antti (and anyone else interested in the above question), A colleague of mine answered this on your openchip web forum: http://altera.openchip.org/forum/viewtopic.php?t=2#3&sid=070e4f3d938f67a4df77b9d249515feb PS: The "white dots" in SOPC Builder show components that are available elsewhere for download/CD, but not installed on your system. There is a CD coming out shortly with an eval version of Nios. It will be separate from the free Quartus download. Here is the link: https://www.altera.com/literature/adl/adl-swtools.jsp SOPC Builder is more of a design tool -- it did make its debut with Nios and remains the main tool in the HW portion of a Nios design, but there are many uses for it independent of Nios (for building interconnects between user logic, downloading SOPC Builder components from 3rd parties, using the Excalibur devices, etc.). This is why it is installed automatically with Quartus now. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 65745
Rather than using two clocks, clock the whole design with your 4 MHz clock
and then generate a clock enable every 4th clock and feed it to the
flip-flops that have the 1 MHz clocking requirement. If these are for
output clocks, you could use an 8 MHz clock, and a state machine to
generate the outputs at 1 MHz and 4 MHz.
Geir Botterli wrote:
> Greetings, this is my first posting to this group, but I've been
> following the discussions for some time.
>
> I have a small problem which I'm trying to solve:
>
> My design has a Virtex E, and I need to generate a 1MHz clock and a
> 4MHz clock from a single clock source. The are to be used internally
> and they need to be synchronized. My problem is that the CLKDLLE
> primitive needs a CLKIN of at least 25MHz. I can supply that, I have
> an external oscillator tunable from 0 (or very low at least) to 40MHz.
> But the CLKDLLE can divide by 16 at maximum, thus I cannot use it to
> create the 1MHz clock.
>
> Do I have any options? Are there any other techniques I may apply to
> perform division and get a minimal clock skew between the two clocks?
>
> What would happen if I tried to use a CLKIN of 16MHz? No DLL lock?
>
> Thank you,
> -Geir Botterli
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 65746There seems to be exactly one supplier of reasonably modern (Virtex II or Spartan II) chips who's prepared to give pricing, and it's plis.ru in Russia. Farnham only have chips so old they don't appear on the http://www.xilinx.com/products/tables/fpga.htm page. Are plis.ru good people to deal with? Or am I missing something obvious? arrow.com have transparent pricing for EP1C and EP1S chips from Altera, but don't have any parts with number XC2* TomArticle: 65747
Thomas Womack wrote: > There seems to be exactly one supplier of reasonably modern (Virtex II > or Spartan II) chips who's prepared to give pricing, and it's plis.ru > in Russia. Farnham only have chips so old they don't appear on the > http://www.xilinx.com/products/tables/fpga.htm page. > > Are plis.ru good people to deal with? Or am I missing something > obvious? arrow.com have transparent pricing for EP1C and EP1S chips > from Altera, but don't have any parts with number XC2* > > Tom for european supplier, try www.memec.com or www.avnet.com ! for online xilinx pricing try www.nuhorizons.com ! larry www.amontec.comArticle: 65748
Tobias M=F6glich wrote: > begin > if rising_edge(IOSTRB_DSP) then Consider synching everything to the uC clk. if rising_edge(clk) then =2E . . And use IOSTRB_DSP as an input. -- Mike TreselerArticle: 65749
Hi all, We add an online help for all the configuration interfaces of your Chameleon POD. Our Chameleon POD is becoming an universal Dongle Emulator ! Just check http://www.amontec.com/temp/laurent/index.html larry ------------ And now a word from our sponsor ------------------ For a quality usenet news server, try DNEWS, easy to install, fast, efficient and reliable. For home servers or carrier class installations with millions of users it will allow you to grow! ---- See http://netwinsite.com/sponsor/sponsor_dnews.htm ----
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