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Messages from 114025

Article: 114025
Subject: Re: SPI slave problem
From: mankin18@gmail.com
Date: 2 Jan 2007 23:27:11 -0800
Links: << >>  << T >>  << A >>
I have just succeed a little on the SPI between ATmega 128 and Xilinx
Spartan-3E.
The board now can displays my desired bit pattern.

___________________________________________________________________________________________________________________________________________

module test_spi(led,MOSI,SCK,SS,clk);

input  MOSI,SCK,SS;clk;

output  [7:0] led;

wire  MOSI,SCK,SS,clk;

reg  [3:0] num = 7;
reg  [7:0] temp = 0;
reg  [7:0] led = 0;

always @(posedge clk)	//clk ---> the clock of FPGA
	begin
	end

always @(posedge SCK)           //SCK ---> the input SCK from ATmega
	begin
		if (!SS)
			begin

				if (num < 8)
					begin
						if (!MOSI)
							begin
								temp = (temp << 1);

							end
						else
							begin
								temp = ((temp << 1)|8'b00000001);

							end

						if (num == 0)
							begin
								led = temp;
								num = 8;
							end
						else
							begin
							end
					end
				else
					begin
					end

				num = num - 1;
			end

		else
			begin
			num = 7;
			temp = 8'b0;
			led = temp;
			end
	end

endmodule


Article: 114026
Subject: Wishbone I2C Application
From: camel_1213@yahoo.com
Date: 2 Jan 2007 23:58:42 -0800
Links: << >>  << T >>  << A >>
Hi,

My name is Loo, I am fresh for FPGA and Wishbone. Currently, I am using
the Opencore I2C with Wishbone interface for my project. However, I am
facing some issue here. I hope someone there can help me.

I try to do the execise below:
Example 1
Write 1 byte of data to a slave.
Slave address = 0x51 (b"1010001")
Data to write = 0xAC
I2C Sequence:
1) generate start command
2) write slave address + write bit
3) receive acknowledge from slave
4) write data
5) receive acknowledge from slave
6) generate stop command
Commands:
1) write 0xA2 (address + write bit) to Transmit Register, set STA bit,
set WR bit.
-- wait for interrupt or TIP flag to negate --
2) read RxACK bit from Status Register, should be '0'.
write 0xAC to Transmit register, set STO bit, set WR bit.
-- wait for interrupt or TIP flag to negate --
3) read RxACK bit from Status Register, should be '0'

However, I cant get the correct waveform for SCL and SDA.
Can someone tell me, what would be the timing diagram like for Wishbone
input signal, which one I need to activated 1st and after that what
should do.
Pls help.


Article: 114027
Subject: Re: Surface mount ic's
From: David R Brooks <davebXXX@iinet.net.au>
Date: Wed, 03 Jan 2007 00:22:39 -0800
Links: << >>  << T >>  << A >>
PeteS wrote:
[snip]

> In addition to  what others have said, a really nice soldering station
> can set you back a bit, but if you're doing small SM resistors/caps
> etc., then *two* fine pitch irons will ease your pain a lot. Most of
> the high end stations have multiple irons from a single controller
> including tweezer irons for such things, but it's usually beyond the
> needs or price range for a hobbyist.
> 
There are also 2-pointed bits, which fit in a regular iron. These come 
with spacings to match standard SMT outlines: 1206, 0805, etc.

> If you're getting older (as I most certainly am), then a magnifier with
> light (at least) will be welcome boon - it would probably be welcome
> anyway :)
> 
Agreed there! More light & a magnifier make all the difference.

Article: 114028
Subject: Re: Xilinx ISE 8.2.3 - Re-Creating Projects
From: Daniel O'Connor <darius@dons.net.au>
Date: Wed, 03 Jan 2007 21:04:47 +1030
Links: << >>  << T >>  << A >>
marc_ely wrote:
> The project file corruptions seem to occur randomly and will do various
> things, such as remove all files from the project (and not let you add
> them back), or not let you edit coregen parts, or a host of other
> things.

Isn't it great?
I find the Xilinx simulator will hang too!

> Re-creating a project each time seems very laborious.  Does anyone have
> any shortcuts to do this?  Is there a TCL script that can be run?
> Archiving and Project Cleanup don't help.
>
> The project is a mix of VHDL, verilog and coregen parts (xaw and xco).
> 
> Why can't they just implement project files as text files and let you
> control them by hand?

You can use pjcli (which is a [gross] Tcl script) like so..
pjcli -f ./npl_cmdfile

cat ./npl_cmdfile
#
# Script file for pjcli to [re]create the .ise file
#
# $Id$
#

# Create the project
NewProject(project.ise)

# Set basic properties
SetProperty(Device Family, spartan3)
SetProperty(Device, xc3s400)
SetProperty(Package, fg456)
SetProperty(Speed Grade, -4)
SetProperty(Top-Level Module Type, HDL)

# Add the sources
AddSource(foo.v, Verilog Design File)
AddSource(foo.ucf, foo)
AddSource(bar.xco, Coregen Design File)

# Test bench sources
AddSource(foo_test.v, Verilog Design File)

# Seems to affect all files..?
SetProperty(Simulation Run Time, 5000 ns, foo_test_v, Simulate Post-Place & Route Model, 9, foo)

# Close the project to tidy up
CloseProject()

-- 
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
"The nice thing about standards is that there
are so many of them to choose from."
  -- Andrew Tanenbaum
GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C

Article: 114029
Subject: Re: Memory controller design
From: "jerzy.gbur@gmail.com" <jerzy.gbur@gmail.com>
Date: 3 Jan 2007 02:35:09 -0800
Links: << >>  << T >>  << A >>

Piotr Wyderski napisal(a):
> Jerzy Gbur wrote:
>
> > IMHO you should use at least BRAM for preparing data to/from SRAM's BUS.
>
> Yes, but this way the fast random access time will be lost and the
> whole system will behave like a DRAM-based system with a tiny
> cache. Another option is to clock the CPU at 83MHz to match
> the bus speed and add the HLD signal, like in the old good DMA
> controllers. It simplifies a lot of things, but the initial question
> "how to connect many slower participants to the bus?" remains
> open. In this design some of them can be easily attached, as
> 83/2 = 41,5 and 83/4 = 20,75, so my USB and Ethernet links
> could work synchronously with the bus, but many other sources
> (AC-97 codecs, display) cannot by synchronized this way.
>
> > BUS side should work at 83MHz, but inner side should work faster to
> > accomplish multiplexing data in adequate "slots".
>
> It depends what you call "inner side". The CPU is supposed to
> work at 2--3 times higher frequency than I said, to hide its
> internal simple pipeline and appear to be one cycle design.
> But its memory interface is bounded by the available bandwidth.
> There is a large data source/target domain that _must_ be clocked
> at 65MHz, but I can connect it via a BRAM to the CPU domain.

I mean "Inner" = into FPGA,

> > I don't know how you like to match Address BUS and Data BUS
>
> What do you mean by "bus matching"?

Address and adequate data must be transferred at same time, that was
what I mean.

If you don't want build cache, you may connect CPU to SRAM only, all
others signals transfer through CPU.

If you want we can meet personally and talk about it - we're living in
the same town :)

Best Regards,

Jerzy Gbur


Article: 114030
Subject: FPGA-CPU THROUG ETHERNET
From: "Pablo" <pbantunez@gmail.com>
Date: 3 Jan 2007 02:48:44 -0800
Links: << >>  << T >>  << A >>
Hi, I am trying to send messages from spartan 3e to pc via ethernet and
viceversa. I have included opb_ethernet in the bsp design but at least
I don't know how to continue it. Any suggestion?

Regard.


Article: 114031
Subject: OT. Re: Surface mount ic's
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 3 Jan 2007 11:15:41 -0000
Links: << >>  << T >>  << A >>
"Dave Pollum" <vze24h5m@verizon.net> wrote in message 
news:1167772034.704908.104330@i12g2000cwa.googlegroups.com...
> Symon wrote:
>>
>> p.s. On the subject of US vs. UK toasting techniques, IMO the problem in 
>> the
>> US is not the toaster machines, it's the post-toasting technology. The 
>> toast
>> just gets piled up on a plate. The US seems to be a veritable toast rack
>> desert, so the toast always ends up soggy. I guess that's why it's IHOP 
>> and
>> not IHOT! :-)
>
> I live in the US and use a toaster to toast bread.  The bread goes in
> vertically.  I don't know what restaurants use.  A toaster oven is a
> small counter top appliance.  I've never used a toaster oven to toast
> bread or cook anything - I use mine to relow SMD parts using solder
> paste ;)
> -Dave Pollum
>
Hi Dave,
During my times in America, I use a toaster oven to make toast. It works 
just fine. The toaster oven is a cool(hot?) multipurpose US invention, which 
is only just starting to catch on in the UK, IME. But I can't find any of 
these:-
http://images.google.com/images?hl=en&q=toast+rack
which greatly enhance the toast experience!
Cheers, Syms.
p.s. I don't believe the urban myths about the US and irony, so I know 
you'll appreciate being lectured about food by an Englishman! :-)
Anyway, we're not as bad as Finland. 
http://news.bbc.co.uk/1/hi/world/europe/4649007.stm 



Article: 114032
Subject: Re: FPGA-CPU THROUG ETHERNET
From: "Jon Beniston" <jon@beniston.com>
Date: 3 Jan 2007 03:18:32 -0800
Links: << >>  << T >>  << A >>

Pablo wrote:
> Hi, I am trying to send messages from spartan 3e to pc via ethernet and
> viceversa. I have included opb_ethernet in the bsp design but at least
> I don't know how to continue it. Any suggestion?

Read an app note that shows you how to do it.

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?iLanguageID=1&category=-1211185&sGlobalNavPick=&sSecondaryNavPick=

Cheers,
Jon


Article: 114033
Subject: Re: OT. Re: Surface mount ic's
From: "Guru" <ales.gorkic@email.si>
Date: 3 Jan 2007 03:30:05 -0800
Links: << >>  << T >>  << A >>
Hi,

I have an article about making a BGA owen from a low cost toast owen by
integrating home made uP temperature control. It was published in
"elektor" (http://www.elektor-electronics.co.uk/) magazine.
The article is named "SMD Reflow Soldering Oven" and available here:
http://www.elektor-electronics.co.uk/default.aspx?tabid=28&art=52955

Cheers,

Guru


Article: 114034
Subject: PPC cache errata
From: "Guru" <ales.gorkic@email.si>
Date: 3 Jan 2007 03:46:48 -0800
Links: << >>  << T >>  << A >>
Hi folks,

I wonder how do you fight (bypass) problems with a PPC405 (Xilinx
Virtex-4FX) caching problems - silicon errata available at
ftp://ftp.xilinx.com/pub/documentation/misc/ppc405f6v5_2_0.pdf.

I tried disabling cache, but performance drops significantly.

I also find this code snippet in GSRD2 design:

 val = mfspr(XREG_SPR_CCR0);
  val |= 0x50000000;
  XCache_WriteCCR0(val);

  XCache_EnableICache(0x80000000);
  XCache_EnableDCache(0x80000000);

Actually I need caching for some 10MB of DDR memory. How to specfy this
in XCache_EnableXCache() ?

Cheers,

Guru


Article: 114035
Subject: Re: ERROR:NgdBuild:604
From: "Guru" <ales.gorkic@email.si>
Date: 3 Jan 2007 04:02:29 -0800
Links: << >>  << T >>  << A >>
Venu,

you must include custom_bram.bbd (dir custom_bram/data) file to specify
all netlists:

Files
################################################################################
custom_bram.edn, XilinxCoreLib.blkmemdp_v6_3.edn


Use "," to separate multiple files specs.

Then copy netlist files to "dir custom_bram/netlist" dir.
That should do.

Cheers,

Guru


Venu wrote:
> Hi People ,
>
> I am using a custom BRAM , but it is not getting synthesised , it keeps
> giving the error that
>    ERROR:NgdBuild:604 - logical block
> 'my_transmitter_0/my_transmitter_0/dpram0'
>    with type 'custom_bram_0' could not be resolved. A pin name
> misspelling can
>    cause this, a missing edif or ngc file, or the misspelling of a type
> name.
>    Symbol 'custom_bram_0' is not supported in target 'virtex2p'.
>
> custom BRAM generated using ----> Xilinx Core Generator
> Xilinx ISE functional simulation  -----> completed successfully
> Xilinx EDK BFM simulation      -----> completed successfully
> Netlist                                   ------> completed successully
> Bit Stream Generation           --------> FAILURE
>
> There has been traffic on this groups regarding the problem that I am
> facing, but none of the solutions that have been proposed are working
> in my case.
>
> I have designed a OPB Master Slave Peripheral , in which I have used a
> Dual Port RAM generated by XilinxCoreGenerator. I name this core
> custom_bram.The following files are generated
> 1)custom_bram.asy     2)custom_bram.edn  3)custom_bram.sym
> 4)custom_bram.v
> 5)custom_bram.veo      6)custom_bram.vhd  7)custom_bram.vho
> 8)custom_bram.xco
> 9)custom_bram_flist.txt
>
> I copied custom_bram.vhd into my user directory and instantiated it as
> a component in the main module.
>
> Things that I have tried:
> 1) custom_bram uses an entity called XilinxCoreLib.blkmemdp_v6_3
> defined in the library XilinxCoreLib . I copied all the related files
> from the blkmemdp_v6_3 into the pcores/hdl/vhdl directory.
>
> 2) i copied the custom_bram.edn file generated into a directory called
> /pcores/netlist and in the my_transmitter_0.mpd file made an entry
> specifying that
> OPTIONS STYLE = MIX.
>
> 3) In the instantiation of the custom_bram i have tried
> my_transmitter_v1_00_0.custom_bram ( as suggested in one of the posts
> on this group)
>
> 4) I am using 4 block rams in this designs ... In of the documents that
> I read , it was stated that you cannot make multiple instantiations of
> the same module, so i made 4 copies of the custom_bram , renamed them
> and referred to each only once
>
> None of these have worked .... Any ideas ? :)
> 
> 
> Thanks 
> Venu


Article: 114036
Subject: Re: OT. Re: Surface mount ic's
From: homelab@hotmail.co.uk
Date: 3 Jan 2007 04:07:01 -0800
Links: << >>  << T >>  << A >>
Speaking of Elektor is anyone on this group doing their FPGA project
series? I think its currently at part 8 (January 2007 edition).

Richard

Guru wrote:

> Hi,
>
> I have an article about making a BGA owen from a low cost toast owen by
> integrating home made uP temperature control. It was published in
> "elektor" (http://www.elektor-electronics.co.uk/) magazine.
> The article is named "SMD Reflow Soldering Oven" and available here:
> http://www.elektor-electronics.co.uk/default.aspx?tabid=28&art=52955
> 
> Cheers,
> 
> Guru


Article: 114037
Subject: Re: PPC cache errata
From: "cpmetz@googlemail.com" <cpmetz@googlemail.com>
Date: 3 Jan 2007 06:03:50 -0800
Links: << >>  << T >>  << A >>
Hi,

currently I think they should have left the caches out. In my design
(something with MPMC, some local-link-DMA's and Gig-Ethernet),
everytime I activate the instruction caches I get Program-Exceptions
(jump to offset 0x700 in the vector table), sporadic resets and so on.
I suspect that in my case the I-side plb (also taken from the
mpmc-example) is too aggresive for the cache. Or whatever. Tried
everything mentioned in the erratas... Sometimes it gets better,
sometimes not... Played around with priorities in the MPMC...

To address your question: in the PowerPC Processor Reference Guide
there is a chapter about how to use the different cache registers. The
address space is clustered in 128MB-regions. Each bit while
enabling/disabling cache-stuff represents one of these regions. Bit 0
(like in your example) is the memory-space from 0x0 to 0x7ffffff.
So cache enables for only 10mb is not possible, you have to enable the
whole 128MB.

Greetings,
Christian.

> I tried disabling cache, but performance drops significantly.
>
> I also find this code snippet in GSRD2 design:
>
>  val = mfspr(XREG_SPR_CCR0);
>   val |= 0x50000000;
>   XCache_WriteCCR0(val);
>
>   XCache_EnableICache(0x80000000);
>   XCache_EnableDCache(0x80000000);
>
> Actually I need caching for some 10MB of DDR memory. How to specfy this
> in XCache_EnableXCache() ?


Article: 114038
Subject: Re: OT. Re: Surface mount ic's
From: "Dave Pollum" <vze24h5m@verizon.net>
Date: 3 Jan 2007 06:31:14 -0800
Links: << >>  << T >>  << A >>
Symon wrote:
> "Dave Pollum" <vze24h5m@verizon.net> wrote in message
> news:1167772034.704908.104330@i12g2000cwa.googlegroups.com...
> > Symon wrote:
> >>
> >> p.s. On the subject of US vs. UK toasting techniques, IMO the problem in
> >> the
> >> US is not the toaster machines, it's the post-toasting technology. The
> >> toast
> >> just gets piled up on a plate. The US seems to be a veritable toast rack
> >> desert, so the toast always ends up soggy. I guess that's why it's IHOP
> >> and
> >> not IHOT! :-)
> >
> > I live in the US and use a toaster to toast bread.  The bread goes in
> > vertically.  I don't know what restaurants use.  A toaster oven is a
> > small counter top appliance.  I've never used a toaster oven to toast
> > bread or cook anything - I use mine to relow SMD parts using solder
> > paste ;)
> > -Dave Pollum
> >
> Hi Dave,
> During my times in America, I use a toaster oven to make toast. It works
> just fine. The toaster oven is a cool(hot?) multipurpose US invention, which
> is only just starting to catch on in the UK, IME. But I can't find any of
> these:-
> http://images.google.com/images?hl=en&q=toast+rack
> which greatly enhance the toast experience!
> Cheers, Syms.
> p.s. I don't believe the urban myths about the US and irony, so I know
> you'll appreciate being lectured about food by an Englishman! :-)
> Anyway, we're not as bad as Finland.
> http://news.bbc.co.uk/1/hi/world/europe/4649007.stm

I've never been to Europe or the UK, so I don't know what the food is
like.  I have heard that the French have an overy inflated opinion of
themselves, especially when it comes to food.  Irony sometimes doesn't
translate well, even though we both speak "English".  Wasn't it
Churchill who said that Britain and the US are separated by a common
language?  <LOL>
-Dave Pollum


Article: 114039
Subject: Spartan3 XC3S400 won't work after upgrading ISE from ISE6.3 to ISE8.2
From: "jetq88" <jetq5188@gmail.com>
Date: 3 Jan 2007 07:17:02 -0800
Links: << >>  << T >>  << A >>
anyone has experienced this before and how to fix it? we have an old
design with XC3S400 using ISE6.3, it works fine until I tried to
upgrade to ISE8.2 Sevice Pack3, with exact the same hardware and VHDL
codes and constrain files, it can be downloaded successfully, but it
simply quit work, can someone suggest where I should look into?


Article: 114040
Subject: Re: Bitstream programming
From: Koen Van Renterghem <Ih8teSpam@intec.ugent.be>
Date: Wed, 03 Jan 2007 16:21:28 +0100
Links: << >>  << T >>  << A >>
Hi,

Take a look at the EDN article "Creating quasistatic, parameterized FPGA 
designs" at http://www.edn.com/article/CA313053.html. The author 
describes how to change the contents of the LUTs of an existing bitfile 
and refers to several interesting Xilinx documents.

Regards,
Koen.

quad wrote:
> Hello
> I've started working on Xilinx Virtex II PRo FPGA kit for a project. Is
> there a way to configure bitstreams or netlists programmatically using
> C (i'm not looking at JBits!) so that i can configure the LUTs,IOBs
> according to my circuit needs?
> I also need to invoke iMPACT several times in my code to evaluate the
> fitness of my circuit. Will OLE automation be a solution to this
> problem?
> Any other alternatives or suggestions please!
> Regards
> quadruples
> 

Article: 114041
Subject: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
From: "Tom J" <tj@pallassystems.com>
Date: 3 Jan 2007 07:47:51 -0800
Links: << >>  << T >>  << A >>

Siva Velusamy wrote:
> >
> > 2) I've also tried to use a memory style interface using either the
> > OPB-to-BRAM controller or the LMB-to-BRAM controller.  However, no
> > "Wizard" or component instaniator will fill in all the parameters
> > correctly, and if I try to modify the files (*.mpd or wrapper *.vhd)
> > either they get rewritten over with the original incorrect values or
> > won't compile.  Any suggestions on working this interface will be
> > appreciated.
> >
>
> Try creating an EDK design that has opb_bram. This will instantiate a
> bram block with one port of the BRAM connected to the opb_bram
> controller. Connect the other port of the BRAM to your peripheral.
>
> /Siva

OK, I've tried this.  (I had to select the opb_bram while creating a
new project, the option isn't available in the IP Catalog of an open
project.)  Now I'm back to the same problem I had originally.  How do I
connect these signals, the unattached BRAM port, to my project without
the compiler rewriting the original configurations over my edits?

Tom


Article: 114042
Subject: Re: Surface mount ic's
From: Tim <simon@nooospam.roockyloogic.com>
Date: Wed, 03 Jan 2007 15:48:29 +0000
Links: << >>  << T >>  << A >>
smount wrote:
> Does anyone know what is needed to work with surface mount
> ic's, what sort of starting price tag are we talking about?
> (Assuming I have ready made boards, i.e. only the soldering
> phase is required)

Prices drop all the time, but last time I checked:

$500 to $800 for a decent stereo microscope (you need approx x4 to x10 
mag) with zoom, illumination, a boom arm, and a very heavy base.

$500 to $800 for a hot air solder rig.

Could be less on eBay.

Article: 114043
Subject: Re: Spartan3 XC3S400 won't work after upgrading ISE from ISE6.3 to ISE8.2
From: "bjzhangwn@gmail.com" <bjzhangwn@gmail.com>
Date: 3 Jan 2007 08:01:03 -0800
Links: << >>  << T >>  << A >>
I think you can do a post simulation or cheak the  timing report from
ISE,Also if there are asynchronous  signals in your design or signals
between multi clock domains,and make sure you have deal with it
correctly.Have a good luck ,and if you have fixed it ,can you write it
here.
"jetq88 =D0=B4=B5=C0=A3=BA
"
> anyone has experienced this before and how to fix it? we have an old
> design with XC3S400 using ISE6.3, it works fine until I tried to
> upgrade to ISE8.2 Sevice Pack3, with exact the same hardware and VHDL
> codes and constrain files, it can be downloaded successfully, but it
> simply quit work, can someone suggest where I should look into?


Article: 114044
Subject: Using Altera's SerialLite to create a high-speed data link between Two or more FPGA's
From: "jjlindula@hotmail.com" <jjlindula@hotmail.com>
Date: 3 Jan 2007 08:33:02 -0800
Links: << >>  << T >>  << A >>
Hello, I have a question about using the SerialLite MegaCore Function
to create a high-speed data link between two or more Stratix FPGA's. I
want to know, do I simply tie the two FPGA's TX/RX pins together, or
are there any devices that are required to link the two FPGA's
together? I've been looking over the SerialLite II MegaCore Function
User Guide on page 3-17 they have a Figure that has two FPGA's
connected together and I was thinking, is it that simple, just tie the
TX & RX lines together?

thanks,
joe


Article: 114045
Subject: Re: ISE Simulator radix question
From: "Xiaqing Wu" <Xiaoqing.Wu@xilinx.com>
Date: Wed, 3 Jan 2007 09:17:17 -0800
Links: << >>  << T >>  << A >>
You can change the radix of a bus to display it as binary, hexadecimal,
decimal (signed or unsigned) or ASCII.
To change the radix in waveform viewer:

  1.. Right-click the bus signal value.

  2.. After the bus context menu displays, select Decimal (Signed), Decimal
(Unsigned), Binary, Hexadecimal or ASCII.

In ISE 9.1i release, you can type the following command in ISE simulator
command console:

isim set radix hex

Below is the link to ISE 8.2i help file:

http://toolbox.xilinx.com/docsan/xilinx82/help/iseguide/iseguide.htm

Xiaoqing Wu

"Fred" <fred@nowhere.com> wrote in message
news:459adf5b$0$2446$db0fefd9@news.zen.co.uk...

>
> "Mike Treseler" <mike_treseler@comcast.net> wrote in message
> news:5003s1F1dp3p6U1@mid.individual.net...
> > Fred wrote:
> >
> >> Is there any way in the test bench VHDL file, or anywhere else, I can
> >> force
> >> the radix to remain to be hexadecimal?
> >
> > If you mean ISE/modelsim, the command is
> >
> >   radix hex
> >
> > at the modelsim prompt.
> >
> >         -- Mike Treseler
>
> Many thanks for your reply.
>
> I'm using the ISE Simulator and thought Modelsim was a different
simulator.
> Using ISE Navigator there doesn't seem to be prompt where I can enter such
> text.
>
>



Article: 114046
Subject: Re: PPC cache errata
From: Ben Jackson <ben@ben.com>
Date: Wed, 03 Jan 2007 11:56:36 -0600
Links: << >>  << T >>  << A >>
On 2007-01-03, cpmetz@googlemail.com <cpmetz@googlemail.com> wrote:
> currently I think they should have left the caches out. In my design
> (something with MPMC, some local-link-DMA's and Gig-Ethernet),
> everytime I activate the instruction caches I get Program-Exceptions

Are you clearing the caches first?  The tags seem to persist across
resets, so if you enable the caches without clearing them they will
immediately start returning (stale) data.

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

Article: 114047
Subject: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
From: Siva Velusamy <siva.velusamy@xilinx.com>
Date: Wed, 03 Jan 2007 10:19:41 -0800
Links: << >>  << T >>  << A >>
>> Try creating an EDK design that has opb_bram. This will instantiate a
>> bram block with one port of the BRAM connected to the opb_bram
>> controller. Connect the other port of the BRAM to your peripheral.
>>
>> /Siva
> 
> OK, I've tried this.  (I had to select the opb_bram while creating a
> new project, the option isn't available in the IP Catalog of an open
> project.)  Now I'm back to the same problem I had originally.  How do I
> connect these signals, the unattached BRAM port, to my project without
> the compiler rewriting the original configurations over my edits?
> 
> Tom

Could you post the relevant MHS/MPD sections and the error messages?

I'm guessing the bram_block section should look like this:

BEGIN bram_block
  PARAMETER INSTANCE = opb_bram_if_cntlr_1_bram
  PARAMETER HW_VER = 1.00.a
  BUS_INTERFACE PORTA = opb_bram_if_cntlr_1_port
  BUS_INTERFACE PORTB = custom_pcore_bram_port
END

and your custom_pcore should have an entry like so:

  BUS_INTERFACE PORTA = custom_pcore_bram_port

If its still complicated, please file a hotline case.

/Siva

Article: 114048
Subject: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
From: "Tom J" <tj@pallassystems.com>
Date: 3 Jan 2007 10:57:35 -0800
Links: << >>  << T >>  << A >>

Siva Velusamy wrote:
        <snip>
> Could you post the relevant MHS/MPD sections and the error messages?
>
> I'm guessing the bram_block section should look like this:
>
> BEGIN bram_block
>   PARAMETER INSTANCE = opb_bram_if_cntlr_1_bram
>   PARAMETER HW_VER = 1.00.a
>   BUS_INTERFACE PORTA = opb_bram_if_cntlr_1_port
>   BUS_INTERFACE PORTB = custom_pcore_bram_port
> END
>
> and your custom_pcore should have an entry like so:
>
>   BUS_INTERFACE PORTA = custom_pcore_bram_port

Up to now, I've only been modifying the compiler produced MPD files.  I
assume from your post that I should be generating files of my own as
well/instead.  Is there a reference for these files?  When to use them,
what goes in them, their format, etc.?

Tom


Article: 114049
Subject: xilinx spi example under linux
From: "cpope" <cepope@nc.rr.com>
Date: Wed, 3 Jan 2007 14:20:30 -0500
Links: << >>  << T >>  << A >>
Does anyone have any example code that uses the Xilinx SPI Linux driver? I
just need to read a temperature sensor so something simple that opens the
device and does read and writes should work.

Thanks,
Clark





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