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Messages from 104975

Article: 104975
Subject: Re: Development Boards -Your chance to suggest features
From: Eli Hughes <emh203@psu.edu>
Date: Tue, 11 Jul 2006 08:36:19 -0400
Links: << >>  << T >>  << A >>
John Adair wrote:
> Following our recent Swinyard1 (Virtex-4) release we are now looking at the 
> Swinyard2 module concept which will be based on a middle end Virtex-5 
> (initial XC5VLX50 and others) that will be supported by our Broaddown series 
> of main development boards. Bearing in mind this a small module what 
> features would you like us to put on this module?
> 
> and what did you all think of the general Swinyard concept?
> 
> This is you chance to influence what we deliver to the marketplace so do let 
> us know.
> 
> John Adair
> Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
> Board.
> http://www.enterpoint.co.uk
> 
> 

Hello John:

I just checked out your Swinyard module.  I like the smal formfactor. 
What are those connectors you use on the module?  Do you have a 
Manufacturer/Part #?   I like having the BGA parts on a PCB that I can 
fit on my PCB that I can hand solder.  Are these connectors do-able by 
hand (I can generally do any QFP or QFN Package, but no BGA)?

-Eli


Article: 104976
Subject: wrapper file error : ports not on the entity
From: "7Up" <findadiat@gmail.com>
Date: 11 Jul 2006 05:45:36 -0700
Links: << >>  << T >>  << A >>
My target board is virtex 4 and I'm trying to simulate multi
microblaze processors. I am adding cache controllers to my design which
will cache DDR SDRAM. I've prepared cache controller module for the
same. This cache controller is connected to my microblaze processor
through an OPB bus (processor is master and cache controller is slave
on this OPB). And the same cache controller is connected to DDR SDRAM
through another OPB bus (cache controller is master and DDR SDRAM is
slave on this OPB). So in 'mpd' file of my cache controller  I've
two sets of OPB ports. 1) OPB ports which are used by the master (This
is for cache controller - DDR SDRAM interface)  2) OPB ports which
are used by the slave (This is for processor - cache controller
interface).

I'm giving the ports section of the mpd file of the cache controller
below
MSOPB is the opb bus between cache controller and DDR SDRAM.
SOPB is the opb bus between processor and cache controller.

## Ports
PORT OPB_Clk = "", DIR = I, SIGIS = Clk, BUS = MSOPB:SOPB
PORT OPB_Rst = OPB_Rst, DIR = I, SIGIS = Rst, BUS = MSOPB:SOPB
PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
PORT Sl_errAck = Sl_errAck, DIR = O, BUS = SOPB
PORT Sl_retry = Sl_retry, DIR = O, BUS = SOPB
PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = SOPB
PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = SOPB
PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS =
SOPB
PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS =
SOPB
PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS =
MSOPB:SOPB
PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB
PORT OPB_select = OPB_select, DIR = I, BUS = SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB
PORT M_ABus = M_ABus, DIR = O, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB
PORT M_DBus = M_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB
PORT M_BE = M_BE, DIR = O, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB
PORT M_busLock = M_busLock, DIR = O, BUS = MSOPB
PORT M_request = M_request, DIR = O, BUS = MSOPB
PORT M_RNW = M_RNW, DIR = O, BUS = MSOPB
PORT M_select = M_select, DIR = O, BUS = MSOPB
PORT M_seqAddr = M_seqAddr, DIR = O, BUS = MSOPB
PORT OPB_errAck = OPB_errAck, DIR = I, BUS = MSOPB
PORT OPB_MGrant = OPB_MGrant, DIR = I, BUS = MSOPB
PORT OPB_retry = OPB_retry, DIR = I, BUS = MSOPB
PORT OPB_timeout = OPB_timeout, DIR = I, BUS = MSOPB
PORT OPB_xferAck = OPB_xferAck, DIR = I, BUS = MSOPB

In the hdl files (user_logic.v and cache_cntlr.vhdl) of the cache
controller I've defined signals according to the ports on the
corresponding bus.
The problem is that while generating the netlist, wrapper file named
"cache_cntlr_1_wrapper.vhd" is giving the error:

"No default binding for component: <cache_cntlr>. Ports
<M_ABus,M_DBus,M_BE,M_busLock,M_request,M_RNW,M_select,M_seqAddr,OPB_errAck,
   OPB_MGrant,OPB_retry,OPB_timeout,OPB_xferAck> are not on the
entity."

Now, as I said before, I've defined these ports in the mpd file and
then defined necessary user ports in the user logic file and vhdl file.
I can't understand then how these ports are "not on the entity".
Please help me understand my mistake. I'll be highly obliged.


Thanks.
7Up


Article: 104977
Subject: DIFFICULT MULTICYCLE PATH WITH QUARTUS II
From: "pippo" <salvatore.callea@aleniaspazio.it>
Date: 11 Jul 2006 05:46:53 -0700
Links: << >>  << T >>  << A >>
Hallo to everybody,
i'm trying to map a very large design onto a stratix EP1S80B956C7
device.
After timing analysis with Quartus II 5.0 i have a "lot of high setup
violations"
on paths between registers of the such type of FF1 and FF2
(see vhdl below that is pheraps only a simplification of the entire
project).
These paths are multicycle 2 period wide.
Apart from clock settings, in the Assignment Editor i gave to Quartus
the subsequent constraints:

set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE 2 -from ENA -to
ENA
set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE 2 -from
internal_EN1 -to internal_EN1
set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE 2 -to
internal_EN1
set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE 2 -from
internal_ENA -to internal_ENA
set_instance_assignment -name CLOCK_ENABLE_MULTICYCLE 2 -from
internal_ENA -to *

and after i ran timing analysis again, i got the Ignored Timing
Assignments in the report:


-------- option ---------------- setting ---- from --------- to
----------------- help -----------
Clock Enable Multicycle     2                         internal_EN1   No
timing path applicable to specified destination
Clock Enable Multicycle     2    internal_EN1   internal_EN1   No
timing path applicable to specified source and destination
Clock Enable Multicycle     2    internal_ENA   *
Destination wildcard does not match any nodes
Clock Enable Multicycle     2    internal_ENA   internal_ENA   No
timing path applicable to specified source and destination
Clock Enable Multicycle     2    ENA                ENA
No timing path applicable to specified source and destination

How can i force Quartus to consider paths enabled by ENA signal and
clocked by CLK
as multicycle paths without specifying all registers interested
(it would be difficult for me to built a list, because of their huge
number)?

Thanks in advance.
Salva


------------------ VHDL ------------------

library ieee;
    use ieee.std_logic_1164.all;

entity PROVA is
    port (
        RSTN : in  std_logic;
        CLK  : in  std_logic;
        IN1  : in  std_logic;
        IN2  : in  std_logic;
        EN1  : in  std_logic;
        EN2  : in  std_logic;
        OUT1 : out std_logic;
        OUT2 : out std_logic
    );
end entity PROVA;

architecture ARCH_1 of PROVA is

    component GLOBAL is
    port (
        A_IN : in  std_logic;
        A_OUT: out std_logic
    );
    end component GLOBAL;

    signal internal_CLK : std_logic;
    signal internal_EN1 : std_logic;
    signal internal_EN2 : std_logic;
    signal internal_ENA : std_logic;

    signal ENA : std_logic;
    signal FF1 : std_logic;
    signal FF2 : std_logic;
    signal FF3 : std_logic;

begin

-- clock is assigned to a global resource
    GLOBAL_STRATIX1: GLOBAL port map(CLK, internal_CLK);


-- enable is assigned to a global resource
    GLOBAL_STRATIX2: GLOBAL port map(internal_ENA, ENA);


-- internally latched signals
    internal_CLK_P: process (RSTN, internal_CLK)
    begin
        if    (RSTN = '0') then
            internal_EN1 <= '0';
            internal_EN2 <= '0';
        elsif falling_edge(internal_CLK) then -- falling edge
            internal_EN1 <= EN1;
            internal_EN2 <= EN2;
        end if;
    end process;


-- internally generated enable
    internal_ENA <= internal_EN1 and internal_EN2;


-- FF with internally generated enable
    FF_1_2_P: process (RSTN, internal_CLK)
    begin
        if    (RSTN = '0') then
            FF1 <= '0';
            FF2 <= '0';
        elsif rising_edge(internal_CLK) then -- rising edge
            if ENA = '1' then
                FF1 <= IN1;
                if IN1 = IN2 then
                    FF2 <= '1';
                end if;
            end if;
        end if;
    end process;


-- FF without internally generated enable
    FF_3_P: process (RSTN, internal_CLK)
    begin
        if    (RSTN = '0') then
            FF3 <= '0';
        elsif rising_edge(internal_CLK) then -- rising edge
            FF3 <= IN1 and FF2;
        end if;
    end process;


-- outputs assignments
   OUT1 <= FF1 or FF2;
   OUT2 <= FF1 and FF3;


end ARCH_1;


Article: 104978
Subject: Re: The FFs with synchronous reset perform worse?
From: "KJ" <Kevin.Jennings@Unisys.com>
Date: 11 Jul 2006 05:55:41 -0700
Links: << >>  << T >>  << A >>

> This is for ASIC. For FPGAs all the cells are already hard-wired. I
> haven't looked carefully but I doubt the timing of the DFFs in any
> FPGA depends on whether it's configured for async/sync or no reset.

Ummm....regardless of the technology the timing depends totally on
whether or not the async inputs are used or not.

If only sync resets are used then the output of the flip flops will
occur after some 'clock to output' delay after the appropriate edge of
the clock.

For async resetable flip flops, the output can change at TWO distinct
times, the first being the above mentioned 'clock to output delay', the
other being the 'reset to output' delay.

You certainly can't count on the clock and reset routing delays and the
'xxx to output' delays to happen to add up to be the same, you have to
do the timing analysis.  No matter how you slice it, using async inputs
to a synchronous element will always cause you to analyze the path that
leads through the clock input and the other that leads through the
async input, there are no shortcuts.

KJ


Article: 104979
Subject: Re: debouncing a switch (in hardware)
From: "Gabor" <gabor@alacron.com>
Date: 11 Jul 2006 06:14:11 -0700
Links: << >>  << T >>  << A >>

aName wrote:
> Bob Perlman wrote:
>
> > Hi -
> >
> > On 6 Jul 2006 11:53:39 -0700, "Brian McFarland"
> > <brian.mcf1985@gmail.com> wrote:
> >
> >
> >>I've been messing around with my own sort of development board for an
> >>Altera MAX 3064 because I have some downtime at work (I'm a coop) and
> >>wanted to teach myself some PLD stuff.  I wanted ot put a manual clock
> >>button on it so I could just mess around with some simple designs to
> >>get a feel for how to use HDL's and Quartus.  I have some DIPs for
> >>inputs and LEDs for outputs, everything run on 3.3V.   But the I can't
> >>manage to get the clock to pulse just once when I press the button.
> >>Can anyone recomend a debouncing circuit to use for something l like
> >>this?
> >
> >
> > Jack Ganssle has written extensively about this.  Here's a paper that
> > summarizes his findings and design suggestions:
> >
> > http://www.ganssle.com/debouncing.pdf
> >
> > Bob Perlman
> > Cambrian Design Works
> > http://www.cambriandesign.com
>
>
> I just finished implementing a small protoboard with 12 unbonced
> switches, I used a safe SRLatch type approach :-)
>
> And it works like heaven ;-)

SRLatch works with SPDT, if you need to debounce SPST, which is more
common, you need to have something with a timing circuit in it like the
Maxim MAX6817 dual switch debouncer:

http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1896

As I recall switch debouncer IC's have been around since early days
of 4000 series CMOS.

Have Fun,
Gabor


Article: 104980
Subject: Re: High-speed DAC/ADC with FPGA
From: "Andy" <jonesandy@comcast.net>
Date: 11 Jul 2006 06:15:00 -0700
Links: << >>  << T >>  << A >>
National Semiconductor has a development board for their dual
ADC08D1500 dual 1500 MSPS, 8 bit ADCs that includes a Xilinx V4 FPGA
and a USB interface controller on board. The dual converters can be
automatically interleaved on the same input for 3000 MSPS. 1:2
demultiplexed LVDS outputs to the FPGA. I've heard they and Altera are
also working on a similar development board.

Andy

Peter Alfke wrote:
> Many A/D converters have a double-width digital interface, which
> reduces the FPGA capture rate by a factor two (but doubles the number
> of bits)
> I have seen sample rates of 1 Gsps interfaced to FPGAs (guess which
> ones).
> Make sure that the sampling clock is as clean as possible. Any jitter
> will severely impact your analog noise floor, i.e. will reduce the
> dynamic range.
>
> Peter Alfke, Xilinx
> ====================
> rnbrady wrote:
> > Hi folks
> >
> > I'm working with an Altera Stratix ep1s10 on a development board. The
> > data sheet says the IO can operate at rates up to 800 MSPS. If I have a
> > look on the internet, I see DAC and ADC technology going up to 400
> > MSPS.
> >
> > My application is software defined radio, where the general mantra is
> > to do as little analog front-end as possible, i.e. sample as fast as
> > you can.
> >
> > What are the limits on my conversion rates? I doubt it's even remotely
> > possible for me to do data conversion at 400 MSPS? My main concern is
> > the PCB layout, with about 15cm of track and a header between the FPGA
> > and the conversion chips. Crosstalk, EMI and impedance matching are all
> > things I know very little about.
> >
> > Is there a more appropraiate group to post on?
> > 
> > Thanks in advance,
> > Richard


Article: 104981
Subject: Re: High-speed DAC/ADC with FPGA
From: "MM" <mbmsv@yahoo.com>
Date: Tue, 11 Jul 2006 10:11:40 -0400
Links: << >>  << T >>  << A >>
"rnbrady" <rnbrady@gmail.com> wrote in message
news:1152606377.870160.319660@m73g2000cwd.googlegroups.com...
>
> I'd like to capture and generate signals anywhere from 10kHz to 100MHz.
> It would be great if I could reach 450MHz with some mixing at the front
> end. I don't really need more than 1MHz at a time. So a lower rate with
> a NCO + mixer might be a better bet.

Have you considered undersampling? You could do any part of your band
without needing any mixers and/or excessively high sampling rates. Covering
whole band would require switchable anti-aliasing filters...

/Mikhail



Article: 104982
Subject: Re: High-speed DAC/ADC with FPGA
From: jean-baptiste.nouvel@jdsu.com
Date: 11 Jul 2006 07:19:45 -0700
Links: << >>  << T >>  << A >>
Richard,

just a quick remark : don't forget in your design phase the
bottleneck that can be the ADC-to-CPU interface.
For instance
> ADC08D1500 dual 1500 MSPS, 8 bit ADCs that includes a Xilinx V4 FPGA
> and a USB interface controller on board. The dual converters can be
I understand wouldn't allow to do real time as USB is limited to
480Mbps
if I remember well.

Have a look at this very good article from Xilinx's XCELL magazine
Capturing Data from Gigasample Analog-to-Digital Converters
http://tinyurl.com/ng738
It explains how you can achieve high data rates sampling in an FPGA.

With respect to Signal Integrity then yes, you can achieve 400MSPS
but indeed with a bit of care. Probably the most important things
that you have to check are :
* The length of the traces (clock, data) will have to be equalised
(400MHz is 2.5ns period and 15cm on a PCB is probaply between 1ns
and 1.5ns depending on various parameters).
* as you are going to design the ADC board, I would place series
termination on (the clock, of course) but on the data as well
to make sure there is no ringing on these signals (ie the
resistance is high enough 30 ohms, 40 ohms...).
This is the minimum you have to guarantee on your 2 layer PCB.
Use local power grounds as well.

Hope this helps, 

jb


Article: 104983
Subject: Re: DIFFICULT MULTICYCLE PATH WITH QUARTUS II, or any other tool
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 11 Jul 2006 07:22:05 -0700
Links: << >>  << T >>  << A >>
pippo,

What you describe is a classical timing closure problem.

The only way I was able to make sure I closed the timing on the right
paths, and not break the timing on others, was to make an exhaustive
list of multi-cycle paths so that the synthesis tool did not make any
assumptions of its own.

The tool I used did have wildcards, which helped a great deal, as I had
all the paths in question (mostly buses) with easily recognized names
with bit numbers.

Austin

Article: 104984
Subject: Re: High-speed DAC/ADC with FPGA
From: jean-baptiste.nouvel@jdsu.com
Date: 11 Jul 2006 07:22:35 -0700
Links: << >>  << T >>  << A >>
Richard,

just a quick remark : don't forget in your design phase the
bottleneck that can be the ADC-to-CPU interface.
For instance
> ADC08D1500 dual 1500 MSPS, 8 bit ADCs that includes a Xilinx V4 FPGA
> and a USB interface controller on board. The dual converters can be
I understand wouldn't allow to do real time as USB is limited to
480Mbps
if I remember well.

Have a look at this very good article from Xilinx's XCELL magazine
Capturing Data from Gigasample Analog-to-Digital Converters
http://tinyurl.com/ng738
It explains how you can achieve high data rates sampling in an FPGA.

With respect to Signal Integrity then yes, you can achieve 400MSPS
but indeed with a bit of care. Probably the most important things
that you have to check are :
* The length of the traces (clock, data) will have to be equalised
(400MHz is 2.5ns period and 15cm on a PCB is probaply between 1ns
and 1.5ns depending on various parameters).
* as you are going to design the ADC board, I would place series
termination on (the clock, of course) but on the data as well
to make sure there is no ringing on these signals (ie the
resistance is high enough 30 ohms, 40 ohms...).
This is the minimum you have to guarantee on your 2 layer PCB.
Use local power grounds as well.

Hope this helps,

jb
> Peter Alfke wrote:
> > Many A/D converters have a double-width digital interface, which
> > reduces the FPGA capture rate by a factor two (but doubles the number
> > of bits)
> > I have seen sample rates of 1 Gsps interfaced to FPGAs (guess which
> > ones).
> > Make sure that the sampling clock is as clean as possible. Any jitter
> > will severely impact your analog noise floor, i.e. will reduce the
> > dynamic range.
> >
> > Peter Alfke, Xilinx
> > ====================
> > rnbrady wrote:
> > > Hi folks
> > >
> > > I'm working with an Altera Stratix ep1s10 on a development board. The
> > > data sheet says the IO can operate at rates up to 800 MSPS. If I have a
> > > look on the internet, I see DAC and ADC technology going up to 400
> > > MSPS.
> > >
> > > My application is software defined radio, where the general mantra is
> > > to do as little analog front-end as possible, i.e. sample as fast as
> > > you can.
> > >
> > > What are the limits on my conversion rates? I doubt it's even remotely
> > > possible for me to do data conversion at 400 MSPS? My main concern is
> > > the PCB layout, with about 15cm of track and a header between the FPGA
> > > and the conversion chips. Crosstalk, EMI and impedance matching are all
> > > things I know very little about.
> > >
> > > Is there a more appropraiate group to post on?
> > > 
> > > Thanks in advance,
> > > Richard


Article: 104985
Subject: Re: Development Boards -Your chance to suggest features
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Tue, 11 Jul 2006 15:38:53 +0100
Links: << >>  << T >>  << A >>
Eli

The connector is a GFZ family from Samtec and are totally solderless. You 
will see a number of nylon bolts holding the board onto the host board that 
provides outside world services like supply voltages etc. The GFZ is a 
sprung contact that when the boards are tightened up together make contact. 
The simple version of the Moel-Bryn socket that we currently use has 2 GFZ 
connectors of 40x10 ways each so we get a high number of I/Os available and 
have a wide range of supporting features.

The Moel-Bryn socket pinout will be available under a license/NDA. The 
license won't necessarily cost anything unless you want to make your own 
modules. One of our intentions is that these modules could be used to bring 
high technology to what are relatively low technology host boards as well as 
the main development board use.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk


"Eli Hughes" <emh203@psu.edu> wrote in message 
news:e90603$s52$1@f04n12.cac.psu.edu...
> John Adair wrote:
>> Following our recent Swinyard1 (Virtex-4) release we are now looking at 
>> the Swinyard2 module concept which will be based on a middle end Virtex-5 
>> (initial XC5VLX50 and others) that will be supported by our Broaddown 
>> series of main development boards. Bearing in mind this a small module 
>> what features would you like us to put on this module?
>>
>> and what did you all think of the general Swinyard concept?
>>
>> This is you chance to influence what we deliver to the marketplace so do 
>> let us know.
>>
>> John Adair
>> Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
>> Board.
>> http://www.enterpoint.co.uk
>>
>>
>
> Hello John:
>
> I just checked out your Swinyard module.  I like the smal formfactor. What 
> are those connectors you use on the module?  Do you have a 
> Manufacturer/Part #?   I like having the BGA parts on a PCB that I can fit 
> on my PCB that I can hand solder.  Are these connectors do-able by hand (I 
> can generally do any QFP or QFN Package, but no BGA)?
>
> -Eli
> 



Article: 104986
Subject: Re: Development Boards -Your chance to suggest features
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Tue, 11 Jul 2006 15:59:34 +0100
Links: << >>  << T >>  << A >>
On Tue, 11 Jul 2006 15:38:53 +0100, John Adair wrote:

[...]
> One of our intentions is that these modules could be used to bring 
>high technology to what are relatively low technology host boards

This is a truly excellent idea.  For some while I've been frustrated
by FPGA development boards that have a ragbag of low-tech
functionality and connectors, pushing up the price just for me
to get something I could easily provide for myself.  What you're
offering fixes that - for many users, even in small-scale production,
the FPGA is the only part of the system that needs fine-line
PCBs and non-trivial assembly techniques, and a small FPGA-only
plug-in module is the right answer.

My only concern would be that you've gone for a fairly high-end
FPGA so the entry cost is quite high.  Fine for some purposes,
but pricing itself out of a potentially useful market for others.
Have you any plans for a significantly lower-cost product with
a similar overall approach?

Thanks
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 104987
Subject: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 11 Jul 2006 08:18:08 -0700
Links: << >>  << T >>  << A >>
Hi Dann,
I have 3 good website to deal with sorting speed:
1. http://www.azillionmonkeys.com/qed/sort.html
2. http://www.eternallyconfuzzled.com/tuts/sorting.html#heap
3.
http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/d8380e137bdb410f/6d2a65ca85ac8bfc?lnk=st&q=Bitonic+sort&rnum=10#6d2a65ca85ac8bfc

None of them mentioned radix sorting as the candidate as the fastest
sorting algorithm.

In the last email I referenced a measurement:
with 1000 values, the times were: ~275000 in clocks for bucket, ~435000
in clocks for qsort.

The measurement was made in 1999.

I like to have more similar data in clocks with best algorithm and best
CPU available now.

I really don't understand that for one data, above measurement needs
1000 clocks . 

Why? Any comments?

Weng


Article: 104988
Subject: DLL in spartan2e
From: "bjzhangwn@gmail.com" <bjzhangwn@gmail.com>
Date: 11 Jul 2006 08:20:38 -0700
Links: << >>  << T >>  << A >>
Hi,everyone,I now use the spartan2e400,and I want to use the dll in
fpga,I need 4 clock in fpga,so I have to divide the clock by using the
dlls,I used 3 dlls for my design,and all inputs are the same drived by
clock input ,but when place and route  ,the system bring errors like
"can't place the clock pad or can't place the bupg buffers",and the
input clock I constaint it on the global clock,so I have no idea.I do
another thing ,I use only two dlls ,and the design can pass place and
route.


Article: 104989
Subject: Re: High-speed DAC/ADC with FPGA
From: "Andy" <jonesandy@comcast.net>
Date: 11 Jul 2006 09:05:08 -0700
Links: << >>  << T >>  << A >>
The point of the USB interface it not to be able to transfer
sample-rate data in real time, it is presumed that a large amount of
processing (i.e. demodulation, etc.) is done in the fpga to reduce the
output data rate to something that could be handled in real or near
real (buffered) time over the USB interface.

Andy


jean-baptiste.nouvel@jdsu.com wrote:
> Richard,
>
> just a quick remark : don't forget in your design phase the
> bottleneck that can be the ADC-to-CPU interface.
> For instance
> > ADC08D1500 dual 1500 MSPS, 8 bit ADCs that includes a Xilinx V4 FPGA
> > and a USB interface controller on board. The dual converters can be
> I understand wouldn't allow to do real time as USB is limited to
> 480Mbps
> if I remember well.
>
> Have a look at this very good article from Xilinx's XCELL magazine
> Capturing Data from Gigasample Analog-to-Digital Converters
> http://tinyurl.com/ng738
> It explains how you can achieve high data rates sampling in an FPGA.
>
> With respect to Signal Integrity then yes, you can achieve 400MSPS
> but indeed with a bit of care. Probably the most important things
> that you have to check are :
> * The length of the traces (clock, data) will have to be equalised
> (400MHz is 2.5ns period and 15cm on a PCB is probaply between 1ns
> and 1.5ns depending on various parameters).
> * as you are going to design the ADC board, I would place series
> termination on (the clock, of course) but on the data as well
> to make sure there is no ringing on these signals (ie the
> resistance is high enough 30 ohms, 40 ohms...).
> This is the minimum you have to guarantee on your 2 layer PCB.
> Use local power grounds as well.
> 
> Hope this helps, 
> 
> jb


Article: 104990
Subject: Xilinx Virtex-4 APU Controller Questions
From: "Jarrod Wood" <jarrodjwood@gmail.com>
Date: 11 Jul 2006 09:51:10 -0700
Links: << >>  << T >>  << A >>
Hello all,

I am in the process of creating a floating point FCM that interfaces
with the APU controller on a ML403 development board. After studying
the documentation, I have a few questions:

1. In the PowerPC405 Processor block reference (UG018), on page 207, a
generic FCM Load Instruction example is presented. Is this an example
of a floating point register load instruction? i.e. if the instruction
"lfd 1,rX(0)" (Load floating point double) is issued, will the APU
follow this example and automatically fetch the data indexed at rX and
then send the instruction plus data to the FPU and let it decode that
the data should go in floating point register 1? Or is this load
example for a special type of UDI?

2. How do you enable hardware floating point support in the EDK
software compiler?

3. On page 188 of the PPC Block Reference, it is stated that three
groups of FP instructions can be selectively disabled: complex arith,
conversion, and estimates. How do you inform the compiler, either the
EDK or a ppc gnu cross compiler that these instructions are not
available? If that isn't possible, what happens if they try to execute
that instruction? Does the APU or FCM simply issue an exception and
hope that the software handles it?


Any advice or suggestions would be greatly appreciated. Thank you.

Sincerely,
Jarrod Wood


Article: 104991
Subject: Re: Development Boards -Your chance to suggest features
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Tue, 11 Jul 2006 17:55:55 +0100
Links: << >>  << T >>  << A >>
The big issue with the GFZ connectors is that they themselves are not low 
cost and tend to set a base cost for the module that takes it out of the 
very low cost sector. However we have on our roadmap a FX12 module that is 
going to use our DIl style connectors at the lower end. We are also 
considering the same as a Spartan-3 solution. Other variations of the theme 
we are considering are a module that breaks out a BGA usable PGA on 2.54mm. 
We have already done that on a non-FPGA part for a very fine pitch BGA and 
in a reasonably economic way for one of our customers.

The Swinyard2 board will cover a cheaper sector than the Swinyard1 that you 
can see on the website. Also if you are considering a small production run 
there is room for discounting on Swinyard1. We are pricing on small batch 
assembly costs due to the price of some of the silicon. We don't plan on 
hold hugh stocks of these boards as there are 18 possible fits of FPGA on 
Swinyard1 by the time you consider all sizes and speed grades available. We 
are planning to hold stock of a small number of variants - the LX40 and SX55 
initially more if we see the a steady market. As these FPGA  are common with 
our Broaddown4 product we may also have a quick assemble to order capability 
but that depends highly on stock we have at any given time.

Putting a commercial spin on what we do we can usually come up with a cost 
effective solution for products in fairly low production numbers. I won't 
put exact numbers on it as I'm sure someone will disagree about what is 
considered cost effective but we commonly provide custom solutions for year 
product volumes of 10-25 units. By the time we hit 100 off batches we aren't 
China style prices but we can definately give good value in the European and 
N America context.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development 
Board.
http://www.enterpoint.co.uk


"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message 
news:npe7b21ppkddj74csrgr02pvjcbcu36b7l@4ax.com...
> On Tue, 11 Jul 2006 15:38:53 +0100, John Adair wrote:
>
> [...]
>> One of our intentions is that these modules could be used to bring
>>high technology to what are relatively low technology host boards
>
> This is a truly excellent idea.  For some while I've been frustrated
> by FPGA development boards that have a ragbag of low-tech
> functionality and connectors, pushing up the price just for me
> to get something I could easily provide for myself.  What you're
> offering fixes that - for many users, even in small-scale production,
> the FPGA is the only part of the system that needs fine-line
> PCBs and non-trivial assembly techniques, and a small FPGA-only
> plug-in module is the right answer.
>
> My only concern would be that you've gone for a fairly high-end
> FPGA so the entry cost is quite high.  Fine for some purposes,
> but pricing itself out of a potentially useful market for others.
> Have you any plans for a significantly lower-cost product with
> a similar overall approach?
>
> Thanks
> -- 
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.bromley@MYCOMPANY.com
> http://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated. 



Article: 104992
Subject: Virtex-4 Vicm for LVDS with Vcco = 3.3V.
From: "Symon" <symon_brewer@hotmail.com>
Date: 11 Jul 2006 19:19:38 +0200
Links: << >>  << T >>  << A >>
Hi All,
So, it looks like it's OK for me to use an unterminated LVDS input on an I/O 
bank with Vcco = 3.3V. I even checked that the tools don't complain! Does 
anyone know of any data for Vicm (the common mode range) for these inputs? 
If the receivers are powered by Vccaux, I assume the spec is the same as for 
LVDS_25, otherwise maybe the spec scales with Vcco.
TIA, Syms. 



Article: 104993
Subject: Re: High-speed DAC/ADC with FPGA
From: "PeteS" <PeterSmith1954@googlemail.com>
Date: 11 Jul 2006 10:45:20 -0700
Links: << >>  << T >>  << A >>
rnbrady wrote:
> Hi guys
>
> Thanks for the helpful replies.
>
>
> > More details are really needed:
> >
> > What type of header are you talking about? I have run signals at 5Gb/s
> > through connectors designed for the task with little loss and very low
> > crosstalk, but they aren't cheap. Is this an existing header?
>
> The headers are existing. They are standard beak-away headers.
>
> > Does this mean you want to run wires, or are you making a circuit board
> > for the A-D? You are unlikely to get high data rates with handwired
> > circuitry (you can get reasonably high speeds, but not too high unless
> > you are an expert in wirewrap and routing ;).
>
> I plan to have a PCB made. We have facilities for two layer PCB
> manufacturing.
>
> > You say you are using a development board. What documentation is there
> > for it? Point us at some details if you have them.
>
> I'm working with an Altera dev kit:
> http://www.altera.com/products/devkits/altera/kit-nios_1S10.html
>
> There is tons of documentaion for the NiosII embedded CPU on this dev
> kit but almost no documnetation on the board itself.
>
> > What is the interface from your A-D converter(s)? Serial? Parallel?
>
> I'd find it simpler to do parallel, there's no shortage of pins.
>
> > Parallel may take more lines, but it also gives the lowest data rate.
> > There are also tricks of synchronised sampling (using multiple
> > converters, suitably calibrated) to increase the effective sample rate,
> > should that be necessary. On that subject, is there a particular A-D
> > device you have in mind, or are you open to suggestions?
>
> Completely open.
>
> > What signal frequency range are you particularly interested in getting?
> > If you are not sure of what to use, this will let others help you
> > choose an appropriate device.
>
> I'd like to capture and generate signals anywhere from 10kHz to 100MHz.
> It would be great if I could reach 450MHz with some mixing at the front
> end. I don't really need more than 1MHz at a time. So a lower rate with
> a NCO + mixer might be a better bet. The basic idea to to be able to
> receice and transmit commercial FM and AM, plus some walkie-talkie FM,
> and maybe some HAM radio, all with as little HW as possible.
>
> >
> > Even if you sample with a decent A-D, you should still (in my opinion)
> > put an anti-aliasing filter on the front end, and buffering to prevent
> > loading. (Some parts have them internally). Unless you have a buffered
> > output from something, you are probably going to have to put down at
> > least some analog circuitry apart from the A-D(s).
>
> This is fine, I simply want to keep it to a minimum.
>
> > Speaking of that, what RF device did you intend to use to get the
> > signal in the first place?
>
> An antenna.
>
> >
> > Answer those (reply to both groups) and some of the denizens of s.e.d.
> > will no doubt dispense some ideas, and no doubt ask more questions.
>
> Thanks again. I really appreciate your input.
>
> Richard

<Had to wait until I got home - was too busy at the day job to respond
;) >

I don't have any information on the buffers, but the header you have
probably runs out of steam at around a few MHz. If you have the
schematic for your dev. board , send it to me (you can find my email
via my profile) and I'll check the ratings on the buffers (if they
exist). I'll consider this one of my good deeds[tm] for the week :)

A two layer PCB (as noted by the esteemed Bill) may be ok with careful
layout. At a minimum, you'll have to have clean power to the A-D and
the appropriate clocks/framing etc., and then run the actual data back
across. Of course, keeping the signal to be sampled clean is an
absolute must (pretty pointless if you don't).

What resolution did you want to get? There are a number of solutions at
reasonably high speeds up to 24 bits (although they aren't cheap; say
$30 to $100s per unit depending on features, and that's in 1k qtys)

How up are you on A-D theory and practise? A device may say 24 bits but
you'll typically get an equivalent 21 bits or so due to the various
errors and noise (some manufacturers are good about putting such things
in their data sheets, others less so), and then there's some tricks of
the trade in the layout to ensure you get the best out of the device
(indeed, get anything useful at all).

The RF signal is going to be pretty low (to say the least) although
some newer devices designed for the task can deal with it - in that
case, you are looking at a different class of A-D with low noise PGAs
on the front end. A wideband RF amp and perhaps some band shaping may
be in order. There are simple solutions for that around, but it will
increase the complexity of the design somewhat.

Perhaps a digitally controlled mixer / IF stage might be a solution;
after all, you can do all sorts of band selection in hardware, and that
can be set up for the band you desire.

A lot of this will depend on exactly what you really need, of course.
If you want to do pre-amplification and selection, life becomes much
simpler (use a single IF output stage set by a mixer perhaps) that is
then sampled.

Cheers

PeteS


Article: 104994
Subject: Re: Virtex-4 Vicm for LVDS with Vcco = 3.3V.
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 11 Jul 2006 10:45:49 -0700
Links: << >>  << T >>  << A >>
Symon,

The LVDS input buffer is a full CMOS differential comparator.  You may
go within ~ 0.6 volts of either ground, or Vccaux, and it will still
meet speed spec.

You may go all the way to the rails (and even a bit beyond -- see abs
max pin V specs), but then you take the diff stage out of its linear
region, and it gets a bit slower.

Austin

Symon wrote:
> Hi All,
> So, it looks like it's OK for me to use an unterminated LVDS input on an I/O 
> bank with Vcco = 3.3V. I even checked that the tools don't complain! Does 
> anyone know of any data for Vicm (the common mode range) for these inputs? 
> If the receivers are powered by Vccaux, I assume the spec is the same as for 
> LVDS_25, otherwise maybe the spec scales with Vcco.
> TIA, Syms. 
> 
> 

Article: 104995
Subject: Assigning unused pins in Quartus II
From: "rnbrady" <rnbrady@gmail.com>
Date: 11 Jul 2006 10:58:14 -0700
Links: << >>  << T >>  << A >>
Hi folks

I have a VHDL design which I'm putting on an FPGA with Quartus II.
There is a specific pin on the FPGA which I need to drive high. This
pin has no corresponding port in my VHDL file and I don't want to edit
the VHDL file.

I can find the option in Quartus to assign all unused pins to say
"driving low." However I want to keep the default at "driving low"
while assigning just this pin to "driving high."

The reason for this is that the default drving low value causes the
configuration controller on my dev-kit (NiosII Stratix kit) to
reconfigure repeatedly.

How can I assign just one pin to drive high? I'm certain it can be
done, but for the life of me I cannot find the option in Quartus.

Thanks in advance,
Richard


Article: 104996
Subject: Re: Assigning unused pins in Quartus II
From: "Tommy Thorn" <tommy.thorn@gmail.com>
Date: 11 Jul 2006 11:12:15 -0700
Links: << >>  << T >>  << A >>
rnbrady wrote:
> I have a VHDL design which I'm putting on an FPGA with Quartus II.
> There is a specific pin on the FPGA which I need to drive high. This
> pin has no corresponding port in my VHDL file and I don't want to edit
> the VHDL file.
>
> I can find the option in Quartus to assign all unused pins to say
> "driving low." However I want to keep the default at "driving low"
> while assigning just this pin to "driving high."

This is one of the most mind boggling things about Quartus II.  By
default it set all unspecified pins to ground, which is a terrible
default as one quick first test is likely to miss this and will end up
driving ground to a bunch of should-be input pins.

Richard, the fix for you problem is (from memory) to enter the general
settings (assignments?) and change the pin default from "output driving
ground" to "input tristated".  That should solve this problem
completely.

Tommy


>
> The reason for this is that the default drving low value causes the
> configuration controller on my dev-kit (NiosII Stratix kit) to
> reconfigure repeatedly.
>
> How can I assign just one pin to drive high? I'm certain it can be
> done, but for the life of me I cannot find the option in Quartus.
> 
> Thanks in advance,
> Richard


Article: 104997
Subject: Re: debouncing a switch (in hardware)
From: aName <anEmail@anAddress.com>
Date: Tue, 11 Jul 2006 14:31:35 -0400
Links: << >>  << T >>  << A >>
Gabor wrote:
> aName wrote:
> 
>>Bob Perlman wrote:
>>
>>
>>>Hi -
>>>
>>>On 6 Jul 2006 11:53:39 -0700, "Brian McFarland"
>>><brian.mcf1985@gmail.com> wrote:
>>>
>>>
>>>
>>>>I've been messing around with my own sort of development board for an
>>>>Altera MAX 3064 because I have some downtime at work (I'm a coop) and
>>>>wanted to teach myself some PLD stuff.  I wanted ot put a manual clock
>>>>button on it so I could just mess around with some simple designs to
>>>>get a feel for how to use HDL's and Quartus.  I have some DIPs for
>>>>inputs and LEDs for outputs, everything run on 3.3V.   But the I can't
>>>>manage to get the clock to pulse just once when I press the button.
>>>>Can anyone recomend a debouncing circuit to use for something l like
>>>>this?
>>>
>>>
>>>Jack Ganssle has written extensively about this.  Here's a paper that
>>>summarizes his findings and design suggestions:
>>>
>>>http://www.ganssle.com/debouncing.pdf
>>>
>>>Bob Perlman
>>>Cambrian Design Works
>>>http://www.cambriandesign.com
>>
>>
>>I just finished implementing a small protoboard with 12 unbonced
>>switches, I used a safe SRLatch type approach :-)
>>
>>And it works like heaven ;-)
> 
> 
> SRLatch works with SPDT, if you need to debounce SPST, which is more
> common, you need to have something with a timing circuit in it like the
> Maxim MAX6817 dual switch debouncer:
> 
> http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1896
> 
> As I recall switch debouncer IC's have been around since early days
> of 4000 series CMOS.
> 
> Have Fun,
> Gabor
> 


Yes of course for SPST amd unbounced pulse you can go with something 
like MAX6818  (they have free samples):-)

I choose SPDT and SRLatch because I wanted unbounced transitions and 
stables states (High Low)  so I can decompose clock and other stuff ;-)


Article: 104998
Subject: Re: High-speed DAC/ADC with FPGA
From: "MM" <mbmsv@yahoo.com>
Date: Tue, 11 Jul 2006 14:33:37 -0400
Links: << >>  << T >>  << A >>
"PeteS" <PeterSmith1954@googlemail.com> wrote in message
news:1152639919.953010.283430@p79g2000cwp.googlegroups.com...
>
> A two layer PCB (as noted by the esteemed Bill) may be ok with careful
> layout.

If you try to do a 2-layer PCB for high-speed ADC/DAC you are on your own
with zero support from manufacturer. The chip pinouts are designed in the
assumption of existence of GND and PWR planes. I don't beleive one can get
advertised performance of a high-speed ADC/DAC using a 2-layer board. One
will be lucky if it will function at all...

> What resolution did you want to get? There are a number of solutions at
> reasonably high speeds up to 24 bits (although they aren't cheap; say
> $30 to $100s per unit depending on features, and that's in 1k qtys)

There no ADCs on the market with more than 14 bits that can cover the
requested band of 450 MHz.  If oversampling is a requirement then you won't
even find a 12 bit device that can do it. Perhaps 10, or 8 for sure, but not
better.


/Mikhail



Article: 104999
Subject: Re: Implementing USB slow protocol into xilink XC95xxx..
From: "Andy Peters" <Bassman59a@yahoo.com>
Date: 11 Jul 2006 11:55:08 -0700
Links: << >>  << T >>  << A >>
aName wrote:
> Implementing USB slow protocol into xilink  XC95xxx..

There's no such thing as "USB slow protocol."

> I don't need long vendor string and stuff like that just the basic protocol.
>
> Is it possible ? it seems pretty complex to do ...

Forget it.  Buy a chip that does the USB stuff for you.

-a




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