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Messages from 113400

Article: 113400
Subject: Re: MPMC2: MPMC2 with DDR2 SDRAM
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Wed, 13 Dec 2006 09:14:35 +1000
Links: << >>  << T >>  << A >>
Erik Widding wrote:
> Antti wrote:
> 
>>John,
>>did you try reversing the ddr2 address bus bit endianess?
>>eg
>>A12>A0
>>..
>>A0>A12
>>
>>if the sdram address bus endianswapped then same data appears
>>on multiply location, exactly as in your case
> 
> 
> I never understood why Xilinx did this.  The JEDEC standard specifies
> fixed bit locations based on little endian ordering.  Change to a
> different size SDRAM and the width of the bus changes, so in big-endian
> format, the location also changes.  Seems like an unnecessary
> complication to the coding of the controller.  As well as the confusion
> this has caused more than one of my engineers, and customers.  I
> confess having participated in missing this detail before.

Bah!   Yes, this fixed the problem (well, got me past that problem, and onto an
easier one :)

Perhaps it's there already in some form, but the memory controller data
sheets/userguides need a big warning box with a giant exclamation mark pointing
out this little trap.

Oh well, at least I'll never fall for that one again.

Thanks Antti, Erik.

John

Article: 113401
Subject: Next Xilinx starter Kit
From: "mike" <nfinity@gmail.com>
Date: 12 Dec 2006 15:14:55 -0800
Links: << >>  << T >>  << A >>
Hello everybody !

Does someone know when the next Xilinx Starter Kit is coming out ?
I think the current one is from April.
How often do they release new starter Kits ?

Greetings,
Nicolas


Article: 113402
Subject: Re: JTAG programming of Altera Cyclone and CONF_DONE
From: "Rob" <robnstef@frontiernet.net>
Date: Wed, 13 Dec 2006 03:34:27 GMT
Links: << >>  << T >>  << A >>
Good point!  I had in my mind the enhanced configuration devices, which do 
use the JTAG pins.  Post if you find the answer--I would be interested.


"Mark McDougall" <markm@vl.com.au> wrote in message 
news:457e4d43$0$2704$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
> Rob wrote:
>
>> Perhaps having the config device in is providing enough of load to clean 
>> up
>> the signals?  Have you looked at the clock and data lines w/o the config
>> device in to see if they're clean.  I believe the standard clock rate is
>> 10MHz, pretty respectable, and needs to treated appropriately during 
>> board
>> layout.
>
> But the JTAG lines don't even go to the config devices!
>
> Regards,
>
> -- 
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266 



Article: 113403
Subject: FPGA : Async FIFO, Programmable full
From: bijoy <pbijoy@rediffmail.com>
Date: Tue, 12 Dec 2006 20:14:56 -0800
Links: << >>  << T >>  << A >>
Hi In designing asynchronous FIFOs we have to use Gray code read/write pointers.

And while using gray code I know how to generate full and empty flags.

But i would like to get ideas from experienced designers how to generate Programmable full or programmable empty flags

Thanks in advance

rgds bijoy

Article: 113404
Subject: Re: Problem with connecting higher order address lines of SDRAM to FPGA
From: "Amirtham" <amirtham@microview-tech.com>
Date: 12 Dec 2006 22:27:20 -0800
Links: << >>  << T >>  << A >>

Amirtham wrote:
> Hi Gabor,
>
> If I am not connecting A10 to SDRAM there is no problem, but if I
> connect A10 board hangs and is not even detected by the system. If
> anybody could help me get rid of this problem, please help.
>
> Thanks
> Mohni.
>
>
>
>
> Amirtham wrote:
> > "Have you tried using A9 and A11, but not A10?"
> >
> > I have only tried all A9, A10 and A11 together and not A9,A11
> > seperately.
> >
> > Thanks
> > Mohni.
> >
> > >
> > > The one thing that comes to mind is that A10 has more than one
> > > function.
> > > So if you are not generating the "AutoPrecharge" function properly
> > > during
> > > Read and Write cycles, or "SelectAllBanks" function during refresh, you
> > > can run into problems.  Have you tried using A9 and A11, but not A10?
> > > 
> > > HTH,
> > > Gabor


Article: 113405
Subject: Re: Problem with connecting higher order address lines of SDRAM to FPGA
From: Ben Jackson <ben@ben.com>
Date: Wed, 13 Dec 2006 01:38:58 -0600
Links: << >>  << T >>  << A >>
On 2006-12-08, Amirtham <amirtham@microview-tech.com> wrote:
>
> If I access SDRAM using address lines sdr_A8 to sdr_A0, I am able to
> access one row 100% correct without error. My problem starts if I
> connect sdr_A11, sdr_A10, sdr_A9. Board hangs.

Do you understand the special function of A10 for READ and WRITE commands?
What is your address logic for read and write?

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

Article: 113406
Subject: Re: RLOC weirdness
From: Andreas Ehliar <ehliar@lysator.liu.se>
Date: Wed, 13 Dec 2006 07:39:55 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2006-12-06, Ray Andraka <ray@andraka.com> wrote:
> There is another reason the RPMs will do this that is related to the 
> mapper.  The mapper has a bug that does not account for the columns 
> correctly when an RPM straddles a non-LUT column (DSP48, BRAM or 
> BRAM/MULT18 column).  The net result is it winds up causing the same 
> problem I described in my earlier post even if you have the RPM 
> constructed properly.  It is a real problem for RPMs in a V4SX family 
> part since it practically limits the size of your RPM to 4 slice columns.

I think I was bitten by both problems actually, but after making sure
that my RPM was placed on a CLB boundary and away from any non-LUT columns
the problems went away.

Thanks!

/Andreas

Article: 113407
Subject: BLVDS_25 @ SPARTAN3
From: Metin <>
Date: Wed, 13 Dec 2006 00:30:34 -0800
Links: << >>  << T >>  << A >>
Hi Folks,

I'm using the BLVDS_25 IO standard for some in/outs in a differential Bus System where the differential bus Lines outside terminated at both ends with 100 Ohm. When the Spartan3 drives the lines, I measure a Differential Voltage of about 2V in Amplitude. That means, I get 1 Volt of Differential Output Voltage from my BLVDS Pins even its specified as 250 - 450 mV in Spartan3 Datasheet. Do someone know why do i get such a high voltage?

Best Regards Metin

Article: 113408
Subject: Re: FPGA : Async FIFO, Programmable full
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 13 Dec 2006 09:25:05 -0000
Links: << >>  << T >>  << A >>
"bijoy" <pbijoy@rediffmail.com> wrote in message 
news:eea0fde.-1@webx.sUN8CHnE...
> Hi In designing asynchronous FIFOs we have to use Gray code read/write 
> pointers.
>
Well, no, you don't _HAVE_ to. You can use ordinary binary counters just 
fine, as long as you design the clock domain crossing bit properly.
>
> And while using gray code I know how to generate full and empty flags.
>
Perhaps you could share this with the V4 FIFO designers! :-) Sorry Peter!
>
> But i would like to get ideas from experienced designers how to generate 
> Programmable full or programmable empty flags
>
> Thanks in advance
>
> rgds bijoy
>
I use binary counters for my FIFOs. A Google search shows that arithmetic is 
difficult on gray coded numbers.
e.g. http://www.altera.com/literature/an/an083_01.pdf

There may well be a trick other than converting to binary, let us know if 
you find it!
HTH, Syms. 



Article: 113409
Subject: Re: Virtex4 : cleaner signals?
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 13 Dec 2006 09:33:00 -0000
Links: << >>  << T >>  << A >>
"John" <seabass950@yahoo.com> wrote in message 
news:eea0f8b.-1@webx.sUN8CHnE...
> Anyone have tips on having the Virtex 4 generate cleaner signals? I have 8 
> data lines coming out from the header IOs. They are supposed to be 3.3V 
> but the noise amplitude swing is rather big, sometimes the high signal 
> dips all the way to 2.1V.
>
> I have slew rates set to fast, drive is 12. What can I do in the FPGA to 
> improve signal quality?

Hi John,
Please don't take this the wrong way, but often if folks are just starting 
learning about SI, they also can make errors when probing the signals. Could 
you tell us how you know that the signal is doing as you say? For example, 
what 'scope setup do you have?
Austin's advice is good; Hyperlynx has a great 'scope! :-)
HTH, Syms. 



Article: 113410
Subject: Re: Question about Verilog Semantics / Xilinx Synthesis of embedded EMAC
From: "cpmetz@googlemail.com" <cpmetz@googlemail.com>
Date: 13 Dec 2006 01:58:28 -0800
Links: << >>  << T >>  << A >>
Hi,

thanks for your answer. Now it makes some sense :-) At first I thought
that this should be fully synchronous and thus covered by the timing
analysis, since the *_FALLING and *_RISING signals are fed through
DDR-flipflops to outputs. But I looked in my UCF and there it is needed
to place following timing (or: non-timing) constraints in it:

NET *rgmii_txd_falling_?_i<?> TIG;
NET *rgmii_tx_ctl_falling_?_i TIG;

Without them the design fails to meet timing and so I copied them
without much thinking from the examples. Is there the possibility to
form a bus in the UCF?

Thanks,
Christian.

<...>

> The two snippets are essentially equivalent.  My first guess would be
> that
> your project is not adequately constrained to meet timing requirements
> of transmit.  It is possible that you get a better fit by renaming the
> two
> 4-bit pieces into an 8-bit bus, due to the mapping feature of "register
> ordering", which tries to find bus structures by name and place them
> in adjacent logic elements.


Article: 113411
Subject: NOR Flash Controller
From: shareef.jalloq@lightblueoptics.com
Date: 13 Dec 2006 02:06:40 -0800
Links: << >>  << T >>  << A >>
Hi all,

I have a requirement to implement a NOR flash controller in a
Spartan-3E.  The interface will be 32-bits and will address 1GB of
flash.  This means using 16 off 512Mb components connected in 8 banks
of 2.

I understand that most designs interface the flash directly to an MCU
or CPU that controls the protocol conversion and polling etc.  In my
case the MCU is outside of the system and is only acting as a system
controller.  I have two high bandwidth datapaths from USB and to an
internal FIFO that need servicing from flash.  Ideally, these
interfaces would connect directly to a flash controller within the FPGA
with no connection to the MCU.

Can anyone point me at any IP blocks for hardware NOR flash
controllers?  Or am I going to have to bite the bullet and write it
myself.

Thanks.


Article: 113412
Subject: electrical interface problem LVPECL - LVDS multi-inputs
From: "Kurt Kaiser" <diebombeausdemwesten@freenet.de>
Date: Wed, 13 Dec 2006 11:17:59 +0100
Links: << >>  << T >>  << A >>
Hi there,

I'm currently having a serious problem: I got an LVPECL clock synthesizer 
and I want to connect it to several clock inputs on my FPGA. The FPGA 
features 2 LVDS interfaces, whereas each LVDS pair is located at opposite 
sides of the device, meaning there will be some extensive routing to do. I 
designed a resistor network for the level conversion from LVPECL to LVDS.
What I'd like to know now is
a) Can I route the 2x2 lines (two times differential to the two opposite 
sides of the FPGA) one-to-one out of my clock device to the inputs or should 
I use a dedicated buffer / repeater IC for clock distribution?
b) If clock buffer are needed, should I use LVPECL buffers and do the 
conversion to LVDS level afterwards or should I perfom the conversion before 
the buffer and then use an LVDS IC?
c) Where should I place the level conversion network? Is is better to place 
it right at the LVPECL output or is it more advisable to do it right before 
the FPGA inputs after a transmission line length of about 7 cm?
Any help, comments, advice is highly appreciated!

Thank you all very much.
Kurt 



Article: 113413
Subject: IQ multiplier
From: "ma" <ma@nowhere.com>
Date: Wed, 13 Dec 2006 10:19:35 GMT
Links: << >>  << T >>  << A >>
Hello,

       I learned that when a signal is multiplied by an IQ signal, the 
signal can be down sampled by 2. So assume that I have a signal that samples 
at 100MS and I multiplied it by an IQ signal. Then I can down sample each I 
and Q to 50MS. How is it working? Do I need a filter before down sampling? 
Or can I down sample without any filtering? Any example design that show how 
I can do this preferably in FPGA?



Best regards



Article: 113414
Subject: MicroBlaze : -mcpu=4.00.b option for mb-gcc compiler...
From: Alfmyk <alfmyk@hotmail.com>
Date: Wed, 13 Dec 2006 02:39:11 -0800
Links: << >>  << T >>  << A >>
Hi all.

I'm using ISE 8.2.03i & EDK 8.2.02i. Moreover I'm using a Spartan 3E starter Kit board for software development.

I'have seen compiling via EDK environment that now has been added this option: -mcpu=4.00.b I know it's a machine dpendent option and generally is enough add it to mb-gcc (or mb-g++) when user compile & link all together.

But in my case I have created some my makefiles with different steps of compiling and then linking.

Question: this new option -mcpu=<...> MUST be used ONLY in compiling, ONLY in linking or it's important for BOTH (link & comp.) ?

Thanks in advance for any answers.

Al.

Article: 113415
Subject: Energy consumption estimation of Virtex-4
From: "=?utf-8?B?R2FMYUt0SWtVc+KEog==?=" <taileb.mehdi@gmail.com>
Date: 13 Dec 2006 02:39:27 -0800
Links: << >>  << T >>  << A >>
Hi,
What would be the energy consumption of a V4-LX100 where 80% of the
logic is used?
About 20% of that logic is working at 400MHz and the rest at 100MHz?

Best Regards
Mehdi


Article: 113416
Subject: Re: Energy consumption estimation of Virtex-4
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 13 Dec 2006 10:55:53 -0000
Links: << >>  << T >>  << A >>
"GaLaKtIkUsT" <taileb.mehdi@gmail.com> wrote in message 
news:1166006366.929507.17030@j44g2000cwa.googlegroups.com...
> Hi,
> What would be the energy consumption of a V4-LX100 where 80% of the
> logic is used?
> About 20% of that logic is working at 400MHz and the rest at 100MHz?
>
> Best Regards
> Mehdi
>
It's impossible to answer this question unless you reveal for how long the 
device is powered on.
Cheers, Syms.

p.s. If you want to know the power consumption why not Google?

power site:xilinx.com 



Article: 113417
Subject: Re: Problem with connecting higher order address lines of SDRAM to FPGA
From: "Amirtham" <amirtham@microview-tech.com>
Date: 13 Dec 2006 03:39:39 -0800
Links: << >>  << T >>  << A >>
Thanks for your response.

I am making

1) A10 = 0 for READ and WRITE to disable AUTO-PRECHARGE since I am
using burst transfer.

2) A10 = 1 for PRECHARGE command to precharge all the banks.

Thanks!!!


Ben Jackson wrote:
> On 2006-12-08, Amirtham <amirtham@microview-tech.com> wrote:
> >
> > If I access SDRAM using address lines sdr_A8 to sdr_A0, I am able to
> > access one row 100% correct without error. My problem starts if I
> > connect sdr_A11, sdr_A10, sdr_A9. Board hangs.
>
> Do you understand the special function of A10 for READ and WRITE commands?
> What is your address logic for read and write?
> 
> -- 
> Ben Jackson AD7GD
> <ben@ben.com>
> http://www.ben.com/


Article: 113418
Subject: what are your current SoC design for ?
From: rponsard@gmail.com
Date: 13 Dec 2006 03:43:56 -0800
Links: << >>  << T >>  << A >>
I don't need your IP secrecies...

This is for my students : what, in your current design, requires using
a fpga + softcore, in place of a COTS micro controler ?
less IC -> lower footprint, lower power cons., parallelism,...

thanks,
raph


Article: 113419
Subject: Maplib Error 661.
From: "Jiten" <jitendrakumawat@gmail.com>
Date: 13 Dec 2006 03:55:26 -0800
Links: << >>  << T >>  << A >>
Hi,
I am getting this error while implementing my design with the xilinx
ise tool

Using target part "2v6000ff1152-4".
Mapping design into LUTs...
ERROR:MapLib:661 - LUT4 symbol
   "ins_part0/ins_partition_0/Partition_0_1_Multiclock_event_out127"
(output
   signal=fpga0_top_multiclock_event0_out_OBUF) has input signal
"evtDetect5"
   which will be trimmed. See the trim report for details about why the
input
   signal will become undriven.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for
more
details.  Output files will not be written.

If anybody have solved this, waiting for their positive response.
Regards
Jitendra


Article: 113420
Subject: Re: what are your current SoC design for ?
From: "Jon Beniston" <jon@beniston.com>
Date: 13 Dec 2006 04:03:12 -0800
Links: << >>  << T >>  << A >>

rponsard@gmail.com wrote:
> I don't need your IP secrecies...
>
> This is for my students : what, in your current design, requires using
> a fpga + softcore, in place of a COTS micro controler ?
> less IC -> lower footprint, lower power cons., parallelism,...

The first two.

Cheers,
Jon


Article: 113421
Subject: Re: Maplib Error 661.
From: "Jon Beniston" <jon@beniston.com>
Date: 13 Dec 2006 04:10:56 -0800
Links: << >>  << T >>  << A >>

Jiten wrote:
> Hi,
> I am getting this error while implementing my design with the xilinx
> ise tool
>
> Using target part "2v6000ff1152-4".
> Mapping design into LUTs...
> ERROR:MapLib:661 - LUT4 symbol
>    "ins_part0/ins_partition_0/Partition_0_1_Multiclock_event_out127"
> (output
>    signal=fpga0_top_multiclock_event0_out_OBUF) has input signal
> "evtDetect5"
>    which will be trimmed. See the trim report for details about why the
> input
>    signal will become undriven.
>
> Error found in mapping process, exiting...
> Errors found during the mapping phase.  Please see map report file for
> more
> details.  Output files will not be written.
>

I once saw something like this. It turned out it was due to the design
being too big for the part. Don't know if this is your problem though.

Cheers,
Jon


Article: 113422
Subject: Re: Energy consumption estimation of Virtex-4
From: "=?iso-8859-1?B?R2FMYUt0SWtVc5k=?=" <taileb.mehdi@gmail.com>
Date: 13 Dec 2006 04:15:24 -0800
Links: << >>  << T >>  << A >>
Many Thanks for your help, I downloaded from Xilinx an MS excel
spreadsheet called XPower estimator for Virtex-4:
http://www.xilinx.com/ise/power_tools/Virtex4_XPE_8_2.xls


Symon wrote:
> "GaLaKtIkUsT" <taileb.mehdi@gmail.com> wrote in message
> news:1166006366.929507.17030@j44g2000cwa.googlegroups.com...
> > Hi,
> > What would be the energy consumption of a V4-LX100 where 80% of the
> > logic is used?
> > About 20% of that logic is working at 400MHz and the rest at 100MHz?
> >
> > Best Regards
> > Mehdi
> >
> It's impossible to answer this question unless you reveal for how long the
> device is powered on.
> Cheers, Syms.
>
> p.s. If you want to know the power consumption why not Google?
> 
> power site:xilinx.com


Article: 113423
Subject: Re: Tarfessock1
From: "Nicolas Matringe" <nic_o_mat@msn.com>
Date: 13 Dec 2006 04:42:22 -0800
Links: << >>  << T >>  << A >>
John Adair a =E9crit :

> Definately on the smaller end. Here is a picture
> http://www.geograph.org.uk/photo/270797 I found.

Looks like a stone to me ... (a rather big one, I admit)
;o)

Nicolas


Article: 113424
Subject: Re: FPGA : Async FIFO, Programmable full
From: Kim Enkovaara <kim.enkovaara@iki.fi>
Date: Wed, 13 Dec 2006 14:55:17 +0200
Links: << >>  << T >>  << A >>
Symon wrote:

> "bijoy" <pbijoy@rediffmail.com> wrote in message 
> 
>>Hi In designing asynchronous FIFOs we have to use Gray code read/write 
>>pointers.
> 
> Well, no, you don't _HAVE_ to. You can use ordinary binary counters just 
> fine, as long as you design the clock domain crossing bit properly.

But crossing the clock domain with binary counter is hard to do correctly,
it needs some kind of handshake protocol. It's not enough to just put
dual flops to each counter bit like with gray coding.

--Kim



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