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Messages from 113200

Article: 113200
Subject: query regarding capacitance of pins of cyclone device
From: "ram" <vsrpkumar@rediffmail.com>
Date: 7 Dec 2006 21:14:43 -0800
Links: << >>  << T >>  << A >>
Dear friends
                    I found out input capacitance for pins of cyclone
IIEP@C20Q240C8devices
1)CIO               Input capacitance for user I/O pin
               6 pF
2)CLVDS          Input capacitance for dual-purposeLVDS/user I/O pin
  6 pF
3)CVREF          Input capacitance for dual-purposeVREF and user I/O
pin.       21 pF
4)CCLK             Input capacitance for clock pin.
                       5 pF
5)The data sheet has  not defined for pins with dual purpose pins like
DPCLK/CDPCLK/uset I/O pins
Kindly throw a light
                         How to calculate the output capacitance for
these  pins when these are connected as output pins considering the
factors like current 4mA in above cases 1,2,3,4,5


Article: 113201
Subject: FPGA : LIFO
From: bijoy <pbijoy@rediffmail.com>
Date: Thu, 7 Dec 2006 22:29:11 -0800
Links: << >>  << T >>  << A >>
Hi I wanted some help or pointers in Asynchronous LIFO design. My read and write clocks are asynchronous, I don't know how to take care of this nature of clock in a LIFO design.

I know how to implement a stack if the read and write are in the same clock domain, but not when the clocks are different.

Any suggestion or pointers will be helpful.

rgds bijoy

Article: 113202
Subject: Re: Xilinx PAR crashing with 'make'
From: Markus <none@nowhere.org>
Date: Fri, 08 Dec 2006 08:13:59 +0100
Links: << >>  << T >>  << A >>
Petter Gustad wrote:
> "johnp" <johnp3+nospam@probo.com> writes:
> 
>> If I run PAR from the command line, it runs OK.  If I use nmake or
>> wmake and my makefile,
>> it crashes.   I've opened a WebCase, but I've little hope that they
>> will resolve anything.
> 
> Could it be that you set some environment variables (including PATH)
> differently in your makefile? 
> 
> Petter
> 

I am not the original poster but that might be the case, even if not
intended. If you use a cygwin environment, several libraries and programs
are installed twice: for cygwin and xilinx ISE. So you par confuses
different library versions of perl, java, tcl and so forth.

- Markus

Article: 113203
Subject: Re: FPGA : LIFO
From: "Thomas Stanka" <usenet_10@stanka-web.de>
Date: 7 Dec 2006 23:22:56 -0800
Links: << >>  << T >>  << A >>
Hi,

bijoy schrieb:
> Hi I wanted some help or pointers in Asynchronous LIFO design. My read and write clocks are asynchronous, I don't know how to take care of this nature of clock in a LIFO design.
>
> I know how to implement a stack if the read and write are in the same clock domain, but not when the clocks are different.
>
> Any suggestion or pointers will be helpful.

A general asynchronous LIFO seems impossible to me. You need to have
some constraints to enable a LIFO to be asynchron read and write, as
all operations occure on the the same register.  This means you should
transfer your LIFO in one clock domain aand manage the domain crossing
outside the LIFO.

Many vendors provide you a build in FIFO or at least a  soft core for a
asynchronous FIFO.
Why not using this FIFO to cross the clock domains and build a synchon
LIFO.  

bye Thomas


Article: 113204
Subject: Re: Microblaze LMB bus
From: "Göran Bilski" <goran.bilski@xilinx.com>
Date: Fri, 8 Dec 2006 08:41:43 +0100
Links: << >>  << T >>  << A >>
Hi,

The way uses MicroBlaze is different on the instruction side compared to the 
data side, at least for v4.
For v5 the usage is the same.

V4 instruction side.
MicroBlaze will just send out the address on one clock cycle and the next 
address will come directly after independent if there is a ready or not.
Normally this is called overlapped address and data phases on the bus.
When the LMb slave returns the ready signal, Microblaze will combinatorial 
drive a new Adress strobe. The new address is already on the bus as explain 
above.

V4 Data side.
MicroBlaze will on recieving the ready signal NOT combinatorial drive the 
new address strobe but that will happen the nextr clock cycle.
The address and data phase do not overlapped.

On V5, the instruction side and data side is the same and they uses the same 
protocol as the V4 instruction side.

The reason for this behaviour is due to the internal pipeline which differ 
from v4 to v5.

Göran Bilski

"Muralidaran Vijayaraghavan" <vmurali@mit.edu> wrote in message 
news:4578d31e$0$562$b45e6eb0@senator-bedfellow.mit.edu...
>I finally checked what happens when using an LMB with microblaze. Looks 
>like it is waits for a ready in the bus as the programs hang if they 
>contain a load/store. So now my question is: how does the microblaze issue 
>the next load/store when the first is in flight (according to the timing 
>diagram in the spec). Does it issue a maximum of two instructions before 
>looking at the ready? Checking this involves more work, so I would be 
>happier if someone knows and can tell :)
>
> Thanks
> Murali 



Article: 113205
Subject: Problem with connecting higher order address lines of SDRAM to FPGA
From: "Amirtham" <amirtham@microview-tech.com>
Date: 8 Dec 2006 00:31:00 -0800
Links: << >>  << T >>  << A >>
Hi
I have done a SDRAM controller design in spartan. using Micron
SDRAM(128Mx32 with 4 banks).

If I access SDRAM using address lines sdr_A8 to sdr_A0, I am able to
access one row 100% correct without error. My problem starts if I
connect sdr_A11, sdr_A10, sdr_A9. Board hangs. I am not able to detect
the board. Some how I used a tristate buffer for sdr_A10 (which is not
the way to do so, but still I just gave a try)  to precharge the rows,
obviously I am not reading correct data from few rows since I have not
connected sdr_A11 and sdr_A9. Using tirstate buffers for these llines
also didn't help.
I couln't trace where the problem could be. If anyone came accross such
problem anywhere in your design experience (not neccessarily in SDRAM)
Please help me.

Thanks
Mohni.


Article: 113206
Subject: About Unstable Operation of ACTEL(A3P1000)....
From: "kypilop" <kypilop@gmail.com>
Date: 8 Dec 2006 00:48:46 -0800
Links: << >>  << T >>  << A >>
Hi..
I can't understand about this situation....
I use same source(VHDL), same program tool(Libero), same
device(A3P1000) and same programmer(FlashPro3)....But the device
operation is not regular....
I test some functions using StartKit from Actel Co.
Many times, parts of function are un-operation....
The un-operated functions are not fixed !!! Malfunctions are
irregular.....................
Also, the source of VHDL had been verified in Altera device
(EPF10K100ARC240)
In Altera, all functions are operated correctly...........
Always, Actel's programmer said "Verifying Passed"....Is that true????
Plz, help me.... I lost self control using Actel's device.... Help me,
Help me


Article: 113207
Subject: Re: Recursive component instantiation
From: Patrik Eriksson <no-replay@dummy.com>
Date: Fri, 08 Dec 2006 10:16:10 +0100
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> googlinggoogler@hotmail.com wrote:
> 
>> I don't wish to hijack your thread, but what would you use recursive
>> component instantiation for? are you instantiating within an
>> instantiation?
>>
>> Cheers
>>
>> david
>>
> 
> Sometimes a parameterized component is easiest to generate with 
> recursion.  For example an adder tree can be generated by recursively 
> calling a component that adds two vectors.
> 
> 
Thank you all for the answers.

The example with a parameterized component is exactly what I have 
designed. I have a generic component that implement the looping 
algorithm used to calculate the configuration bits for a Benés network 
with a generic number of ports. The lowest level is for a 4-port Benés 
network. For each hierarchal level the number of ports are doubled. I 
have simulated my code in modelsim and it have the correct behavior but 
in synthesis I get a width mismatch for one of the output ports. 
Unfortunately no figures of the different widths are printed by synplify 
so I can't know at which level the error occurs. But from your answers I 
now know that synplify should fix this. Maybe it could be a problem with 
how generics are handled (global or local?)

Thanks again!

Cheers
Patrik

Article: 113208
Subject: source synchronous timing (Xilinx)
From: "Dolphin" <Karel.Deprez@gemidis.be>
Date: 8 Dec 2006 01:19:07 -0800
Links: << >>  << T >>  << A >>
Hello,

I am trying to constrain a source synchronous input to a Spartan 3E
FPGA.
On the website:
http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0042_7.html
I found an examples for source synchronous timing constraints.

The thing that I don't understand is the constraint for the falling
edge:

TIMEGRP DATA_IN OFFSET IN = 4 VALID 3 BEFORE CLK TIMEGRP FF_FALLING;

Why do they use 4 ns in this example? I can't relate it to the timing
diagram that is shown.

thanks and best regards,
Karel


Article: 113209
Subject: Organization of character bit maps
From: "ALuPin@web.de" <ALuPin@web.de>
Date: 8 Dec 2006 02:32:42 -0800
Links: << >>  << T >>  << A >>
Hi,

I want to design a character generator.

Using Lattice XP EBR blocks I have the following architecture of the
RAM blocks
available:

8192bit =3D 36bit * 256

Now I want to store ASCII characters with following dimensions:
12bit wide, 18bit high

When trying to display characters arranged successively what
organization of characters in RAM would be reasonable ?

I can think of two possible alternatives:

a)

1 .....  36
C0  C0  ...... C0
C0  C0  .....  C0
C0  C0  ...... C0
C0  C0  ...... C0
C0  C0  ...... C0
C0  C0  ...... C0

Rgds
Andr=E9
C1  C1  .......C1
.=2E.

1 ...12  13 ... 24  25 ... 36
C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0  C1 ... C1 C2 ... C2
C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0  C1 ... C1 C2 ... C2
C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0  C1 ... C1 C2 ... C2
.=2E.
C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0  C1 ... C1 C2 ... C2


Article: 113210
Subject: Re: About Unstable Operation of ACTEL(A3P1000)....
From: Alan Myler <amyler@eircom.net>
Date: Fri, 08 Dec 2006 11:16:34 +0000
Links: << >>  << T >>  << A >>
kypilop wrote:

> Hi..
> I can't understand about this situation....
> I use same source(VHDL), same program tool(Libero), same
> device(A3P1000) and same programmer(FlashPro3)....But the device
> operation is not regular....
> I test some functions using StartKit from Actel Co.
> Many times, parts of function are un-operation....
> The un-operated functions are not fixed !!! Malfunctions are
> irregular.....................
> Also, the source of VHDL had been verified in Altera device
> (EPF10K100ARC240)
> In Altera, all functions are operated correctly...........
> Always, Actel's programmer said "Verifying Passed"....Is that true????
> Plz, help me.... I lost self control using Actel's device.... Help me,
> Help me
> 


You are not giving enough information about your board, about your 
design, about the tool versions, about the VHDL, about the timing 
constraints etc etc etc.

If you want people to help you then you really need to learn how to ask 
meaningful questions.

All those !!! and ??? and .... don't help :-)


Article: 113211
Subject: Looking for simple Cycone 2 example design
From: Mike Harrison <mike@whitewing.co.uk>
Date: Fri, 08 Dec 2006 12:15:22 GMT
Links: << >>  << T >>  << A >>
I'm looking for a complete project  containing a minimal VHDL design for the Cyclone II, preferably
2C35 or similar to have a play around with with prior to getting hold of a real board for an
upcoming proiject  - the sort of thing that usually comes with a low-end devboard to flash a few
LEDs etc. 
Can't find anything at Altera for this family.
If <5MB, please email to mike@whitewing.co.uk, thanks.

Article: 113212
Subject: Re: Organization of character bit maps
From: "ALuPin@web.de" <ALuPin@web.de>
Date: 8 Dec 2006 04:15:49 -0800
Links: << >>  << T >>  << A >>
Trying again:

a)


1 .....  36
C0  C0  ...... C0
C0  C0  .....  C0
C0  C0  ...... C0
C0  C0  ...... C0
C0  C0  ...... C0
C0  C0  ...... C0
C1  C1  .......C1
.=2E.

b)

1 ...12  13 ... 24  25 ... 36
C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0  C1 ... C1 C2 ... C2
C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0  C1 ... C1 C2 ... C2
C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0  C1 ... C1 C2 ... C2
.=2E.
C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0  C1 ... C1 C2 ... C2

Rgds
Andr=E9


Article: 113213
Subject: Re: Recursive component instantiation
From: "acd" <acd4usenet@lycos.de>
Date: 8 Dec 2006 05:02:24 -0800
Links: << >>  << T >>  << A >>

Ray Andraka wrote:
> Sometimes a parameterized component is easiest to generate with
> recursion.  For example an adder tree can be generated by recursively
> calling a component that adds two vectors.

I also like recursion in HW design, and used exactly the population
count
with a long vector as an educational example.

However I think that even in that case it is better to use flat
instantiation and
recursive functions to calculate the parameters (adder sizes), indexes
for the
connections of the ports and so on.

In many tools recursive instantiation has  the consequence of very long
unreadable
signal and component names in the netlist.
This makes pattern matching etc. in floorplanning, timing analysis etc.
harder.
By using recursive functions and flat instantiation one gets both,
clarity and
easy handling.
In both cases it would be nice to have a standardized way to control
the naming of
instantiated primitives (such as adders or registers). 

Andreas


Article: 113214
Subject: Re: About Unstable Operation of ACTEL(A3P1000)....
From: "kypilop" <kypilop@gmail.com>
Date: 8 Dec 2006 06:37:21 -0800
Links: << >>  << T >>  << A >>
Hi~
I'm sorry...

The board is A3PE-A3P-EVAL-BRD1 REV3 which is manufactured by Actel Co.
This board has expantion port for I/O, some LEDs, 1 LCD and regulators,
just simple design.

Libero version is 7.2
FlashPro Program version is 4.2
Synflify version is 8.1 for Actel

The tested VHDL source has function of serial communication(UART).
And always, LED blink correctly in VHDL source
But serial communication function operates unregular
Sometimes Reciever operates well, But Transmitter is not.
Sometimes Transmitter operates well, But Reciever is not.
X-tal is 11.0592MHz and operates correctly.
Supply voltage is 3.3V for I/O which supplied by Application board from
Actel
As I know, TTL level can adapt CMOS 3.3V
Power ground was one point.
And I use RS232 to USB converter, but they operate well. Self test
passed.

I don't know well about timing constraints which is default option.
But palce&router of Actel said satisfying the timing constraint.

Are U want any informations? Plz, let me know.. I'm beginner of FPGA..
:-)
Are there some options or parameters to consider for palce&route ?
Thx to Alan Myler for your advice :-)

Alan Myler =C0=DB=BC=BA:
>
> You are not giving enough information about your board, about your
> design, about the tool versions, about the VHDL, about the timing
> constraints etc etc etc.
>
> If you want people to help you then you really need to learn how to ask
> meaningful questions.
>=20
> All those !!! and ??? and .... don't help :-)


Article: 113215
Subject: Re: Firmware for Xilinx USB cable
From: mark.jarvin@gmail.com
Date: 8 Dec 2006 06:38:57 -0800
Links: << >>  << T >>  << A >>
Eric Smith wrote:
> It may have moved; it now seems to be at:
> ftp://ftp.xilinx.com/pub/utilities/fpga/install_drivers.tar.gz

Thanks -- I had updated my erroneous post with a reply, but I guess it
bears repeating.

Also, it turned out that my USB cable was broken but that the drivers
were working.  Now that I've tried with working cable, count me as a
second successful user of the new drivers (both the Parallel IV and the
Platform USB, tested and working on Xubuntu Edgy i386). I'm using the
Jungo 802 distributed by Xilinx and patched as described previously,
not the latest Jungo 811.  I haven't yet tried the 64-bit version.

Based on what I observed, the "CPLD Version = FFFFh" message seems to
indicate a broken cable whereas the "CPLD Version = 0000h" message
seems to indicate a driver problem that's (presumably) fixed by the
1025 firmware.

I also observed something else a little weird.  Since my environment
doesn't use hotplug, I shouldn't need to run the setup_pcusb script and
so I didn't.  I found that programming from within EDK worked but that
programming from iMPACT directly didn't -- it gave me an error and told
me to run setup_pcusb.  Same for XMD -- it wouldn't connect unless
setup_pcusb had been run.  I eventually found that iMPACT and XMD look
for some side-effect of running setup_pcusb and refuse to proceed until
setup_pcusb has been run (as root).  If you run iMPACT as root, it'll
run setup_pcusb for you (though you can obviously run it from the
terminal, too).  Once setup_pcusb had been run, I found that any user
could program from EDK or directly from iMPACT (with appropriate
permissions on the /dev nodes).  XMD worked for any user, too.  I
speculate that it was failing because the firmware .hex file wasn't in
/etc/hotplug.

The lesson: if you do a fresh install of ISE and EDK (or just ISE) and
you install the drivers from the Xilinx website, don't forget to also
run setup_pcusb even if it won't do anything useful in your
environment.  EDK must use some environment variable or flag that gets
around this -- anybody know what it might be?


Article: 113216
Subject: Re: Problem with connecting higher order address lines of SDRAM to FPGA
From: "Gabor" <gabor@alacron.com>
Date: 8 Dec 2006 07:16:56 -0800
Links: << >>  << T >>  << A >>

Amirtham wrote:
> Hi
> I have done a SDRAM controller design in spartan. using Micron
> SDRAM(128Mx32 with 4 banks).
>
> If I access SDRAM using address lines sdr_A8 to sdr_A0, I am able to
> access one row 100% correct without error. My problem starts if I
> connect sdr_A11, sdr_A10, sdr_A9. Board hangs. I am not able to detect
> the board. Some how I used a tristate buffer for sdr_A10 (which is not
> the way to do so, but still I just gave a try)  to precharge the rows,
> obviously I am not reading correct data from few rows since I have not
> connected sdr_A11 and sdr_A9. Using tirstate buffers for these llines
> also didn't help.
> I couln't trace where the problem could be. If anyone came accross such
> problem anywhere in your design experience (not neccessarily in SDRAM)
> Please help me.
>
> Thanks
> Mohni.

The one thing that comes to mind is that A10 has more than one
function.
So if you are not generating the "AutoPrecharge" function properly
during
Read and Write cycles, or "SelectAllBanks" function during refresh, you
can run into problems.  Have you tried using A9 and A11, but not A10?

HTH,
Gabor


Article: 113217
Subject: Re: About partial reconfiguration in Virtex 4
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 08 Dec 2006 07:54:06 -0800
Links: << >>  << T >>  << A >>
Perry,

Only those blocks that have a dynamic reconfiguration port (DRP) interface.

We standardized on the DRP so that any block that wanted to provide the
feature should follow the same interface (a bit like creating an
internal bus architecture for blocks that need reconfiguration).

At this time, the DCM, the MGT, and the System Monitor all have DRP.
There may be more, but you may go to the user's guide, and look at each
block (PPC, EMAC, PCIe, etc.) to see if they use DRP, or if they have a
set of registers that are part of the fabric access (or both).

Austin


Perry wrote:
> Hi all,
> It seems that run-time reconfigurations are only available in DCM and
> RocketIO blocks.
> Concerning about partial reconfiguration, can every functional block be
> partially reconfiged?
> thanks
> 

Article: 113218
Subject: Re: RTL Hardware design issue: Count Leading Zeros CLZ
From: Ray Andraka <ray@andraka.com>
Date: Fri, 08 Dec 2006 11:12:08 -0500
Links: << >>  << T >>  << A >>
davidc@ad-holdings.co.uk wrote:
> Thanks for the info guys it's starting to make sense.
> 
> On Dec 7, 6:49 pm, Ray Andraka <r...@andraka.com> wrote:
> 
>>dav...@ad-holdings.co.uk wrote:
>>
>>>Hi,
>>
>>>I'm trying to create a Count Leading Zero (CLZ) in VHDL for a project
>>>but i'm having difficulty in finding any information what so ever apart
>>>from an explanation as to what it does, can anyone help?
>>
>>>Can anyone explain what logic would be required to create a CLZ, i've
>>>only found one point of reference on the web which uses a number of
>>>nested multiplexers with the output of one being fed back into the
>>>select line of the next. Any information regarding the hardware/ schema
>>>would be greatly appreciated.
>>
>>>Thanks, DaveThe best way depends on what you intend to do with the count.  If it
>>
>>will be used to left-justify the data,
> 
> 
> There is no practicle intention, it's more of an exercise to understand
> how it works, so i'm mearly try to count the number of leading zeros
> starting at the most significant bit.
> 
> 
>>then the best approach is to use
>>a series of 2:1 muxes with each layer controlled by the previous layer's
>>output.
> 
> 
> Similar to the CLZ diagram in the link provided by Andy above:
> 
> http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/Flottan.htm
> 
> The diagram in the following link uses muxes, but they have multiple
> outputs why is this? or are they adders in the diagram?
> 
> 
>>The control function is easiest if you use sign-magnitude
>>notation rather than two's complement, since that makes it strictly
>>leading zeros rather than redundant sign.  The mux on the last layer
>>shifts by 1 bit or passes unchanged, the previous layer by 2 bits or
>>unchanged, the one before that 4 bits or unchanged and so on.  The
>>select decision for each layer forms 1 bit of the leading zero count,
>>which is the same as the number of positions the data was shifted left.
>>
> 
> 
> OK, so the output of each mux is fed into the "next layer's" input mux
> and in addition to this the select line SEL forms the total output of
> the circuit.
> 
> So if I had an 8 bit input, the output would be 4 bits. so on the first
> layer which is uses 2 bit muxes on the input, for an 8 bit CLZ the
> first layer would have 4 SEL lines, are these just connect together to
> form the first bit of the output?
> 
> something like:
> 
>  0   1              2   3          4   5             6   7
>  |    |                |    |          |    |              |    |
> --------   S        --------  S    --------   S       --------  S
> |       |----|        |      |----|    |       |----|       |
> |----|            2's
> --------             --------         --------           --------
>     |                  |
>     |_____    ___|
>              |    |
>             --------
>             |       |
>             4's
>             --------
> 
> I this instance for output bit 0 all the "S" would be connected
> together, is this coreect?
> 
> Is there any additional digital circuity required or is it all done
> using muxes and "not" gates for the inputs.
> 
> Is there any way of doing this using Karnaugh maps, i've had experience
> before with them, but where would I start on something like this?
> 
> Thanks,
> Dave
> 
> 
>>If, on the other hand, you are not also shifting the data, then you need
>>some form of priority encoder to encode the position of the first 1.
>>The Xilinx 4000 series was nice for this because the carry chain could
>>go up or down the chip, so you could set it up to propagate down and use
>>it as a first '1' detect (a one-hot signal), which is very easy to
>>encode into a leading zero count without having to propagate a 'carry'
>>in the encoder.
> 
> 

David, close but not quite.

Let's consider a 16 bit input.  You can have from 0 to 16 leading 0's 
(16 leading zeros is a special case, it is 15 where the data is also 0). 
  In this case we shift left 0 to 15 places, left shifting if all the 
leading bits for that shift are '0'.  This is done with 4 layers of 2:1 
muxes shifting by 8,4,2 and then 1 bits.  Each layer's shift select is 
the logical OR of the left N bits (N=8,4,2 and 1) so that a shift only 
occurs if all those left bits are 0.

lyr8 <= din(7 downto 0) & X"00" when din(15 downto 8)=X"00" else din;
sout(3) <= '1' when din(15 downto 8)=X"00" else '0';
lyr4 <= lyr8(11 downto 0) & X"0" when lyr8(15 downto 12)=X"0" else lyr8;
sout(2) <= '1' when lyr8(15 downto 12)=X"0" else '0';
lyr2 <= lyr4(13 downto 0) &"00" when lyr4(15 downto 14)="00" else lyr4;
sout(1) <= '1' when lyr4(15 downto 14)="00" else '0';
dout <= lyr2(14 downto 0) & '0' when lyr2(15)='0' else lyr2;
sout(0) <= '1' when lyr2(15)='0' else '0';

This works if din is unsigned because you only have leading '0's.  If 
din is 2's complement data, then you have leading sign bits instead of
leading '0', so the detection at each stage is made more difficult; in 
that case it has to see if all the bits that will get shifted out match 
the leftmost retained bit instead of just being zero so the detect 
function has an additional term:  when din(15 downto 7)="000000000" or 
din(15 downto 7)="111111111";  This precludes some shortcuts like using 
the carry chain to perform the detect.  It is often easier to convert 
from 2's complement notation to sign-magnitude notation, which is an 
unsigned magnitude plus an independent sign bit.  The conversion is done 
by performing the 2's complement if the 2's complement input is negative 
to get an unsigned magnitude, and then retaining the sign bit.  (this 
description is to answer a question posed by email).









Article: 113219
Subject: Re: LVDS output pins of Altera Cyclone II
From: tentacle (onlyspam@online.ms)
Date: Fri, 08 Dec 2006 17:12:37 +0100
Links: << >>  << T >>  << A >>
>tentacle (onlyspam@online.ms) wrote:
>
>> I'm trying to use a FPGA to control a flat panel display that has LVDS
>> inputs. Displays try to draw current from active LVDS lines if the power
>> supply of the panel is switched off.
>> 
>> That is very harmful for the TFT and sooner or later it gets destroyed.
>> 
>> That is why I have to tri-state the LVDS outputs.
>
>Didn't know that
>
>> Every LVDS driver IC on the market has an "output enable" signal. So why
>> shouldn't this be possible with an FPGA?
>
>Well, I know that a lot of Philips TFT panels are driven by a Cyclone II,
>but then again, these Cyclones get their current from the same supply as
>the panel so the TFT can try to draw current until it hurts, but the
>Cyclone will have nothing to give ;-)
>
>Alternatively you could use SSTL2, which basically has the same electrical
>characteristics but is available as a bidirectional IO buffer. Setting OE
>to 0 in this mode would effectively tristate the buffer. Drive strength is
>limited to 15mA though.
>
>Best regards,
>
>Ben

Hi,

thanks for the tip. I wrote my own serializer IP which uses the DDIOs as output stages and 
tristating the buffer works fine.

Best regards,
Simon


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Article: 113220
Subject: Re: Clock phase shift
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Fri, 08 Dec 2006 11:23:05 -0500
Links: << >>  << T >>  << A >>
Frank Buss wrote:
> Alan Myler wrote:
> 
>> Use an inverter?
> 
> I don't think this will result in an exact 180 shifted signal at 100 MHz,
> because of the delay of the inverter, so using a DCM is a good idea.
> 

Aren't clocks on V4 already routed differentially?

In that case, putting an inverter should simply instruct the synthesis 
tools to use the clockN net instead of clockP for the affected regional 
clock buffers. Alternatively, clockP can be used but FFs will absorb the 
inverter and clock on negedge instead.

An inverter in VHDL does not necessarily translate into extra logic 
after synthesis... most inverters get absorbed somewhere, somehow.

Article: 113221
Subject: Re: RTL Hardware design issue: Count Leading Zeros CLZ
From: davidc@ad-holdings.co.uk
Date: 8 Dec 2006 09:09:57 -0800
Links: << >>  << T >>  << A >>

>
> Let's consider a 16 bit input.  You can have from 0 to 16 leading 0's
> (16 leading zeros is a special case, it is 15 where the data is also 0).
>   In this case we shift left 0 to 15 places, left shifting if all the
> leading bits for that shift are '0'.  This is done with 4 layers of 2:1
> muxes shifting by 8,4,2 and then 1 bits.  Each layer's shift select is
> the logical OR of the left N bits (N=8,4,2 and 1) so that a shift only
> occurs if all those left bits are 0.



OK, so the "top" layer has 8 x 2-1 muxes for a 16 bit input (A0-A15),
the select line for each are connected together
by a logical OR function, the inputs of which are the left N bits - so
in this case would the inputs to the OR gate be A15-A8 or is it
"A1, A3, A5, A7, A9, A11, A13, and A15" which are all OR'd together and
the output goes to each select line SEL for
that particular layer?


>
> lyr8 <= din(7 downto 0) & X"00" when din(15 downto 8)=X"00" else din;
> sout(3) <= '1' when din(15 downto 8)=X"00" else '0';
> lyr4 <= lyr8(11 downto 0) & X"0" when lyr8(15 downto 12)=X"0" else lyr8;
> sout(2) <= '1' when lyr8(15 downto 12)=X"0" else '0';
> lyr2 <= lyr4(13 downto 0) &"00" when lyr4(15 downto 14)="00" else lyr4;
> sout(1) <= '1' when lyr4(15 downto 14)="00" else '0';
> dout <= lyr2(14 downto 0) & '0' when lyr2(15)='0' else lyr2;
> sout(0) <= '1' when lyr2(15)='0' else '0';
>
> This works if din is unsigned because you only have leading '0's.  If
> din is 2's complement data, then you have leading sign bits instead of
> leading '0', so the detection at each stage is made more difficult; in
> that case it has to see if all the bits that will get shifted out match
> the leftmost retained bit instead of just being zero so the detect
> function has an additional term:  when din(15 downto 7)="000000000" or
> din(15 downto 7)="111111111";  This precludes some shortcuts like using
> the carry chain to perform the detect.  It is often easier to convert
> from 2's complement notation to sign-magnitude notation, which is an
> unsigned magnitude plus an independent sign bit.  The conversion is done
> by performing the 2's complement if the 2's complement input is negative
> to get an unsigned magnitude, and then retaining the sign bit.  (this
> description is to answer a question posed by email).

I understand what you mean as negative numbers have a "1" at the most
significant bit which will give a 0 for the CLZ. I think i'll leave the
2's compliment for now ;D

Thanks


Article: 113222
Subject: Implementing DVI EDID on Stratix II GX?
From: "jjlindula@hotmail.com" <jjlindula@hotmail.com>
Date: 8 Dec 2006 09:34:00 -0800
Links: << >>  << T >>  << A >>
Hello, I have a project which will require a DVI output and was
wondering if it is possible to have the FPGA do the DVI EDID? If anyone
has some experience with the EDID I would like to hear your thoughts.
Thanks,
joe


Article: 113223
Subject: Re: source synchronous timing (Xilinx)
From: "Jim Wu" <jimwu88NOOOSPAM@yahoo.com>
Date: 8 Dec 2006 10:39:48 -0800
Links: << >>  << T >>  << A >>
That's probably a typo. The latest PDF guide below shows that it is -4
(note the negative sign).

http://toolbox.xilinx.com/docsan/xilinx82/books/docs/cgd/cgd.pdf

Cheers,
Jim
http://home.comcast.net/~jimwu88/tools/

Dolphin wrote:
> Hello,
>
> I am trying to constrain a source synchronous input to a Spartan 3E
> FPGA.
> On the website:
> http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0042_7.html
> I found an examples for source synchronous timing constraints.
>
> The thing that I don't understand is the constraint for the falling
> edge:
>
> TIMEGRP DATA_IN OFFSET IN = 4 VALID 3 BEFORE CLK TIMEGRP FF_FALLING;
>
> Why do they use 4 ns in this example? I can't relate it to the timing
> diagram that is shown.
> 
> thanks and best regards,
> Karel


Article: 113224
Subject: Re: Implementing DVI EDID on Stratix II GX?
From: yttrium <yttrium@telenet.be>
Date: Fri, 08 Dec 2006 19:48:01 +0100
Links: << >>  << T >>  << A >>
jjlindula@hotmail.com wrote:
> Hello, I have a project which will require a DVI output and was
> wondering if it is possible to have the FPGA do the DVI EDID? If anyone
> has some experience with the EDID I would like to hear your thoughts.
> Thanks,
> joe
> 

since EDID is just a I2C PROM with data for the graphics card, i think 
it is possible to do it in an FPGA with an I2C slave core and some 
memory attached to it ... DDC = 5V I2C so be carefull how to attach it 
to the FPGA ...

i think it is possible ... just be very carefull if you want an dynamic 
EDID PROM value, those can be very tricky ... then you would also need 
an HPD (Hot Plug Detect) logic...



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