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Messages from 113775

Article: 113775
Subject: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
From: "Marco T." <mmm@mmm.com>
Date: Thu, 21 Dec 2006 07:55:40 +0100
Links: << >>  << T >>  << A >>

"Pablo" <pbantunez@gmail.com> ha scritto nel messaggio 
news:1166629886.453702.17780@n67g2000cwd.googlegroups.com...
> Has anybody tried to write a code for crontroling what you put in a VGA
> port?? I have a Spartan 3E, and I want to put an image in a monitor.
> I've created a XPS project with Microblaze and OPB bus, and I've
> incorporated the VGA Peripheral. Finally I send the pixel values from a
> C program but there is a problem: The communication is too slow. I
> can't view a quiet image.
>
> Can anybody tell me how can I write a project to print an image into
> the VGA?. I soppuse I could write a code to access to the sdram, but I
> don't know how can I get it.
>
> Thanks, Pablo
>

You could use the multiport memory controller.

http://direct.xilinx.com/bvdocs/appnotes/xapp909.pdf

http://direct.xilinx.com/bvdocs/appnotes/xapp912.pdf

Marco 



Article: 113776
Subject: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
From: "Marco T." <mmm@mmm.com>
Date: Thu, 21 Dec 2006 07:57:00 +0100
Links: << >>  << T >>  << A >>

"Antti" <Antti.Lukats@xilant.com> ha scritto nel messaggio 
news:1166635041.824034.325330@n67g2000cwd.googlegroups.com...
> Pablo schrieb:
>
>> Has anybody tried to write a code for crontroling what you put in a VGA
>> port?? I have a Spartan 3E, and I want to put an image in a monitor.
>> I've created a XPS project with Microblaze and OPB bus, and I've
>> incorporated the VGA Peripheral. Finally I send the pixel values from a
>> C program but there is a problem: The communication is too slow. I
>> can't view a quiet image.
>>
>> Can anybody tell me how can I write a project to print an image into
>> the VGA?. I soppuse I could write a code to access to the sdram, but I
>> don't know how can I get it.
>>
>> Thanks, Pablo
>
> 1 add PLB bus
> 2 put the sdram controller on PLB bus
> 3 add xilinx VGA or TFT or DVI core (attaches to PLB bus)
> 4 add PLB2OPB bridge
> 5 connect the PLB2OPB bridge to your OPB bus
>
> done.
> works.
>
> antti
>

Could you tell me which application has the plb_dvi controller?

Many Thanks
Marco 



Article: 113777
Subject: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
From: "Antti" <Antti.Lukats@xilant.com>
Date: 20 Dec 2006 23:50:47 -0800
Links: << >>  << T >>  << A >>
Marco T. schrieb:
> Could you tell me which application has the plb_dvi controller?
>
> Many Thanks
> Marco

MPMC2, look at refcores, there it is !

Antti
http://www.microfpga.com


Article: 113778
Subject: Embedded Development Tools
From: "Andy" <ezembedded@gmail.com>
Date: 21 Dec 2006 00:28:02 -0800
Links: << >>  << T >>  << A >>
Hello,

Here is our web site www.ezEmbedded.com for your reference and I am
very happy to assist you on your project. Please feel free to contact
me for your any question about our products as well as service.

Best Regards,

Andy
The EZ EMBEDDED Team
www.ezEmbedded.com
info@ezEmbedded.com


Article: 113779
Subject: Re: A nice CIC-Filter, but I can't find the result in the bitsequence!?
From: "bg" <b.gascho@procitec.de>
Date: 21 Dec 2006 01:19:35 -0800
Links: << >>  << T >>  << A >>
Thanks a lot. I knew it would be quite simple, but I couldn't see it.


Article: 113780
Subject: Re: New user help required
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 21 Dec 2006 10:17:13 -0000
Links: << >>  << T >>  << A >>
"Karen Halgren" <khal@yahoo.com> wrote in message 
news:4589b270$1_3@mk-nntp-2.news.uk.tiscali.com...
>> > Where do I find the schematic diagram of the
>> > xilinx xc9536 which indicate power/gnd, io
>> > pins, and jtag pins?
>>
>> http://www.xilinx.com
>>
>
> Hi Jon, thanks for your reply,
> I had a look in xilinx.com but could not find which
> datasheet carrys the schematic of the package, I know
> it's a PLCC configuration, but need to know which pins
> are which if you know what I mean. Any suggestions?
>
>
Hi Karen,
I've a suggestion, if you're gonna get anywhere with FPGAs, you wanna learn 
how to use a search engine. This one seems popular:-

http://www.google.com/advanced_search

In shorthand, Google this:-

package site:xilinx.com

HTH, Syms. 



Article: 113781
Subject: XILKERNEL and MICROBLAZE (how to probe this)
From: "Pablo" <pbantunez@gmail.com>
Date: 21 Dec 2006 03:08:44 -0800
Links: << >>  << T >>  << A >>
Has somebody tried to config Xilkernel with the XPS. I have a Spartan
3E and XPS 8.1, and I've added Xilkernel with an opb_timer. Now I want
to probe this and I write a C program with "xil_printf". This is OK,
but I want to do something with the kernel, so I write xilkernel_main
(I don't know what this means but i try). The problem is:

region ilmb_cntlr_dlmb_cntlr is full
region ilmb_cntlr_dlmb_cntlr is full
error in function xilkernel init
..... (quite a lot)

Can anyone tell me about a manual or something to probe "threads" or
something with xilkernel?. And How do you configure "Software Platform
Settings".

Thanks


Article: 113782
Subject: Re: XILKERNEL and MICROBLAZE (how to probe this)
From: "Jon Beniston" <jon@beniston.com>
Date: 21 Dec 2006 03:44:02 -0800
Links: << >>  << T >>  << A >>

Pablo wrote:
> Has somebody tried to config Xilkernel with the XPS. I have a Spartan
> 3E and XPS 8.1, and I've added Xilkernel with an opb_timer. Now I want
> to probe this and I write a C program with "xil_printf". This is OK,
> but I want to do something with the kernel, so I write xilkernel_main
> (I don't know what this means but i try). The problem is:
>
> region ilmb_cntlr_dlmb_cntlr is full
> region ilmb_cntlr_dlmb_cntlr is full
> error in function xilkernel init
> ..... (quite a lot)
>
> Can anyone tell me about a manual or something to probe "threads" or
> something with xilkernel?. And How do you configure "Software Platform
> Settings".

Do you have external memory? Sounds like you are trying to place all
your code in on chip RAM, but the memory is too small. If you have
external memory, create a custom link script that places the code
there.

Cheers,
Jon


Article: 113783
Subject: Re: ANN: PicoBlaze C: compile to bitstream!
From: "spartan3wiz" <magnus.wedmark@gmail.com>
Date: 21 Dec 2006 06:08:54 -0800
Links: << >>  << T >>  << A >>
Hi Antti,

I like what you have done and are trying to do with MicroFPGA. Nice
idea!

I downloaded your MicroFPGA test-package but I can't get it working
correctly. As I understand the clock used are created by some kind of
internal DDS of something? Can you explain this further?  Can this give
problems with differnet circuits?

I tried out both the build.bat for the assembler-example and the
build.bat for the C-example. Both of them create a download.bit but
when downloading them using Impact no LED is blinking.

I use:
Windows XP
Spartan3-Starter Kit 200K from Digilent and also pointed out both the
correct circuit
(xc3s200_ft256) AND the correct board (digilent\s3sk)
ISE v8.1 - Impact for download, and the standard Parallell-JTAG cable
that came with the kit!

I also changed the assembler code to reflect the correct pins for my
board:

-snip-
...
		OUTPUT ON,  pad_K12
		OUTPUT OFF, pad_P14
		OUTPUT OFF, pad_L12
		OUTPUT ON,  pad_N14

		OUTPUT OFF, pad_P13
		OUTPUT ON,  pad_N12
		OUTPUT OFF, pad_P12
		OUTPUT ON,  pad_P11
swloop:


		OUTPUT ON,  pad_K12
		CALL ledelay

		OUTPUT OFF,  pad_K12
		CALL ledelay
-snip-

A note is that the "prepare.bat"-file uses direct-path to the
xilinx82-environment and for me that is using xilinx81 I must manually
go in and change it and it did not indicate any errors before doing
this either. Use the %XILINX% environment variable instead in some
smart way. I've changed it to suit me, but this didn't fix the
problem..

Do you have any ideas what could be wrong with my setup? The end-result
is that the board indicates a correctly download-procedure by lighting
the green LED next to the "PROG DONE" button. How should the RESET be
handled within Impact? Now it automatically starts (try to start) after
the programming has finished.

Keep on working on the tool and I'll keep on testing it and reporting
back!

Best Regards
Magnus


Antti Lukats wrote:
> PicoBlaze C compiler has been available for some time already,
> but until yesterday I never tried it.
> But today when I type:
>
> >start build.bat
>
> then the following C file
>
> ----- cut -----
> // This is first PCCOMP Program tested on MicroFpga!
> // Target was S3-200 with KCPSM3_256S MF-Core
>
> #include "..\inc\padmap.h"
> #include "..\inc\board.h"
> #include "..\lib\pinapi.h"
>
> unsigned int i;
>
> // Delay
> void ledelay() { for (i=0;i<65000;i++) {} }
>
> void main()
> {
>  // blink a LED forever !
>  while (1) {
>   SetPin(LED1, 0); ledelay();
>   SetPin(LED1, 1); ledelay();
>  }
> }
> ----- cut -----
>
> generates a BIT file (without invoking synthesis or fpga implementation
> tools)
> and there is LED blinking on my desk right this moment :)
>
> KCSPM3_256S core only supports maximum 256 FPGA I/Os but its still fun
>
> the evaluation package is ready for download
>
> http://www.microfpga.com/joomla/index.php?option=com_remository&Itemid=27&func=fileinfo&id=3
>
> it includes the MicroFpga bitstreams and compile scripts
> devices included:
> xc2v1000_fg256
> xc2v250_cs144
> xc2v250_fg256
> xc2v250_fg456
> xc2v40_cs144
> xc2v40_fg256
> xc2v500_fg256
> xc2v80_cs144
> xc2v80_fg256
> xc2vp2_ff672
> xc2vp2_fg256
> xc2vp2_fg456
> xc2vp4_fg256
> xc2vp4_fg456
> xc2vp7_fg456
> xc3s1000_fg320
> xc3s1000_ft256
> xc3s200_ft256
> xc3s200_pq208
> xc3s200_tq144
> xc3s200_vq100
> xc3s400_fg320
> xc3s400_ft256
> xc3s400_pq208
> xc3s400_tq144
> xc3s50_cp132
> xc3s50_pq208
> xc3s50_tq144
> xc3s50_vq100
> xc4vfx12_sf363
> xc4vlx15_sf363
> xc4vlx25_sf363
>
> note: MicroFpga is useable on linux too, but PCCOMP and KCPSM3 are only
> available for
> windows platform - on linux the java based picoblaze assembler should be
> used
> (we have no scripts or support for that at the moment)
>
> Antti
> PS MicroBlaze based MicroFgpa packages are are also ready but will be
> released a little later.


Article: 113784
Subject: How to simulate from the xilinx ISE
From: <phooey>
Date: Thu, 21 Dec 2006 14:10:04 -0000
Links: << >>  << T >>  << A >>
Hello all,
How do I start a simulation from the xilinx ISE?
thanks.



Article: 113785
Subject: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
From: "Marco T." <mmm@mmm.com>
Date: Thu, 21 Dec 2006 15:16:27 +0100
Links: << >>  << T >>  << A >>

"Antti" <Antti.Lukats@xilant.com> ha scritto nel messaggio 
news:1166687447.575834.152950@n67g2000cwd.googlegroups.com...
> Marco T. schrieb:
>> Could you tell me which application has the plb_dvi controller?
>>
>> Many Thanks
>> Marco
>
> MPMC2, look at refcores, there it is !
>
> Antti
> http://www.microfpga.com
>


Many Thanks Antti!!

Marco



Article: 113786
Subject: Re: How to simulate from the xilinx ISE
From: "Pablo" <pbantunez@gmail.com>
Date: 21 Dec 2006 07:29:37 -0800
Links: << >>  << T >>  << A >>

phooey ha escrito:

> Hello all,
> How do I start a simulation from the xilinx ISE?
> thanks.

I don't start a simulation in ISE. I have done this in gtkwave and ghdl
(for Linux). But, first of all, you have to define a testbench, that
is, you have to define the signals that you have to simulate, for
example the clock.

I hope this can help you.


Article: 113787
Subject: Re: How to simulate from the xilinx ISE
From: helmut.leonhardt@gmail.com
Date: 21 Dec 2006 09:36:10 -0800
Links: << >>  << T >>  << A >>
Hi,

Rightclick on you top entity > New Source > Testbench Wavefrom....

Bye Helmut

Pablo schrieb:

> phooey ha escrito:
>
> > Hello all,
> > How do I start a simulation from the xilinx ISE?
> > thanks.


Article: 113788
Subject: Re: ANN: PicoBlaze C: compile to bitstream!
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 21 Dec 2006 19:09:06 +0100
Links: << >>  << T >>  << A >>
"spartan3wiz" <magnus.wedmark@gmail.com> schrieb im Newsbeitrag 
news:1166710133.913520.220700@n67g2000cwd.googlegroups.com...
> Hi Antti,
>
> I like what you have done and are trying to do with MicroFPGA. Nice
> idea!
>
> I downloaded your MicroFPGA test-package but I can't get it working
> correctly. As I understand the clock used are created by some kind of
> internal DDS of something? Can you explain this further?  Can this give
> problems with differnet circuits?
>
> I tried out both the build.bat for the assembler-example and the
> build.bat for the C-example. Both of them create a download.bit but
> when downloading them using Impact no LED is blinking.
>
Hi Magnus,

thanks a lot for trying - it seems that you made all correct
there was however a minor typo in assembly example build script
namly project was set to 'blink' and source code was 'leds' as
result an empty hex file was created, and that will not do anything.

the c example should have compiled out of the box, and assuming the
board specific include file was ok, it should have worked.

all MicroFpga's start without the need of any external signals
eg no clock or reset is required depending on the MicroFpga
config there may be options to change the clock later to either
different frequency or source.

note that there is also no need to worry about "startup clock"
setting, the same bitstream will work without changing the clock
option from jtag and from cclk based configuration method.

S3sk board has LEDs active high, so when the microfpga
is loaded all of them should be half-on because of the fpga
pullups.

if want to troubleshoot uncomment the "clean" to leave all
files in place and look that the .mem file is not empty

after configuring with download.bit read back the usercode
should be a5000001

if that all doesnt help please contact per email, we do
provide support

Antti
http://groups.google.com/group/microfpga 



Article: 113789
Subject: Re: timing?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Thu, 21 Dec 2006 12:14:55 -0800
Links: << >>  << T >>  << A >>
223 wrote:

> I have checked this program on the xilinx ISE and it seems
> to synthesise.

You won't get what you are expecting without
a synchronous block.

 Can someone explain what is the .timescale
> directive

`timescale <reference_time_unit>/<time_precision>

This is a simulation setting that has
no effect on your design.

 and where I can find its help screen

http://www.asic-world.com/verilog/verifaq2.html

> (I tried the
> help from the ISE, but this simply opens my browser somewhere
> on the xilinx website, and there is no help for it there.

Use only modelsim and your editor until the design sims ok.

> Secondly, since I am using blocking assignments, what does it
> actually mean, will I have propagation delay issues or what?

"<=" assignments are the popular choice for everything,
but I prefer to use them only for module outputs.
See the example code below.

> Thirdly, can someone write a short test bench to simulate this
> on the ISE (shouldn't be too difficult with just one input and
> one output)

It isn't too difficult.
http://www.google.com/search?q=verilog+testbench+example
Give it a try on the code below.

> and lastly, can someone explain how I can implement
> this program with a schematic instead of hdl, my problem is what
> logic devices correspons to 'always' and also to 'if/else'?
> thanks.

Once you get always and if figured out, ise or quartus
will draw the schematic for you with the RTL viewer
like this: http://home.comcast.net/~mike_treseler/div10.pdf

Happy Holidays

       -- Mike Treseler


//________________________________________________
`timescale 1ns/10ps

module div10 (clk, q);
//M.Treseler Thu Dec 21 11:37:49 2006
output q;
   reg q; // allows block output to module port
input clk;

  always @(posedge clk)
    begin: process // named block
      // local declarations
       reg q_v;
       reg [3:0] cnt_v;

      // update regs
      if (cnt_v == 4'h9)
        begin
           cnt_v = 4'h0;
           q_v = 1;
        end
      else
        begin
           q_v = 0;
           cnt_v = cnt_v + 1'b1;
        end

      // out to module port
      q <= q_v;
   end // block: process

endmodule

Article: 113790
Subject: What next next big thing coming for HDL?
From: "jjlindula@hotmail.com" <jjlindula@hotmail.com>
Date: 21 Dec 2006 12:16:37 -0800
Links: << >>  << T >>  << A >>
Hello, I''ve been talking with a co-worker about the HDL languages that
are availabile these days, such as VHDL, Verilog, SystemVerilog, and
AHDL. In our shop we've used AHDL because it was easy to learn and use
and because we've decided to stay with Altera chips. My co-worker
believes that in the future these languages will be passed over my
better HDL's and that sparked my curiousity. What is the next big HDL
that will catch on and grab people from these different HDL
backgrounds? Will VHDL, Verilog, AHLD, or SystemVerilog be replaced by
something better? If so, what do you think it will be?

thanks,
joe


Article: 113791
Subject: Re: PLL minimum input clock frequency
From: kayrock66@yahoo.com
Date: 21 Dec 2006 12:54:13 -0800
Links: << >>  << T >>  << A >>
Just use a crystal or resonator, not an oscillator.  They are small and
under a buck in small quantities.  Use the Lattice to provide the gain
and 180 degree phase shift required to sustain oscillation.

Jay

Ndf wrote:
> Hello all,
>
>
>
> I would like to multiply by 4 a USB chip 12MHz clock. The phase shift is not
> important.
>
> I cannot use LatticeXP PLL because minimum input clock frequency is 25MHz.
>
> There is a way to work around this problem? I would like to save space and
> money avoiding an external oscillator.
> 
> 
> 
> Thanks,
> 
> Dan.


Article: 113792
Subject: Re: Soft processor Microblaze vs embedded core PowerPC
From: kayrock66@yahoo.com
Date: 21 Dec 2006 12:57:26 -0800
Links: << >>  << T >>  << A >>
The 2 options are good at different things.  The way I look at is if
your task is computationally intensive, go for the PPC because you can
clock it at hundreds of MHz and run out of on-macro cache.  If the task
is basically an I/O processor and you're plugging OPB peripherals, go
with the microblaze, its faster for that kind of stuff.


hattangady@gmail.com wrote:
> Hi,
>
>   I am unable to come across any material that critically examines the
> reasons I must go in for Microblaze or Powerpc. Is processor
> obsolesence the only reason why an FPGA designer would go in for
> Microblaze? Could the present PowerPC architecture could become
> obsolete?
> 
> Regards,
> Sandy


Article: 113793
Subject: DCM start up
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Thu, 21 Dec 2006 23:45:56 -0000
Links: << >>  << T >>  << A >>
I've got a DCM as part of a 4 byte Aurora implementation on a VII Pro. 
Sometimes after JTAG configuration the DCM just won't lock (hence the 
ChannelUp never happens either). Once it's decided not to work, doing the 
reconfiguration again or resetting has no effect. If I then configure with 
an old version of code (also with a power cycle) it works OK with old and 
new code. Are there any tricks I should know about here either in the VHDL 
or settings in the tools that anyone can tell me about please as I really 
need to get around this problem?

TIA,

Rog. 



Article: 113794
Subject: FSL feasibiliity
From: hattangady@gmail.com
Date: 21 Dec 2006 16:41:22 -0800
Links: << >>  << T >>  << A >>
Hi,

  Can anyone tell me the fastest interface from Microblaze and PowerPC
to a custom peripheral if it were to be used for DSP applications?
Would FSL (the unarbitrated FIFO interface) be feasible or would OPB be
better to use? Are there other options?

Regards,
Sandy


Article: 113795
Subject: Re: DCM start up
From: Austin <austin@xilinx.com>
Date: Thu, 21 Dec 2006 18:07:48 -0800
Links: << >>  << T >>  << A >>
Roger,

What is the status of the DCM is this condition (the status byte)?

It may be that the CLKFB signal isn't right while the DCM attempts to 
lock, and it either can't lock (taps on delay lines overflow or 
underflow), or it locks in the wrong place.

Try resetting the DCM after a delay to allow oscillators and all 
circuitry to stabalize.

Austin



Roger wrote:

> I've got a DCM as part of a 4 byte Aurora implementation on a VII Pro. 
> Sometimes after JTAG configuration the DCM just won't lock (hence the 
> ChannelUp never happens either). Once it's decided not to work, doing the 
> reconfiguration again or resetting has no effect. If I then configure with 
> an old version of code (also with a power cycle) it works OK with old and 
> new code. Are there any tricks I should know about here either in the VHDL 
> or settings in the tools that anyone can tell me about please as I really 
> need to get around this problem?
> 
> TIA,
> 
> Rog. 
> 
> 

Article: 113796
Subject: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
From: "abright52" <abright52@gmail.com>
Date: 21 Dec 2006 18:24:29 -0800
Links: << >>  << T >>  << A >>
Anyone else have any ideas?  We are trying to get this done for a
school project and our professor that is supposed to help us, doesn't
know how to solve the problem.  We have tired to contact Xilinx and
they have been uncooperative.

Thanks.

abright52 wrote:
> Hello,
>   We are using the Xilinx Virtex-II Pro Developement System XUP-V2P.
> Our objective is to read a binary file that contains 0101 into the
> board from the compact flash card, then modify the file and write it
> back to the board.  Right now we would just like to invert the numbers,
> to make things simple.
>
>   Our main problem is when we connect the CF Card to the Board the
> SYSTEM ACE ERROR light illuminates.  We have checked to make sure that
> it is formatted correcly using mkdosfs, as recommended by Xilinx.  The
> only thing loaded on the card is our .bin file.
> 
>   Does anyone know what else could cause this?
> 
> Thank you.


Article: 113797
Subject: Re: FSL feasibiliity
From: "Lorne Mower" <lm@mulchit.com>
Date: Fri, 22 Dec 2006 09:53:28 -0000
Links: << >>  << T >>  << A >>

<hattangady@gmail.com> wrote in message 
news:1166748082.931353.231820@i12g2000cwa.googlegroups.com...
> Hi,
>
>  Can anyone tell me the fastest interface from Microblaze and PowerPC
> to a custom peripheral if it were to be used for DSP applications?
> Would FSL (the unarbitrated FIFO interface) be feasible or would OPB be
> better to use? Are there other options?
>
> Regards,
> Sandy
>

Don't know about Microblaze, but for PowerPC fastest would be DMA. 



Article: 113798
Subject: Re: DCM start up
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Fri, 22 Dec 2006 12:10:36 +0000
Links: << >>  << T >>  << A >>
On Thu, 21 Dec 2006 23:45:56 -0000, "Roger" <enquiries@rwconcepts.co.uk>
wrote:

>I've got a DCM as part of a 4 byte Aurora implementation on a VII Pro. 
>Sometimes after JTAG configuration the DCM just won't lock (hence the 
>ChannelUp never happens either). Once it's decided not to work, doing the 
>reconfiguration again or resetting has no effect. If I then configure with 
>an old version of code (also with a power cycle) it works OK with old and 
>new code. Are there any tricks I should know about here either in the VHDL 
>or settings in the tools that anyone can tell me about please as I really 
>need to get around this problem?

May not be related to the DCM problem, but starting the PPC from JTAG in
a V2Pro was also problematic (random failure, probability > 50%) unless
the "Pulse Prog" option was ticked in IMPACT. 

My webcase didn't get a clear explanation from Xilinx, so I suggest
these two startup problems MAY be related, and (if you're using Impact)
it's a quick and easy change to try. (If you're accessing JTAG by some
other tool, there must be some way to pulse the PROG pin). I'd be
interested to hear if this clears the problem.

- Brian

Article: 113799
Subject: Re: Virtex-5 Webpack?
From: bkelly@altera.com
Date: 22 Dec 2006 06:45:59 -0800
Links: << >>  << T >>  << A >>
My name is Bud Kelly and I am the Area Channel Manager for Altera based
here in Chelmsford. We have a very comprehensive University Program,
including software and boards, that I would be happy to discuss with
you. I can be reached at bkelly@altera.com.


jonas@mit.edu wrote:
> Hello! For a long time my lab purchased the lower-cost ISE Base-X kit,
> which was recently discontinued and its functionality was rolled into
> WebPack (which is available for free!) Base-X always seemed to contain
> support for the two smallest of Xilinx's high-end devices. The latest
> WebPack, however, does not contain support for the V5s. Is there a plan
> to have V5 support in WebPack in the future?
>
> I know the standard Xilinx line on this is "If you're doing high-end
> development, ISE tools are not going to be a big part of your cost" but
> in our environment where we have a bunch of students doing development
> on prototype boards, the license costs can add up quickly.
> 
> Thanks, 
>        ...Eric




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