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Messages from 109725

Article: 109725
Subject: ISE timing errors
From: dhruvakshad@gmail.com
Date: 4 Oct 2006 09:02:37 -0700
Links: << >>  << T >>  << A >>
my basic design works perfectly. Now when I add a set of adders to the
design I get timing errors in my design.
I changed the PAR effort level from standard to medium  andthe PAR
completed successfully however when I test the design I see that my
state machine gets stuck at one state and doesnt come out of it. It
runs the first cycle of transitions susccessfully .However after that
it gets stuck.What are the possible solutions which I can try.  I
changed the design to accomodate adders in different possible ways but
still with no success.
Thanks,
D


Article: 109726
Subject: Re: Xilinx PowerPC & MicroBlaze Development Kit
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Wed, 04 Oct 2006 09:24:08 -0700
Links: << >>  << T >>  << A >>
czeczek wrote:
> Hi,
> Is there anyone who knows where can I buy XIlinx PowerPC & MicroBlaze
> Development Kit in european union ?? (DO-ML403-EDK-ISE,
> http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Intellectual+Property&category=&iLanguageID=1&key=DO-ML403-EDK-ISE
> )
> I tried via XIlinx on-line store but since their products are not RoHS
> compliant it's not possible to ship it to EU.

You are correct that the ML403 is not RoHS compliant, but we pre-stocked
inventory on this board with our distributor Avnet/Silca prior to the
July 1st cutoff date for sale in the EU.  If you contact your local
Avnet/Silica office they will sell you this board.

Ed McGettigan
--
Xilinx Inc.

Article: 109727
Subject: Re: How to create a library for a Xilinx project
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 4 Oct 2006 09:52:37 -0700
Links: << >>  << T >>  << A >>

Jim Wu wrote:
> > I found the simplest way to create a library for a project while using
> > ModelSim:
> > 1. Put all necessary *.vhd files into one proejct directory;
> > 2. Compile them without errors;
> > 3. Delete all *.vhd files that are generated by Xilinx CoreGenerator or
> > something similar;
> >
> > These deleted *.vhd code are still referenced properly in the work
> > library and there are no need to generate a separate library.
> >
> > Any comments?
>
>
> Not sure what you're trying to do. If you just want to avoid
> re-compiling the core libraries, you don't have to delete the source
> files. What you can do is to do the compile in two steps:
>
> vlog -f my_core_files
> vlog -f my_design_files
>
> If you make any changes to your design files, you only need to run the
> second step.
>
> HTH,
> Jim
> http://home.comcast.net/~jimwu88/tools/
> 
> 
> > > > Weng

Hi Jim,
Thank you.

Weng


Article: 109728
Subject: Re: ISE timing errors
From: "KJ" <kkjennings@sbcglobal.net>
Date: Wed, 04 Oct 2006 16:55:18 GMT
Links: << >>  << T >>  << A >>
<dhruvakshad@gmail.com> wrote in message 
news:1159977757.366498.50050@h48g2000cwc.googlegroups.com...
> my basic design works perfectly. Now when I add a set of adders to the
> design I get timing errors in my design.
> I changed the PAR effort level from standard to medium  andthe PAR
> completed successfully however when I test the design I see that my
> state machine gets stuck at one state and doesnt come out of it. It
> runs the first cycle of transitions susccessfully .However after that
> it gets stuck.What are the possible solutions which I can try.  I
> changed the design to accomodate adders in different possible ways but
> still with no success.

You've already identified the problem "I get timing errors in my design". 
To 'fix' timing problems you need to start by performing static timing 
analysis.  One of the things you need to perform static timing analysis is 
the output of the place and route which produces a file that has the results 
of the timing analysis that was performed by whatever place and route tool 
was used to run through the design.  There are four basic types of numbers 
you're looking for Tsu, Tco, Tpd and T.  The last one is the minimum clock 
cycle that your design will work at.  The other three have to do with when 
inputs and outputs will be changing.

Once you've performed static timing analysis you will know when the input 
are allowed to change and at what time the outputs are allowed to change. 
These conditions must be adhered to both in a simulation environment or on 
an actual board.

If you have inputs that are inherently asynchronous to your FPGA clock then 
this means you'll find that you have a Tsu setup time that you are required 
to meet...but can't because the input is asynchronous to the clock.  What 
you need to do there is first synchronize the signal with two flip flops and 
feed the output of the second flip flop to the rest of your design.  The 
output of the first flip flop goes nowhere except for the input of the 
second flip flop.

Failure to perform static timing analysis and model these conditions 
appropriately is the primary cause for timing simulations to fail even 
though simulating the original code, 'works perfectly'.  Similarly, failure 
to perform static timing analysis and putting the design into an actual part 
on a real board is the primary cause for 'flaky', 'unexpected' results that 
'don't make any sense'.  In both cases, if timing is violated then you can 
expect to see just about any symptom.

This analysis does NOT require use of simulation...in fact a simulator is 
completely useless for this analysis.  Also, the above method is used for 
any design, it has absolutely nothing to do with the particular function 
you're implementing (i.e. 'adders', 'more adders', etc.).  For that reason, 
"changed the design to accomodate adders in different possible ways" can 
only result in failure which is what you're seeing when you report "no 
success".  You're going down the wrong path by changing the function so 
you'll never get where you need to go.

Happy hunting!
KJ 



Article: 109729
Subject: Xilinx ML310 logical analyzer
From: TaiYing@gmail.com
Date: 4 Oct 2006 10:39:49 -0700
Links: << >>  << T >>  << A >>
how to see the read signal in ML310?
i know ChipScope can do it, but i think it's not easy to add it into my
design.
i survey another way to see the real signal, does LA can see the real
signal in ML310?


Article: 109730
Subject: Re: Virtex-II Pro Platform FPGA : Assembling the modules
From: "Jens Hagemeyer" <jenze@et.upb.de>
Date: 4 Oct 2006 10:50:56 -0700
Links: << >>  << T >>  << A >>
Hi Thang,

the xilinx bus marcos will be ok. I'm not sure about the software
you're using, but if doing partial reconfiguration, i would strongly
suggest to use the Early Access Partial Reconfiguration Patch for 8.1i.


http://www.xilinx.com/xlnx/xil_entry2.jsp?sMode=login&group=prealounge

See also the paper presented by xilinx on FPL06: "Enhanced
architectures, design methodologies and CAD tools for dynamic
reconfiguration of xilinx FPGAs"

Regards,

Jens

THANG NGUYEN schrieb:

> Hi, As I know, there is not VCC-Blocks in the bus macro. Is this the problem about bus macro? Or the broblem of the module myRegister? Thanks Thang Nguyen


Article: 109731
Subject: Re: FPGA power-up and code relocation (basics)
From: "Andrea05" <cispa@email.it>
Date: 4 Oct 2006 11:13:25 -0700
Links: << >>  << T >>  << A >>
Thank you again Ben!

Your always very clear and now I'm starting to understand...

Now I'm working with a Memec V2MB1000 Development board but the goal is
to design (or at least to write the pecifications to realize ) a small
board devoted to the control of a single joint of a robot. If you are
intrested in details you can find a paper in which i'm a co-author at
http://scholar.google.com/url?sa=U&q=http://ieeexplore.ieee.org/xpls/abs_all.jsp%3Farnumber%3D1545480

> What happens if your application is bigger than the BRAM resources available
> in the FPGA?

Yeah! This is my nightmare!



> you will need some other non-volatile storage to hold the application
> program, or you'll have to find some other way to provide it to the FPGA.

Given that I have filled such non-volatile memory with the application
(how to do that will be another question!) how should I tell to the
FPGA that the program is in such memory? In this case the linker script
has a role?


> It is certainly true that using external memories for your application will
> often allow you to use a smaller FPGA device, since the BRAM resources are
> probably the limiting factor (and buying and FPGA is a very expensive way to
> buy memory!).

You got the point Ben!
One of the goals of my research is to demonstrate that the
self-coordinating technique we propose, and that form a mathematical
point of view are correct, can be implemented with a relative low cost.
So it's very important for me to choose the right components for my
control board.

> So, you are probably best off just
> asking lots of questions!

No problem Ben... I'll ask a lot, stay tuned!

Thanks, 
Andrea.


Article: 109732
Subject: PLB/OPB Bus Access from ISE
From: "akcooper8@gmail.com" <akcooper8@gmail.com>
Date: 4 Oct 2006 13:03:43 -0700
Links: << >>  << T >>  << A >>
Is there an easy way to access the PLB or OPB buses from XIlinx ISE
without going through the PowerPC and EDK?
I am using the XUP Virtex II Pro Development Board and want to
read/write from DDR RAM in ISE rather then EDK for speed reasons.
So I need to access the PLB/OPB buses from ISE which are connected to
the DDR RAM.

Thanks

Ashwin


Article: 109733
Subject: Re: Input signal problem...
From: "motty" <mottoblatto@yahoo.com>
Date: 4 Oct 2006 13:23:36 -0700
Links: << >>  << T >>  << A >>

Well, I talked to Xilinx and what I am trying to do is not possible.
There are no routing resources available to connect the ISERDES like I
want to.  Oh well.  Back to the drawing board!


Article: 109734
Subject: Re: Are you ready for Virtex-5? We are...
From: "Peter Alfke" <peter@xilinx.com>
Date: 4 Oct 2006 14:01:27 -0700
Links: << >>  << T >>  << A >>

PeteS wrote:
>> Here's my view as a system designer:
>
> 1. Errata are a fact of life in silicon. I have never met a device in
> the last 10 years that did not have errata against it.
>
> 2. If the device itself has no NDA requirement, then neither should the
> errata. The press _might_ make a meal of it, but probably not; designers
> expect it - indeed we welcome it because it makes our life easier if we
> know about issues.
>
>
> That said, make it easy for me to design something in at the hardware
> level (easier than your competition) and I will live with other issues.
> Compiler / PAR etc., can be dealt with if I can at least design with the
> part, but that requires full disclosure at the time I am designing. If
> Xilinx makes it difficult for me to find that info, then I won't design
> with their parts - nothing personal, but that's the way it is. I have
> rejected certain vendors because they won't provide me with what I
> consider sufficient information _without jumping through hoops_ to
> design their parts.
>
> I like Xilinx parts - indeed, a friend of mine used to be a Xilinx
> employee doing IP cores (and may still be for all I know), and that
> colours my view :)
>
> So please - do the right thing and just make it open on the same page as
> the basic docs. (A lot of others do)
>
> Cheers
>
> PeteS
========
I am now addressing two issues:
1.Can we make registration easier, and
2.Should registration be required for downloading errata.

1. Regarding the problems with registration, the responsible guy within
Xilinx tells me:

"We are in the process of completely redesigning the Web Registration
system. Our existing system may be slow, but it is not that difficult
to use.  Remember, 1.5 million visitors come to our site every quarter
and I haven't heard a complaint like this in years.  From what I can
tell things are working reasonably well.  If this is not the case,
perhaps we can pull something together to mitigate any existing issues
as we continue to develop the new system."

Any comments? If you have specific gripes, e-mail me:  peter@xilinx.com
We want to make it easy to evaluate, buy, and use our parts. Obviously.

2. Regarding the need for registration, we want to make sure that you
look at the relevant errata for your specific order. Before accepting
any ES order, we always ask you to acknowledge that errata, and we then
ship the part with the errata print-out. Just to make sure.
But I am still trying to get the errata documentation free of
registration...

Peter Alfke, Xilinx Applications


Article: 109735
Subject: Re: ISE timing errors
From: dhruvakshad@gmail.com
Date: 4 Oct 2006 14:07:40 -0700
Links: << >>  << T >>  << A >>
Hello KJ,
 I have added exactly one flip flop in  between the asycnhronous inputs
and the state machines since the asynchronous input is coming at a much
lower rate. is it ok?

Thanks,
D

KJ wrote:
> <dhruvakshad@gmail.com> wrote in message
> news:1159977757.366498.50050@h48g2000cwc.googlegroups.com...
> > my basic design works perfectly. Now when I add a set of adders to the
> > design I get timing errors in my design.
> > I changed the PAR effort level from standard to medium  andthe PAR
> > completed successfully however when I test the design I see that my
> > state machine gets stuck at one state and doesnt come out of it. It
> > runs the first cycle of transitions susccessfully .However after that
> > it gets stuck.What are the possible solutions which I can try.  I
> > changed the design to accomodate adders in different possible ways but
> > still with no success.
>
> You've already identified the problem "I get timing errors in my design".
> To 'fix' timing problems you need to start by performing static timing
> analysis.  One of the things you need to perform static timing analysis is
> the output of the place and route which produces a file that has the results
> of the timing analysis that was performed by whatever place and route tool
> was used to run through the design.  There are four basic types of numbers
> you're looking for Tsu, Tco, Tpd and T.  The last one is the minimum clock
> cycle that your design will work at.  The other three have to do with when
> inputs and outputs will be changing.
>
> Once you've performed static timing analysis you will know when the input
> are allowed to change and at what time the outputs are allowed to change.
> These conditions must be adhered to both in a simulation environment or on
> an actual board.
>
> If you have inputs that are inherently asynchronous to your FPGA clock then
> this means you'll find that you have a Tsu setup time that you are required
> to meet...but can't because the input is asynchronous to the clock.  What
> you need to do there is first synchronize the signal with two flip flops and
> feed the output of the second flip flop to the rest of your design.  The
> output of the first flip flop goes nowhere except for the input of the
> second flip flop.
>
> Failure to perform static timing analysis and model these conditions
> appropriately is the primary cause for timing simulations to fail even
> though simulating the original code, 'works perfectly'.  Similarly, failure
> to perform static timing analysis and putting the design into an actual part
> on a real board is the primary cause for 'flaky', 'unexpected' results that
> 'don't make any sense'.  In both cases, if timing is violated then you can
> expect to see just about any symptom.
>
> This analysis does NOT require use of simulation...in fact a simulator is
> completely useless for this analysis.  Also, the above method is used for
> any design, it has absolutely nothing to do with the particular function
> you're implementing (i.e. 'adders', 'more adders', etc.).  For that reason,
> "changed the design to accomodate adders in different possible ways" can
> only result in failure which is what you're seeing when you report "no
> success".  You're going down the wrong path by changing the function so
> you'll never get where you need to go.
> 
> Happy hunting!
> KJ


Article: 109736
Subject: Re: ISE timing errors
From: dhruvakshad@gmail.com
Date: 4 Oct 2006 14:13:36 -0700
Links: << >>  << T >>  << A >>
  how could I find the maximum frequency of the adder generated using
core generator?
thanks,
D



dhruvaks...@gmail.com wrote:
> Hello KJ,
>  I have added exactly one flip flop in  between the asycnhronous inputs
> and the state machines since the asynchronous input is coming at a much
> lower rate. is it ok?
>
> Thanks,
> D
>
> KJ wrote:
> > <dhruvakshad@gmail.com> wrote in message
> > news:1159977757.366498.50050@h48g2000cwc.googlegroups.com...
> > > my basic design works perfectly. Now when I add a set of adders to the
> > > design I get timing errors in my design.
> > > I changed the PAR effort level from standard to medium  andthe PAR
> > > completed successfully however when I test the design I see that my
> > > state machine gets stuck at one state and doesnt come out of it. It
> > > runs the first cycle of transitions susccessfully .However after that
> > > it gets stuck.What are the possible solutions which I can try.  I
> > > changed the design to accomodate adders in different possible ways but
> > > still with no success.
> >
> > You've already identified the problem "I get timing errors in my design".
> > To 'fix' timing problems you need to start by performing static timing
> > analysis.  One of the things you need to perform static timing analysis is
> > the output of the place and route which produces a file that has the results
> > of the timing analysis that was performed by whatever place and route tool
> > was used to run through the design.  There are four basic types of numbers
> > you're looking for Tsu, Tco, Tpd and T.  The last one is the minimum clock
> > cycle that your design will work at.  The other three have to do with when
> > inputs and outputs will be changing.
> >
> > Once you've performed static timing analysis you will know when the input
> > are allowed to change and at what time the outputs are allowed to change.
> > These conditions must be adhered to both in a simulation environment or on
> > an actual board.
> >
> > If you have inputs that are inherently asynchronous to your FPGA clock then
> > this means you'll find that you have a Tsu setup time that you are required
> > to meet...but can't because the input is asynchronous to the clock.  What
> > you need to do there is first synchronize the signal with two flip flops and
> > feed the output of the second flip flop to the rest of your design.  The
> > output of the first flip flop goes nowhere except for the input of the
> > second flip flop.
> >
> > Failure to perform static timing analysis and model these conditions
> > appropriately is the primary cause for timing simulations to fail even
> > though simulating the original code, 'works perfectly'.  Similarly, failure
> > to perform static timing analysis and putting the design into an actual part
> > on a real board is the primary cause for 'flaky', 'unexpected' results that
> > 'don't make any sense'.  In both cases, if timing is violated then you can
> > expect to see just about any symptom.
> >
> > This analysis does NOT require use of simulation...in fact a simulator is
> > completely useless for this analysis.  Also, the above method is used for
> > any design, it has absolutely nothing to do with the particular function
> > you're implementing (i.e. 'adders', 'more adders', etc.).  For that reason,
> > "changed the design to accomodate adders in different possible ways" can
> > only result in failure which is what you're seeing when you report "no
> > success".  You're going down the wrong path by changing the function so
> > you'll never get where you need to go.
> > 
> > Happy hunting!
> > KJ


Article: 109737
Subject: Re: free CAN field bus IP for EDK ?
From: rponsard@gmail.com
Date: 4 Oct 2006 14:18:27 -0700
Links: << >>  << T >>  << A >>
for those who have done it :
how much work is it to integrate a CAN controler as the one in opencore
into an =B5blaze-EDK design (day, week, month ???)


Article: 109738
Subject: Re: FPGA power-up and code relocation (basics)
From: "u_stadler@yahoo.de" <u_stadler@yahoo.de>
Date: 4 Oct 2006 14:25:45 -0700
Links: << >>  << T >>  << A >>
hi andrea,

well i'm facing the exact same problem as you are. just started to work
with the xilinx edk and a digilent spartan 3e board. i found this xapp
(http://www.xilinx.com/bvdocs/appnotes/xapp482.pdf) from xilinx talking
about using the platform flash for storing the configuration bitstream
and the user software. seems to work with a bootloader. this would be a
nice sollution in my eyes because you don't need anything else than the
platformflash as non-volatile memory.
i'm playing around with this right now but could't get it to work so
far becuase the sample project isn't working...
well thought you might be interested in this.

urban


Article: 109739
Subject: Re: logarithm look-up table
From: "j.bernspang" <j.bernspang@gmail.com>
Date: 4 Oct 2006 14:47:17 -0700
Links: << >>  << T >>  << A >>
Ray and John_H,

Thanks a lot for your inputs. I kind of knew I would get some valuable
comments from the group, and I'm not really surprised it came from you
guys... I will take it to my heart and implement it as soon as I get
back to my office.

Regards

Johan


Ray Andraka skrev:

> Johan Bernsp=E5ng wrote:
> > Hi all,
> >
> > I'm about to convert the amplitude output from a Cordic to dB,
> > 20*log(amp) that is. The output from the Cordic is 24 bits wide, the
> > maximum value would thus be approximately 144.5 dB. It is sufficient
> > with 12 bits resolution on the logarithm, 8 integer bits and 4
> > fractional bits.
> >
> > My idea is to create a look-up table out of BRAM in the FPGA, and since
> > I want 12 bits resolution the size should not be larger than 2312 words
> > (the largest value is 10010000.0111 which is equal to 2311 if the binary
> > point is removed) each 12 bits wide. The problem has proved to be to
> > create a clever address function though.
> >
> > Any thoughts or ideas I have forseen? I'm sure this has been done
> > before, but some Googling didn't really help me in the right direction.
> >
> > Regards
>
> Left shift the CORDIC output to get the first '1' bit into the left most
> position, keeping track of how many bit positions you shift.  Each shift
> is 6dB.  The residue that is left has the MSB always '1' so it can be
> discarded (it is implied), and then use as many MSBs of the remaining
> residue to address a smaller table.  Add the number of bit shifts * 6dB
> to the table output to get your complete log.  A 4 bit look-up will get
> you to about 1/4dB, which is often sufficient.  In that case, no BRAMs
> are used or harmed for testing the product :-)


Article: 109740
Subject: Re: free CAN field bus IP for EDK ?
From: "Antti" <Antti.Lukats@xilant.com>
Date: 4 Oct 2006 15:10:07 -0700
Links: << >>  << T >>  << A >>
rponsard@gmail.com schrieb:

> for those who have done it :

no one around!

> how much work is it to integrate a CAN controler as the one in opencore
> into an =B5blaze-EDK design (day, week, month ???)

choice 1:

NO WORK, just take Altium Designer and use MicroBlaze or PPC with CAN,
well it will be on wishbone as Altium designer uses MicroBlaze with wb
wrapper
its a bit cheating, AD uses MB from EDK, but it really isnt true EDK
solution?

choice 2:
1 day - integration
1+ month - testing and verification

dumb estimates (your mileage may vary)

choice 3:
use GRLIB/LEON3 it already has OC CAN to AHB(APB?) wrapper

Antti


Article: 109741
Subject: Re: Looking for HDL code for sin( a ) and x ** y Functions
From: ditsdad@gmail.com
Date: 4 Oct 2006 15:13:18 -0700
Links: << >>  << T >>  << A >>
Derek Simmons wrote:
> Andrew FPGA wrote:
> > > >What I'm looking for is a resource like, if it existed, Numerical
> > > >Receipes in HDL (VHDL/Verilog).
> >
> > Elementary Functions, Algorithms and Implementation by Jean-Michel
> > Muller.
> > No HDL code but the algorithms are there.
>
> I found a couple of people have recommended this book and when I did a
> quick search on Amazon it came highly recommended. I'm looking into
> getting a copy.
>
> Thanks,
> Derek

Another book to consider is -

DIGITAL COMPUTER ARITHMETIC DATAPATH DESIGN USING VERILOG HDL by James
Stine.

It has a 25 page chapter on Elementary Functions; the style of the book
is to sketch the algorithm and then show the verilog code for typically
a 16 bit implementation at the hierarchic gate level.


Article: 109742
Subject: Can I use MIG tool to generate memory controller for DIMM module of DDR SDRAM?
From: "jetq88" <jetq5188@gmail.com>
Date: 4 Oct 2006 15:14:35 -0700
Links: << >>  << T >>  << A >>
is MIG the tool to use or there are some other tools I am not aware of
?
I want to use low profile 256M DIMM DDR-SDRAM which has ECC and 72 bit,
not regular 64 bit module, is there any tool to make my life easy to
generate memory interface.

thanks


Article: 109743
Subject: Re: logic analyzer signal tap 2 - writing data
From: "Subroto Datta" <sdatta@altera.com>
Date: Thu, 05 Oct 2006 02:31:30 GMT
Links: << >>  << T >>  << A >>
It is definitely possible to update the memory and constants in a programmed 
device from Quartus using the In System Memory Content Editor. Details can 
be found at:

http://www.altera.com/literature/hb/qts/qts_qii53012.pdf

You can use this in conjunction wiith SignalTap II Embedded logic analyzer 
to debug your work.

Hope this helps,
Subroto Datta
Altera Corp.

"david" <1024.david@gmail.com> wrote in message 
news:1159976602.300018.42380@e3g2000cwe.googlegroups.com...
> hello
> i am a student, working on development kit nios 2 cyclone edition.
> i want to use the logic analyzer to import data to the fpga from the
> logic analyzer, can i do it?
> 



Article: 109744
Subject: Just a matter of time
From: "rickman" <gnuarm@gmail.com>
Date: 4 Oct 2006 19:52:40 -0700
Links: << >>  << T >>  << A >>
Over the years I have gotten a lot of junk email from Xilinx to email
addresses that I have given out only to support and never to any
marketing channel.  I have always been disappointed that Xilinx has
done this.  But now they have sunk to a new low, they are giving or
selling my email address to third party junk emailers.

I guess I should not be surprised at this since it is getting to be the
norm rather than the exception.  Everyone seems to think it is
perfectly ok to post a non-"privacy" statement saying in typical
crypto-speak that they share your information with anyone that suits
them.  I have found that if I contact a vendor directly and say I want
to opt out of their "privacy" policy and they should not share my info
with anyone at all, they will honor this.  But why is this necessary?
Why can't a privacy policy be a PRIVACY policy and not a NON-privacy
policy?  

Am I alone in being irritated by these practices?


Article: 109745
Subject: Re: Help required regarding PCI Master core
From: Mark McDougall <markm@vl.com.au>
Date: Thu, 05 Oct 2006 13:22:31 +1000
Links: << >>  << T >>  << A >>
Adnan wrote:

> I want to write data from the master of bridge to its OWN target and
> read written data back. This might sound stupid but this is what I have
> to do. Please tell is it possible or not. IMHO it is possible. I have
> tried to do it in the following way but failed.

If I understand correctly, you're trying to bus master from the wishbone
side and have a PCI target respond? That's certainly possible.

What you need to do is setup a wishbone IMAGE that maps to a pci target
instantiated in the testbench (IIRC two are instantiated in the supplied
testbench?). So either the base address of the wishbone image is the
same as the PCI base address of the target, or you use address
translation (from the wishbone side).

The use the *wishbone* address as target_address, not the pci address
(of course they could be the same depending on how you've set it up).

Easiest way to debug is to simulate in ModelSim and see what addresses
go into the core and are coming out of the PCI bus during your call.

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 109746
Subject: Re: Just a matter of time
From: David Ashley <dash@nowhere.net.dont.email.me>
Date: Wed, 04 Oct 2006 20:23:04 -0700
Links: << >>  << T >>  << A >>
rickman wrote:
> Over the years I have gotten a lot of junk email from Xilinx to email
> addresses that I have given out only to support and never to any
> marketing channel.  I have always been disappointed that Xilinx has
> done this.  But now they have sunk to a new low, they are giving or
> selling my email address to third party junk emailers.
> 
> I guess I should not be surprised at this since it is getting to be the
> norm rather than the exception.  Everyone seems to think it is
> perfectly ok to post a non-"privacy" statement saying in typical
> crypto-speak that they share your information with anyone that suits
> them.  I have found that if I contact a vendor directly and say I want
> to opt out of their "privacy" policy and they should not share my info
> with anyone at all, they will honor this.  But why is this necessary?
> Why can't a privacy policy be a PRIVACY policy and not a NON-privacy
> policy?  
> 
> Am I alone in being irritated by these practices?
> 

I get so much spam anyway whatever comes from such sources is
just trivial. I hope oneday spammers will get their just deserts.
Death is too good for them.

-Dave

-- 
David Ashley                http://www.xdr.com/dash
Embedded linux, device drivers, system architecture

Article: 109747
Subject: Re: PLB-IPIF and user IP interface problem
From: "Ashish" <ashish.shringarpure@gmail.com>
Date: 4 Oct 2006 20:29:25 -0700
Links: << >>  << T >>  << A >>
Thanks Guys for not replying to my problem.(May be I would have got
diverted.... :)  )

I am able to solve the problem I was facing.


Just for somebody's ref.

My IPIF transaction IP Master signals were extending to next clock
after last ack and that was causing problem in initiating back to back
transactions.

PLB_IPIF took my IP master signals (asserted for one clock after de
assertion of Last_ack) as new transaction request and my state machine
went to dead lock. That also caused PLB_IPIF Ip slave attachment
Statemachine to go in  busy state and I was not able to complete more
than one write transactions!!!!!!!


This I could solve by wiring the IPMaster signals INSTAED of flopping.


Thats it...


regards

Ashish

Ashish wrote:
> Any body has updates on this????
>
>
> Ashish wrote:
> > I have a problem in initiating a PLB _IPIF back to back transactions.
> >
> > I have integrated my IP backend with PLB-IPIF.
> >
> > My IP is User master while initiating transaction and then completes
> > the transaction as slave, on IPIF side.
> >
> > Once I am done with Write transaction initiated on PLB bus from IP
> > Master interface(through IPIF)  and after receiving last_ack, I am
> > initiating another write transaction, but its fails to respond!
> >
> > The status after 1st write transaction is that Bus2IP_BE shows 80h and
> > Bus2IP_CE shows IP master chp enable asserted. What does it mean?
> >
> > I found nothing related to this in PLB_IPIF_V2_01.pdf
> > 
> > Can anybody help me out in understanding the disconnects?


Article: 109748
Subject: Re: Just a matter of time
From: Don Seglio <don.seglio@cox.net>
Date: Wed, 04 Oct 2006 23:12:34 -0500
Links: << >>  << T >>  << A >>
David Ashley wrote:
> rickman wrote:
>> Over the years I have gotten a lot of junk email from Xilinx to email
>> addresses that I have given out only to support and never to any
>> marketing channel.  I have always been disappointed that Xilinx has
>> done this.  But now they have sunk to a new low, they are giving or
>> selling my email address to third party junk emailers.
>>
>> I guess I should not be surprised at this since it is getting to be the
>> norm rather than the exception.  Everyone seems to think it is
>> perfectly ok to post a non-"privacy" statement saying in typical
>> crypto-speak that they share your information with anyone that suits
>> them.  I have found that if I contact a vendor directly and say I want
>> to opt out of their "privacy" policy and they should not share my info
>> with anyone at all, they will honor this.  But why is this necessary?
>> Why can't a privacy policy be a PRIVACY policy and not a NON-privacy
>> policy?  
>>
>> Am I alone in being irritated by these practices?
>>
> 
> I get so much spam anyway whatever comes from such sources is
> just trivial. I hope oneday spammers will get their just deserts.
> Death is too good for them.
> 
> -Dave
> 
Is that why they invented wood-chippers?

-- 

Cecil
KD5NWA
www.qrpradio.com www.hpsdr.com

"Sacred Cows make the best Hamburger!"	Don Seglio Batuna

Article: 109749
Subject: Re: JTAG cable @ 2.5 V - where?
From: "Ulrich Bangert" <df6jb@ulrich-bangert.de>
Date: Thu, 5 Oct 2006 07:23:24 +0200
Links: << >>  << T >>  << A >>
 John,

>Prog2 actually performs very well against the competition and works in
circumstances where many others fail.

is this a business secret or can you elaborate a bit on that? Using the
right buffers the high level to low level translation should not be a
problem anymore. Is it a question of TDO conditioning?

Best regards
Ulrich Bangert

"John Adair" <g1@enterpoint.co.uk> schrieb im Newsbeitrag
news:1159907018.668373.267310@i3g2000cwc.googlegroups.com...
Well I did say look-alike I didn't say the same. It looks the same to
the Xilinx software so it can use it without issue. Prog2 actually
performs very well against the competition and works in circumstances
where many others fail. We have tried several of these in compatibility
testing with our own boards. Our Prog2 isn't as good as Cable IV but
then it is about 1/5 th of the price when buying and we do give them
away with our own development boards.

John Adair
Enterpoint Ltd.

John_H wrote:
> I don't see where the "Parallel Cable III look-alike" PROG2 is 2.5V
> compliant since the Parallel Cable III doesn't work so well from 2.5V.
>
> I think I've gotten the III to work with a 3.3V supply for 2.5V JTAG but
> the IV or USB versions of the cable are certainly more robust.
>
> Perhaps the Xilinx online store could ship to Switzerland with a simple
> credit card purchase.
>
> The Parallel Cable IV doesn't include schematics but it does show what
> the input and output stages look like, easily replacing the simple
> buffers in the Parallel Cable III which does have full schematics.
>
> - John Handwork
>
>
> John Adair wrote:
> > Markus
> >
> > Our Prog2 cable(ask for narrow head version) is available in the
standard 14
> > way 2mm connector. Cost GBP10. It is a Cable III look-alike as most
third
> > party cables are. Schematics for Cable IV are generally not in public
domain
> > and generally not replicated by anyone as far as I know.
> >
> > The only advantage of the Cable IV is the download speed.
> >
> > Our shop website has those listed under programming solutions for an
easy
> > order solution.
> >
> > John Adair
> > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
> > Board.
> > http://www.enterpoint.co.uk
> >
> > "Markus Zingg" <m.zingg@nct.ch> wrote in message
> > news:ahn4i25ir1pnpqbol22na85ggkrjeoam3m@4ax.com...
> >> Hi group
> >>
> >> I'm a newbee, so please bear with me if this does not make sense.
> >>
> >> I got a AVNet (MEMEC) Virtex 4 based developper kit based on the
> >> Virtex-4 FX12 Mini Module whoes baseboard JTAG port is documented as
> >> "a 2.5V compatible JTAG chain header". The pinout is identical to what
> >> Xilinx seems to use (14 pins etc.). The docs seem to asume that one
> >> must use the Xilinx parallel cable IV which from what I understand
> >> seems to automatically sense the voltage needs of the target and is
> >> having other nice to have features. However, due to several reasons
> >> which are beond the scope of this post, I can't simply pick up the
> >> phone and order one from a supplier last not least also because I
> >> don't know any that would carry this item here in Switzerland.
> >>
> >> The net seems to be full of homebrew JTAG cable websites giving
> >> instructions to build you own. The question is can I use one of those?
> >> I'm a bit afraid that this will not work cause from what I understand
> >> they seem to be designed for 5V or 5V tolerant devices. What other
> >> options do I have? Any links to a schema of the Xilinx paralell cable
> >> IV or such to build my own JTAG cable running at 2.5V?
> >>
> >> I would also not mind to shell out the needed $$$ to get that original
> >> cable if I could easily purchase it somewhere online using paypal or a
> >> credit card and get it deliverd quickly. Any ideas?
> >>
> >> TIA
> >>
> >> Markus





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