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Messages from 117550

Article: 117550
Subject: Re: Spartan 3E Not enough block ram.
From: "Ken Soon" <csoon@xilinx.com>
Date: Wed, 4 Apr 2007 08:46:52 +0800
Links: << >>  << T >>  << A >>
> Even if you find a suitable DRAM controller to paste into your design
> overnight, reworking your scaler to work with it will require some
> significant effort.

Yeh true, well my supervisor was asking me to start from at least an
existing design and start learning at least how a DRAM controller works.
But well no matter, still can't begin how to go about even "pasting" it. It
really seems complicated with all the addresses, data and then the control
signals.

> The coding style is obvious to anyone who has spent any significant amount
> of time getting 'fancy' BRAM inferences to work. The independent read and
> write port BRAM, independently clocked or not, is the easiest to get right
> to the point of being nearly impossible to mess up.
>
Heh, oops. guess I really haven't spend significant amount of time on FPGA
yet.
Well, sometimes, I really wonder about how designers know which feature and
how many of that feature will be used and why the codes they write will
exactly used that feature in the FPGA chip. Like, if I use array for storing
some data, block rams will be used? and if I use * , mulitpliers will be
used?. Sorry if this is just too inane to answer. Just that for synthesis,
everything seems so automatic. Well, I do know about the language templates
but it looks really different.


Hmm, I guess it looks good to perform some reduction tricks that you
mentioned. I had a question on hand though.
Let's say I have the following instantiated modules under my wrapper module
as shown:
pvs_wrapper
                - h_seqlut_inst - dpbram - rtl (dp_bram.vhd)
                - v_seqlut_inst - dpbram - rtl (dp_bram.vhd)
                - h_coeff_0_0_inst - dpbram - rtl (dp_bram.vhd)
                - h_coeff_0_1_inst - dpbram - rtl (dp_bram.vhd)
                - h_coeff_1_0_inst - dpbram - rtl (dp_bram.vhd)
                - h_coeff_1_1_inst - dpbram - rtl (dp_bram.vhd)
                - h_coeff_2_0_inst - dpbram - rtl (dp_bram.vhd)
                - h_coeff_2_1_inst - dpbram - rtl (dp_bram.vhd)
                - v_coeff_0_inst - dpbram - rtl (dp_bram.vhd)
                - v_coeff_1_inst - dpbram - rtl (dp_bram.vhd)
                - v_coeff_2_inst - dpbram - rtl (dp_bram.vhd)
                - pvs_top_structural (pvs_top.vhd)
                    - ...
(erm you can ignore the pvs_top and onwards as those will be for the
original design modules)

Now each of the dp_bram.vhd has the following codes:
mem_array(conv_integer('0' & wr_addr)) <= din;
dout <= mem_array(conv_integer('0' & rd_addr));
as you mentioned, will be using the dual port rams. Thus, I was thinking of
maybe combining some of the modules together? Hmm though usage of the block
rams will still be the same.
Any common techniques that you would know that people have used when they
wish to reduce BRAMs?
(Well the trial synthesis did write out a report and it said that 60 Block
rams was used so I guess that they would have already tried to optimize the
usage and 60 block rams is the lowest they could have gone)

> You really need to look into exactly what is consuming how many BRAMs how
> and why as I suggested in my previous message. Coefficient tables and
video
> line buffers will be difficult to shift into DRAM: you will need some
BRAMs
> to buffer data to/from the DRAMs and are not going to be any better off if
> you end up with as many FIFO BRAMs as you originally needed plain BRAMs
for
> the initial design... actually, you will be worse off given the extra
> glue-logic.

Hmm can this be worse off? Well definitely FIFO Brams will be needed but it
certainly be lesser than not using the DRAM right?
If not, what purpose would the DRAM serve? (which is to store data)




Article: 117551
Subject: Re: Looking for Memory Recommendation for Spartan 3E 1200
From: "John McCaskill" <junkmail@fastertechnology.com>
Date: 3 Apr 2007 19:00:34 -0700
Links: << >>  << T >>  << A >>
On Apr 3, 4:03 pm, Matthias Einwag <matthias.ein...@web.de> wrote:
> Hi everyone,
>
> I'm working on a Board for Bus Interfacing and some Audio Processing,
> which will use Spartan 3E 1200 and the Microblaze.
> Now I'm not sure what kind of memory I should use. Size ist not too
> important for me. 8Mbytes would be ok, but more is always better. But
> the speed should be high enough to get the Microblaze run at a decent
> speed and to allow permanent storing auf 4 stereo audio streams.
> Most important is, that the layout and memory interface should run
> stable and from the beginning. There's not much time for error
> investigations and redesigns.
>
> Spartan 3E Starter Kit uses a 16bit Wide DDR SDRAM Memory. But I read
> here and in some other boards, that people have much trouble with this
> one. Is this because Spartan 3E and the given IP Cores have always
> Trouble with DDR, or because of the missing clock feedback path on the
> board?
>
> Another option would be normal SDRAM Memory. I think this should give
> less trouble. But here I'm wondering that Xilinx doesn't mention the
> Spartan 3E in the Device Family Support List of the OPB SDRAM Controller
> and the MultiChannel OPB SDRAM Controller. Only Spartan 3 and 3A are
> supported according to the Links on this page:http://www.xilinx.com/ise/embedded/edk_ip.htm
> In fact the Spartan 3E is only listed in the support list for the OPB
> DDR SDRAM Controller. Are there mistakes in this list, or is spartan 3e
> really not supported by most memory controllers?
>
> Greetings
> Matthias



If they have enough bandwidth for your application, psuedo srams are
very simple to use. I have used this part:

http://www.micron.com/products/partdetail?part=MT45W4MW16BFB-856%20WT

with the Xilinx opb_emc on a Virtex-4 part, and it just worked the
first time.  This is an 8 MB part, and they have bigger ones.  Micron
also provides simulation models for it.  It has been in stock every
time I have bought it, and best of all it comes in a manufacturing
friendly BGA package so that you do not have to worry about bending
any pins.  Anvnet and Digikey both carry it. Their web sites do not
list it as in stock, but I just bought some from Avnet and they
shipped it within a few days.

Regards,

John McCaskill
www.fastertechnology.com





Article: 117552
Subject: Re: shift register with distributed ram
From: Ray Andraka <ray@andraka.com>
Date: Tue, 03 Apr 2007 22:13:05 -0400
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

>  "Slow" (and "fast") are very nebulous statements. Losing a few
> nanoseconds in an interconnect is o.k. when the clock runs at 100 MHz,
> or even a bit faster...
> Peter Alfke

And a killer when the clock runs at 250 MHz.  100MHz is slow in modern 
FPGAs...slow compared to what the FPGA is capable of with careful design.



Article: 117553
Subject: Re: ModelSim VHDL Pragmas
From: Ray Andraka <ray@andraka.com>
Date: Tue, 03 Apr 2007 22:19:37 -0400
Links: << >>  << T >>  << A >>
Peter Klemperer wrote:

> Hi All,
> 
> In one of my VHDL designs I have a section of code that I want
> different versions for synthesis than for simulation.  Currently I
> just comment out one section and uncomment the other, but I had a
> rather embarassing incident yesterday where I forgot to change the
> comments before beginning synthesis.  Ooops.
> 
> I searched around a bit, but haven't found a definitive solution other
> than using a preprocessor.  I don't think that this is a satisfactory
> solution.  Eliminating the simulation only code is simple, the --
> synthesis translate_off/on pragmas works great.  Is there an
> equivalent for modelsim?
> 
> Thanks in advance for any ideas.
> --Peter Klemperer
> 

You could use a generic and if statement inside a process or conditional 
assignment outside to select various parts of the code.

generic (
	options: integer:=1);
	:
	:


concurrent_sig <= option1 when options=1 else option2;

process....
	if options=1 then
		sequential_sig <= option_1;
	else
		sequential_sig <= option_2;


Article: 117554
Subject: Re: ModelSim VHDL Pragmas
From: Ray Andraka <ray@andraka.com>
Date: Tue, 03 Apr 2007 22:30:18 -0400
Links: << >>  << T >>  << A >>
Gabor wrote:

> On Mar 30, 4:11 pm, "Andy Peters" <goo...@latke.net> wrote:
> 
>>On Mar 30, 12:00 pm, "Peter Klemperer" <ftpe...@gmail.com> wrote:
>>
>>
>>>Hi All,
>>
>>>In one of my VHDL designs I have a section of code that I want
>>>different versions for synthesis than for simulation.  Currently I
>>>just comment out one section and uncomment the other, but I had a
>>>rather embarassing incident yesterday where I forgot to change the
>>>comments before beginning synthesis.  Ooops.
>>
>>>I searched around a bit, but haven't found a definitive solution other
>>>than using a preprocessor.  I don't think that this is a satisfactory
>>>solution.  Eliminating the simulation only code is simple, the --
>>>synthesis translate_off/on pragmas works great.  Is there an
>>>equivalent for modelsim?
>>
>>Generate statements?
>>
>>-a
> 
> 
> 
> That's a solution to reducing the changes needed, but it doesn't fully
> automate the changes unless there's a way to detect which compiler is
> being used - Modelsim or synthesis.  If you had a way to put your
> synthesis-specific code at the top of the file, you could use the -
> line
> option for vcom in Modelsim to start compilation after the synthesis
> only section, but I don't see this as very practical.  If you were
> using Verilog I could think of a few ways to deal with this...
> In Verilog for example you can define a macro on the command line
> and then use `ifdef `else to exclude code that is for synthesis only.
> 

you can exclude blocks of code from synthesis using the syn_translate 
on/off pragma, which will allow you to put sections of code that is only 
seen during simulation.  This is useful for splitting out time 
multiplexed signals in a way that is easier to examine during 
simulation, for example.  You can get a little creative with the 
syn_translate pragma to make a function that produces a signal that is 
active only in synthesis to block simulation of a chunk of logic too, 
although I haven't found much need for that.


Article: 117555
Subject: Re: ModelSim VHDL Pragmas
From: Ray Andraka <ray@andraka.com>
Date: Tue, 03 Apr 2007 22:34:21 -0400
Links: << >>  << T >>  << A >>
Tim wrote:

> Peter Klemperer wrote:
> 
>> Hi All,
>>
>> In one of my VHDL designs I have a section of code that I want
>> different versions for synthesis than for simulation.  Currently I
>> just comment out one section and uncomment the other, but I had a
>> rather embarassing incident yesterday where I forgot to change the
>> comments before beginning synthesis.  Ooops.
>>
>> I searched around a bit, but haven't found a definitive solution other
>> than using a preprocessor.  I don't think that this is a satisfactory
>> solution.  Eliminating the simulation only code is simple, the --
>> synthesis translate_off/on pragmas works great.  Is there an
>> equivalent for modelsim?
> 
> 
> You can use this old trick:
> 
> constant MODELSIM : boolean := false
> -- synthesis translate_off
>         or true
> -- synthesis translate_on
>     ;
> 
> then
>   if MODELSIM then foo; else bar; end if;
> 
> or similar.
>     
> Jonathan B will surely post a better solution in due course.

Mine uses a function call, same idea though:

function synthesis_only return integer is
	variable temp: integer;
begin
	temp:=1;
	--synthesis translate_off
	temp:=0;
	--synthesis translate_on
	return temp;
end function synthesis_only;			


if synthesis_only()=1 then...

Article: 117556
Subject: Re: Implement IIR Filter on FPGA
From: "Gordon Freeman" <gordonfreeman1983@gmail.com>
Date: 3 Apr 2007 19:38:59 -0700
Links: << >>  << T >>  << A >>
On Apr 3, 1:22 pm, John_H <newsgr...@johnhandwork.com> wrote:
> Gordon Freeman wrote:
> > hi people,
>
> > I'm designing filter system called IIR filter  on the FPGA kit, but it
> > doesn't work when I implement on FPGA. When i iput the signals, the
> > output results seem to not get any thing. I do not know whether my
> > source code is wrong or another reason. The FPGA kit operate normally
> > with other sources which i loaded in the past.
>
> > Can anyone give me some advices to test what parts in my project do
> > not work or give me some idea to test anything. I am in the mess. I
> > hope everyone can show me.
>
> > I am looking forward hearing from people soon,
>
> Simulate your design.
>
> Watch the values change in the accumulators as you add and subtract the
> input values.

Hi everyone!
Thank you for your reply!
I used ModelSim to simulate. The result is the same when I canculate
by calculator.
But when I implement on FPGA, it don't work too.
I design IIR filter with 10 orders. I use Matlab to generate
coefficients for filter (b(k) and a(k)). For coefficient "b", I
multiply with 2^14 and multiply with 2^5 for coefficent "a". After
that I round them. These coefficients stored in LUT. I use SDA for
filter. Because I think IIR filter include tow FIR filter. One filter
with coefficient "b" and one with coefficient "a". Is it right?


Article: 117557
Subject: Re: RFC: VHDL testbench enhancements
From: "Eli Bendersky" <eliben@gmail.com>
Date: 3 Apr 2007 23:02:50 -0700
Links: << >>  << T >>  << A >>
On Apr 3, 6:10 pm, Jim Lewis <j...@synthworks.com> wrote:
> Hi,
> Let me try this again.
>
> The VHDL standards community has been considering whether
> to enhance VHDL to add advanced testbench features.
>
> If you are a VHDL user,
>    Do you want these features added to VHDL?
>    Would you rather adopt a verification language that
>    already supports these (SystemVerilog, SystemC, E, Vera).
>
> I think VHDL needs these features to stay competitive.
>
> The current plan in the VHDL working group is to make
> these features similar to other verification languages
> while at the same time keeping the nature of VHDL.
>

This would be excellent, and I will be happy to use such features.
VHDL already supports a large (compared, say, to Verilog) non
synthesizable subset for the sake of testbenches. Then why not make it
more useful.


Article: 117558
Subject: MIG under Linux
From: "=?utf-8?B?R2FMYUt0SWtVc+KEog==?=" <taileb.mehdi@gmail.com>
Date: 4 Apr 2007 00:01:19 -0700
Links: << >>  << T >>  << A >>
Hi everybody,
Did someone tried to install MIG under Linux using Wine?

Cheers
Mehdi


Article: 117559
Subject: Re: FPGA with 5V and PLCC package
From: Herbert Kleebauer <klee@unibwm.de>
Date: Wed, 04 Apr 2007 10:27:09 +0200
Links: << >>  << T >>  << A >>
Jon Elson wrote:> 
> Herbert Kleebauer wrote:
> 
> >The problem is not the money, but the time of the students.
> >The system must be very easy to use so the students can built
> >the simple CPU at gate level in 10 hours including the time to
> >learn the tools.
> >
> This is a fantasy!  You could probably design a 2-bit adder at the gate
> level in 10 hours, starting from not knowing the package.  There is no
> way a student could design a CPU at the gate level, unless it was maybe
> a Turing machine (one-bit CPU), in 10 hours.  Even if they were fluent in
> VHDL, every toolkit has its own dialect of what is accepted and what is
> not.  Then, you have to learn the simulator, how to write test benches,

Then this fantasy has become true since many years. This is a 12 week lecture
about computer organization an we have 45 min time every week for exercises.
We have combined this time to 3 x 3 hours to reduce overhead. The first
3 hours are mostly needed to explain and discuss the processor architecture
and to get familiar with the VIELOGIC system. So there only 6 hours left
to implement and test the CPU (some groups need a few additional hours,
but they are willing to spend this extra time because most of them are
really interested). They don't have to start from zero, the design is 
given at block level, but all the gates and flip-flops they have to
insert and wire themselves. And this is not a 1-bit CPU, but a 16 bit
processor (which can address 64 kbyte external memory) with external 
interrupt support and built-in IO (8 input and 8 output lines).

> debug the board, the FPGA soldering, testing the FPGA config ON the
> target board.....

The board already exists, all they have to do is to generate the 
bitstream to download. (I have posted a link to the description
of the course in the OP, the documentation the students get is:
ftp://137.193.64.130/pub/mproz/mproz_ub.pdf ).

> >
> >1. I have tried to find an actual FPGA with a package which can
> >   be soldered with a non professional equipment, something like
> >   a PLCC84 where you can get cheap sockets which can be used on
> >
> You can use Xilinx Spartan chips such as XCS10-xPC84 (x is the speed grade).
> I don't remember how big the array goes in the PC84 package.  With a

Yes, but the actual software doesn't support this chips anymore. We also
could go back to the last version which supports XC3000 so we could use
the current hardware. But I'm not even sure whether this version runs
in XP. If we have to make a cut and drop the old system, then we don't
want to replace it with something which also isn't supported anymore.

I would like to use an actual system which we could use for the next
8-10 years without modification (like we did with VIELOGIC/XC3000).
But maybe we have to drop the hardware completely and finish the 
course after the simulation. But it was always a big motivation for
the students to finally seE the processor running on a simple PCP
board with nothing than an FPGA, EPROM, SRAM and a few LED's.

Article: 117560
Subject: Conceptos about VCCINT,VCCAUX,etc
From: "jajo" <jmunir@gmail.com>
Date: 4 Apr 2007 01:42:53 -0700
Links: << >>  << T >>  << A >>
Hi!,

Maybe this doubt is stupid but nobody has explained it to me so could
you help me? What are the functionality of the listed elements into
the FPGA? Why are there several of them into the FPGA?:

-VCCINT
-VCCAUX
-VCCO
-VBATT
-MGT VREF
-MGT CLK
-MGT Termination Reference
-System Monitor/ADC

Thanx

Jajo


Article: 117561
Subject: Problem with PHY clocks on Spartan 3E Starter Kit
From: "roger" <roger.jons@gmail.com>
Date: 4 Apr 2007 01:48:25 -0700
Links: << >>  << T >>  << A >>
Hi,

I am designing a ethernet block using the Spartan 3E Starter Kit. The
design will be using the RX and TX clock provided by the SMSC PHY on
FPGA pins T7 and V3 on the Spartan 3E Starter Kit. I have problems
getting the design to work and when I started to look for errors I
found that the RX clock from the PHY doesn't seem to be possible to
use as a clock.

I made a simple counter which flashes a led in 2 Hz using first the TX
clock from the PHY as the clock input and then the RX clock as the
clock input. When I'm using the TX clock everything works fine and
when I'm using the RX clock I get no activity at all. I have verified
that I have  a clock output from the PHY using an oscilloscope.

If I instead run the counter on the 50MHz clock and sample the RX or
TX clock and increment the counter when an change on the RX or TX
clock signal has occured it works fine using any of the input clocks
from the PHY.

One could suspect some problems with the input buffers in the FPGA but
since it works using the TX clock I cant see that it is a problem in
the FPGA. It is a very confusing problem, can you give me some help
what I am doing wrong?


Article: 117562
Subject: Can I boot PowerPC without JTAG?
From: "Pablo" <pbantunez@gmail.com>
Date: 4 Apr 2007 02:20:45 -0700
Links: << >>  << T >>  << A >>
Is it possible to build an application over PowerPC and download to
board without the use of JTAG?. I have a non Xilinx Board with a
Virtex II Pro, and at the moment I have not Parallel Cable IV so I use
an application on the PC to download Bitstream to board. I have probed
with VHDL designs and all is ok, but when I try to download a PowerPC
design with a TestApp_Peripheral C Application it seems like powerpc
doesn't work (doesn't boot). Must I use JTAG? Is it possible to create
a bootloader or init bram without that cable?

Thanks

Pablo


Article: 117563
Subject: Re: Conceptos about VCCINT,VCCAUX,etc
From: "jerzy.gbur@gmail.com" <jerzy.gbur@gmail.com>
Date: 4 Apr 2007 02:37:09 -0700
Links: << >>  << T >>  << A >>
On 4 Kwi, 10:42, "jajo" <jmu...@gmail.com> wrote:
> Hi!,
>
> Maybe this doubt is stupid but nobody has explained it to me so could
> you help me? What are the functionality of the listed elements into
> the FPGA? Why are there several of them into the FPGA?:
>
> -VCCINT
Supply for the core unit.

> -VCCAUX
Supply for the configuration pins and unit.

> -VCCO
Supply for the IO bufs.

> -VBATT
Here you plug battery for backup cryptography key. If you don't use
crypto connect to ground or VCCAUX.

You will find this info in datasheets of particular families.
....
> -MGT VREF
> -MGT CLK
> -MGT Termination Reference
> -System Monitor/ADC
>
> Thanx
>
> Jajo

Regards

Jerzy Gbur


Article: 117564
Subject: Re: Boot PowerPC on VirtexIIPro
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Wed, 04 Apr 2007 11:34:03 +0100
Links: << >>  << T >>  << A >>
On 3 Apr 2007 10:25:53 -0700, "Pablo" <pbantunez@gmail.com> wrote:

>Well I have a strange problem. I have a VirtexIIPro30 on a Sundance
>target. I use XPS 8.2.02 to create a design with a 16KB of
>plb_bram_if_cntlr, and GPIO LED with bandwith 2. I add a Test_App
>Peripheral for testing leds but it seems like powerpc doesn't boot
>(work). I don't see the leds on and I have probed the design in a
>Microblaze on a Spartan. The test app is fine.
>
>PD: I have not JTAG for debugging. I have only an application to
>download "bitstream" and it is ok because I have download vhdl models
>on virtex.
>
>Does I have to init anything or use OCM??

If you are downloading using Impact, set the "Pulse PROG" option. 
(Other download tools may have other ways to pulse the programming pin).
In some systems (including the development board I use) it seems that
without this, the download may appear to complete correctly, but the PPC
doesn't come out of reset correctly.

- Brian

Article: 117565
Subject: Re: RFC: VHDL testbench enhancements
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Wed, 04 Apr 2007 12:02:26 +0100
Links: << >>  << T >>  << A >>

Hi Jim,

Jim Lewis <jim@synthworks.com> writes:

>   Classes / OO:
>     Classes are useful for creating verification data structures,
>     transaction communication, and grouping for transaction based
>     randomization (building relationships between separate data
>     items).  Many of the data structures (such as scoreboards,
>     memories, and linked structures) can already be created, however,
>     classes give you the ability to hide all pointer manipulations.
>     For example, using a memory would require a declaration with
>     initialization of the memory data structure, then MemWrite and
>     MemRead would allow a user to store and retrieve items from the
>     data structure.  Pointers and allocation of the sparse data
>     structure are handled by MemWrite and MemRead and the
>     user would not need to be aware of it.
>     Status:
>     Peter Ashenden submitted a class proposal last year and
>     provided updates to it this year at DVCon.  Currently
>     he plans on finishing an updated draft soon.
>

Is there anyway us non-members can see this?  I'm on the reflector,
and see the links to files, but of course, I can't see them :-(

I'd like to see more OO, and I agree with Andy, I'd like synthesis of
these extensions to be taken very seriously early on.

>   Randomization:
>     Randomization is useful for designs that have numerous configurable
>     features.  Testing features individually in an isolated manner is
>     typically straightforward. However, testing how these features
>     interact can be a large verification space  one that may not be able
>     to be simulated completely. It is also may be difficult to predict
>     all of the corner cases.  Randomization has been used to sequence a
>     test in a non-deterministic way to get reasonably good coverage of
>     this verification space.
>     While I do not share the thought that randomization should be
>     adapted to work for all verification problems, I do believe it
>     to be a valuable technique for some problems.
>
>     I wrote a draft of the randomization proposal and it is ready
>     for review.
>

I have to admit, I've never had a need for random testing... yet.
However, I can see where it would be useful!

>   Functional Coverage:
>     Tool/structural coverage can tell you that you did a FIFO
>     read or that the the FIFO went empty, but it can't tell
>     you that you did a read while the FIFO was empty.
>
>     Functional coverage constructs allow you to track this.
>     Some functional coverage capability will come from assertions
>     (since PSL has been integrated into VHDL).  Additional constructs
>     will be added to allow data binning (coverage groups) and
>     correlation between different coverage items (cross coverage).
>
>     I have started working on this - anyone else who is interested
>     is welcome to contribute as much as they would like.
>

Yes, this would be great!

Thanks for all your efforts!

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 117566
Subject: high number of multipliers / low cost
From: ryan_usenet@yahoo.com
Date: 4 Apr 2007 04:35:33 -0700
Links: << >>  << T >>  << A >>
Hello,
I need the highest possible number of multiplication operations per
second at low cost. I know that several factors affect the overall
performance, but since I have no idea which FPGA chips might be worth
to be considered, I'd like to ask what you think is the chip with the
lowest ratio

R=(prize of chip)* (delay time)/(number of multipliers)

18x18bit multipliers seem to be quite common, so lets assume this
design for the estimate.

For example for the Spartan XC3S1000 (~60$, 24 multipliers, 4ns delay)
I have
R= 10$ per (Billion multiplications/s). The Cyclone EP2C70 (~230$, 150
multipliers, 4ns delay) has R=6.13$ per (Billion multiplications/s).

Do other FPGAs exist that are maybe specialized for multiplication-
intensive tasks and which therefore are much cheaper?

Best regards,
Ryan


Article: 117567
Subject: Re: Spartan 3E Not enough block ram.
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Wed, 04 Apr 2007 07:58:05 -0400
Links: << >>  << T >>  << A >>
Ken Soon wrote:
>> Even if you find a suitable DRAM controller to paste into your design
>> overnight, reworking your scaler to work with it will require some
>> significant effort.
> 
> Yeh true, well my supervisor was asking me to start from at least an
> existing design and start learning at least how a DRAM controller works.
> But well no matter, still can't begin how to go about even "pasting" it. It
> really seems complicated with all the addresses, data and then the control
> signals.

The DRAM control/data/etc. signals is one thing, making the DRAM work 
exactly the way you want it to is quite another - you need to familiarize 
yourself with DRAMs' internals... learn what row activation and precharge 
do, why these are necessary, how they can affect your design and how you 
can work around these delays by doing pipelined burst transfers. There are 
a bunch of other quirks that can be exploited or have to be avoided, the 
ones enumerated are simply the more fundamental ones IMO... and do not 
forget those auto-refresh cycles.

> Well, sometimes, I really wonder about how designers know which feature and
> how many of that feature will be used and why the codes they write will
> exactly used that feature in the FPGA chip. Like, if I use array for storing
> some data, block rams will be used? and if I use * , mulitpliers will be
> used?. Sorry if this is just too inane to answer. Just that for synthesis,
> everything seems so automatic. Well, I do know about the language templates
> but it looks really different.

These things are automatic only to the extent where the HDL coder follows 
some limitations. For SRAMs/ROMs/registers to get mapped onto BRAMs, the 
synthesis tools must be able to reduce the access/data logic down to 
something supported by the hardware. For a BRAM, this means the logic must 
be reducible to no more than two read+write+address+clock sets. Depending 
on the target device, there may be additional restrictions such as 
read-write policies - write first, read before write or no change.

Multipliers also have their share of quirks, particularly if you want to do 
pipelining.

> Now each of the dp_bram.vhd has the following codes:
> mem_array(conv_integer('0' & wr_addr)) <= din;
> dout <= mem_array(conv_integer('0' & rd_addr));
> as you mentioned, will be using the dual port rams. Thus, I was thinking of
> maybe combining some of the modules together? Hmm though usage of the block
> rams will still be the same.

Look at your synthesis reports pay attention to each BRAM's inference data 
and port mappings. Look for memories that are under 8kbits and are not 
using both read and write ports - these may be mergeable if they use the 
same clocks.

> Any common techniques that you would know that people have used when they
> wish to reduce BRAMs?

1) FIR filters are often symmetric: the nth tap (n=0..N) has the same 
coefficient as the (N-n)th one... it is unlikely that this optimization has 
not already been done if applicable to your filter but double-checking is 
cheap.

2) If your coefficient tables (ROMs?) use under half a BRAM and only one 
port, you should be able to merge two tables into one BRAM by using both 
ports for reading: map one address to "'0' & addrA" and the other to "'1' & 
addrB".

3) Examine the tables to find redundancies and equivalences, it may be 
possible to multiplex accesses to the coefficient tables.

> Hmm can this be worse off? Well definitely FIFO Brams will be needed but it
> certainly be lesser than not using the DRAM right?
> If not, what purpose would the DRAM serve? (which is to store data)

How much data do you need to put in the DRAMs? 60 BRAMs x 2KB each = 120KB 
max., assuming you intended to put everything on the DRAMs. The question 
you really need to ask yourself is: can you afford the glue-logic?

Try ripping the memory controller off any project with DRAM controller you 
may have handy, do an unconstrained implementation run (use a slow clock 
like 50MHz and the memory controller's top as your synthesis project's top) 
and see how resource-hungry the memory controller you have is.

Article: 117568
Subject: Re: high number of multipliers / low cost
From: "Rob" <robnstef@frontiernet.net>
Date: Wed, 04 Apr 2007 11:59:51 GMT
Links: << >>  << T >>  << A >>
Look at the CycloneIII EP3C family that was just released.

<ryan_usenet@yahoo.com> wrote in message 
news:1175686533.726030.62610@d57g2000hsg.googlegroups.com...
> Hello,
> I need the highest possible number of multiplication operations per
> second at low cost. I know that several factors affect the overall
> performance, but since I have no idea which FPGA chips might be worth
> to be considered, I'd like to ask what you think is the chip with the
> lowest ratio
>
> R=(prize of chip)* (delay time)/(number of multipliers)
>
> 18x18bit multipliers seem to be quite common, so lets assume this
> design for the estimate.
>
> For example for the Spartan XC3S1000 (~60$, 24 multipliers, 4ns delay)
> I have
> R= 10$ per (Billion multiplications/s). The Cyclone EP2C70 (~230$, 150
> multipliers, 4ns delay) has R=6.13$ per (Billion multiplications/s).
>
> Do other FPGAs exist that are maybe specialized for multiplication-
> intensive tasks and which therefore are much cheaper?
>
> Best regards,
> Ryan
> 



Article: 117569
Subject: Re: high number of multipliers / low cost
From: "Ben Jones" <ben.jones@xilinx.com>
Date: Wed, 4 Apr 2007 13:11:32 +0100
Links: << >>  << T >>  << A >>

<ryan_usenet@yahoo.com> wrote in message 
news:1175686533.726030.62610@d57g2000hsg.googlegroups.com...
> Hello,
> I need the highest possible number of multiplication operations per
> second at low cost.

Wow, FPGA marketing departments are going to be swarming all over you like 
it's Christmas!

Wait, are you sure you're real...? ;-)

    -Ben-

<removes tongue from cheek> 



Article: 117570
Subject: Re: Can I boot PowerPC without JTAG?
From: "John McCaskill" <junkmail@fastertechnology.com>
Date: 4 Apr 2007 05:25:47 -0700
Links: << >>  << T >>  << A >>
On Apr 4, 4:20 am, "Pablo" <pbantu...@gmail.com> wrote:
> Is it possible to build an application over PowerPC and download to
> board without the use of JTAG?. I have a non Xilinx Board with a
> Virtex II Pro, and at the moment I have not Parallel Cable IV so I use
> an application on the PC to download Bitstream to board. I have probed
> with VHDL designs and all is ok, but when I try to download a PowerPC
> design with a TestApp_Peripheral C Application it seems like powerpc
> doesn't work (doesn't boot). Must I use JTAG? Is it possible to create
> a bootloader or init bram without that cable?
>
> Thanks
>
> Pablo



If you put the TestApp_Peripheral program into BRAMs in the FPGA, you
should not need JTAG to be able to run it. Two things to check are:

Is the linker script set up to locate your program in the BRAMs? On my
system, the default linker script wants to put code in the lowest
memory, which is off chip for me.

Did you run the "BRAM Init" feature of EDK to merge the program into
the FPGA bitstream?  Pay attention to any warnings here. It will tell
you if part of your program is not located in on chip memory.

As for initilizing off chip memory, that depends on your card.  On my
cards, we use a boot loader that is in BRAMs to load the rest of the
software off of a MiniSD card.

Regards,

John McCaskill
www.fastertechnology.com





Article: 117571
Subject: Re: high number of multipliers / low cost
From: Sylvain Munaut <tnt-at-246tNt-dot-com@youknowwhattodo.com>
Date: Wed, 04 Apr 2007 14:28:16 +0200
Links: << >>  << T >>  << A >>
ryan_usenet@yahoo.com wrote:
> Hello,
> I need the highest possible number of multiplication operations per
> second at low cost. I know that several factors affect the overall
> performance, but since I have no idea which FPGA chips might be worth
> to be considered, I'd like to ask what you think is the chip with the
> lowest ratio
> 
> R=(prize of chip)* (delay time)/(number of multipliers)
> 
> 18x18bit multipliers seem to be quite common, so lets assume this
> design for the estimate.
> 
> For example for the Spartan XC3S1000 (~60$, 24 multipliers, 4ns delay)
> I have
> R= 10$ per (Billion multiplications/s). The Cyclone EP2C70 (~230$, 150
> multipliers, 4ns delay) has R=6.13$ per (Billion multiplications/s).
> 
> Do other FPGAs exist that are maybe specialized for multiplication-
> intensive tasks and which therefore are much cheaper?
> 
Look at the Xilinx virtex 5 sxt series

The V5 SX95T for example has 640 multipliers running at 450 MHz. I don't know it's cost, but even if it's 750$ (and it's probably less), that would make R = 2.6 $ per (Billion multiplications/s)

You can also look at the spartan 3A DSP series.
The 3SD3400A costs around 60$ and can do 30 billion multiplication per seconds so that would make R = 2


	Sylvain

Article: 117572
Subject: Re: Help with a face recognition system
From: "Patrick Dubois" <prdubois@gmail.com>
Date: 4 Apr 2007 05:43:42 -0700
Links: << >>  << T >>  << A >>
On Apr 3, 2:00 pm, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote:
> On a sunny day (3 Apr 2007 08:21:24 -0700) it happened "PatrickDubois"
> <prdub...@gmail.com> wrote in
> <1175613684.443163.290...@d57g2000hsg.googlegroups.com>:
>
> >On Apr 3, 8:59 am, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote:
> >> PS3 has only 1 power processor and _6_ SPE cores.
> >>  http://en.wikipedia.org/wiki/PlayStation_3#Central_processing_unit
>
> >Nope, 1 central PPC core and 8 Synergistic Processor Unit:
> >http://www.research.ibm.com/cell/heterogeneousCMP.html
>
> Nope, in the PS3 only 6 are available.

Alright, I don't want to argue about this but I think we can fairly
say that the info on the web is not clear...
Just for fun, here's a link directly from Sony with the PS3 Cell
specs :)
http://cell.scei.co.jp/index_e.html


Article: 117573
Subject: Re: FPGA with 5V and PLCC package
From: "Paul" <pauljbennett@gmail.com>
Date: 4 Apr 2007 05:48:11 -0700
Links: << >>  << T >>  << A >>
Hebert,

   As a recent student myself (been doing FPGA design for 2 years now)
I've gotta say....  HDL.

   Actual FPGA design flow, in the real world, is

Preliminary Design - Block Diagrams
Detailed Desgin - HDL
Verification - HDL

In terms of getting an idea of how many flops and gates (you said they
should be able
to get an idea for the scale of the design) all you have to do is not
allow
them to use high level constructs.

A <= B AND C;

1 line of code = 1 gate.....

That would make them go through the labor of explicitly understanding
every single gate, but yet expose them to something they might
actually
use in their career - something they can build off of in future
classes or a future
job.

I took a intro digital design class.... we learned carnot maps and the
rest of it...
next semester, the professor for the advanced class tells us "You'll
never actually
use any of that - the synthesizer will do all that for you... and
given the architecture
of the logic device you're using the fully reduced function is not
always the most
efficient, because that 4 input LUT is there whether you use it or
not"  Sure enough
take a quick when the last time I used a carnot map was... I wouldnt
remember how.
The one lesson learned from that first class "Logic is reducable" the
reality learned in the
second class "your design tools will do that for you".  There was a
very good reason why the
first class did NOT have a lab associated with it... cause making us
hook up discrete AND and
OR gates in DIP packages would have zero bearing on our careers.  The
second class
had a GREAT lab associated with it that used a Virtex2.

At any rate... just the opinion of a recent student.  If you can't
teach everything you need to
in HDL, then you need to go back and learn HDL a littler better.





On Mar 21, 6:22 am, Herbert Kleebauer <k...@unibwm.de> wrote:
> Symon wrote:
> > If it's OK, I have an observation. I wonder why these students are being
> > taught design methods on design tools and FPGA parts that most folks on this
> > newsgroup haven't used for a long time. The schematic vs. HDL wars have long
> > since died down because modern FPGA designs are generally 'better'
> > implemented using HDLs.
>
> This is an exercise to a lecture about computer organization. The student
> have just learned how to make a truth table, minimize logic functions and
> design simple state machines. In this exercise they should use this
> knowledge to implement a little bit more complex design. And what
> can be more interesting than designing your own CPU. Therefore VHDL
> isn't any alternative, they are only allowed to use D-FF's and simple
> gates like AND,OR,NAND,NOR. We could stop the course after simulating
> the design, but it is much more motivating when at the end your CPU
> is running in hardware. But this hardware has to be a simple hardware
> (not one of this complex multilayer FPGA prototyping boards) so they
> see that there is no hidden technology and they even could make the
> same board at home with an cheap soldering iron.
>
> > p.s. I HATE Viewlogic. I wasted a day on a legacy design a while back
> > because a wire had the wrong shaped dot on it. The worst part was the bloody
> > software guy spotted the mistake!
>
> Maybe you didn't use the DOS version. I suppose this software
> was made by hardware engineers to support there work. An it
> was so good that other people also wanted it. But with the
> success of the tool the company hired software engineers and
> these people can destroy any perfect usable SW in nearly no
> time. I installed the Windows version of WorkView when it was
> available, but after testing immediately deleted it. The
> same happened a few years before with the Daisy CAD system.



Article: 117574
Subject: Re: re-assemble bootloader for NIOS Processor
From: "Dolphin" <Karel.Deprez@gemidis.be>
Date: 4 Apr 2007 06:33:35 -0700
Links: << >>  << T >>  << A >>
Hello,

I have no experience with make files. Can you tell me which software I
have to use and how to run the make file?

thanks and best regards,
Karel




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