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Messages from 117750

Article: 117750
Subject: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
From: CBFalconer <cbfalconer@yahoo.com>
Date: Mon, 09 Apr 2007 17:00:52 -0400
Links: << >>  << T >>  << A >>
johnp wrote:
> 
... snip ...
> 
> Yes, you can also force the start of a new packet using the PKTEND
> pin, but your USB bandwidth may suffer since you will be sending
> short packets.

Please do not top-post.  Your answer belongs after (or intermixed
with) the quoted material to which you reply, after snipping all
irrelevant material.  See the following links:

-- 
  <http://www.catb.org/~esr/faqs/smart-questions.html>
  <http://www.caliburn.nl/topposting.html>
  <http://www.netmeister.org/news/learn2quote.html>
  <http://cfaj.freeshell.org/google/>  (taming google)
  <http://members.fortunecity.com/nnqweb/>  (newusers)


-- 
Posted via a free Usenet account from http://www.teranews.com


Article: 117751
Subject: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
From: "johnp" <johnp3+nospam@probo.com>
Date: 9 Apr 2007 14:23:58 -0700
Links: << >>  << T >>  << A >>
Cypress has some notes on using PKTEND.  I don't recall all
the details, but I believe you need to be careful not to assert
it if the fifo_full flag for the fifo is active.

John Providenza


On Apr 9, 10:54 am, "johnp" <johnp3+nos...@probo.com> wrote:
> We've used the FX2 on multiple projects with FPGAs.
>
> The FX2 delivers a stream of data bytes to the host, from the
> hosts perspective, it hasn't a clue if the external FX2 bus is
> 8 or 16 bits.  As long as the transfer lengths are an even
> number of bytes and your FPGA code properly converts your
> internal 16/32/48 bit data into a byte stream, you should
> have no problems.
>
> Yes, you can also force the start of a new packet using the PKTEND
> pin, but your USB bandwidth may suffer since you will be sending short
> packets.
>
> John Providenza
>
> On Apr 9, 10:02 am, cs_post...@hotmail.com wrote:
>
> > Any Cypress FX2 (USB) gurus out there?
>
> > I have one of these devices on an FPGA board (Digilent Nexys), which
> > only provides an 8-bit external datapath instead of 16 bits.  I'd like
> > to stream substantially wider words (32, maybe 48 bit) to a PC
> > application.
>
> > Could anyone provide some clarity on what mechansims exist to
> > synchronize the byte-wide data to application word boundries?  Is
> > there something I can do to insure that each USB packet begins on a
> > word boundary?
>
> > The boundry locations are readily available to the FPGA code, the
> > question is how to communicate that information to the USB engine - is
> > there a way to force creation of a new packet?
>
> > Obviously in-band signalling for data framing remains an option, but I
> > would very much like to avoid resorting to that.
>
> > Thanks for any ideas - I haven't given up on figuring this out from
> > the data sheets & manuals, but given their length it's not going
> > quickly.



Article: 117752
Subject: Re: MGT Clocking
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Mon, 09 Apr 2007 14:44:32 -0700
Links: << >>  << T >>  << A >>
Matthew Hicks wrote:
> I am currently trying to free-up some DCMs for use in other parts of our 
> design, so I am trying to make some MGTs share DCM outputs.  Currently I 
> have one DCM per each of the eight MGTs which uses all of our DCMs.  For 
> reference, we are on a Virtex II-pro trying to communicate at a rate of 
> 2.5Gbs in two-byte mode.  Xilinx document UG024 talks about a case where 
> no DCMs are needed at all, but it isn't clear on when this solution is 
> suitable (pg. 46).  I thoguht we may at least be able to use one DCM for 
> the top four MGTs and another for the bottom four.  Any thoughts or 
> experiences related to this issue or clocking MGTs on a Virtex II in 
> general would be appreciated.
> 

If the 8 MGTs are all running from the same reference clock source
then you only need one DCM+BUFGs circuit to drive all of the TX and
RX user clocks in the device.  The only use for individual DCMs is
if they are running on different clocks.

Ed McGettigan
--
Xilinx Inc.

Article: 117753
Subject: record type port in vhdl and simulation in ISE
From: "mans" <(use_my_name_here)-34@blueyonder.co.uk>
Date: Mon, 09 Apr 2007 22:27:27 GMT
Links: << >>  << T >>  << A >>
Hello,

   I have an entity in VHDL that one of its ports is a record type. I am 
trying to create a test bench wave form to test the code but when ISE 
creating a test bench; it doesn't create the wave form for records. What is 
the problem and how can I solve it?



Regards



Article: 117754
Subject: Re: record type port in vhdl and simulation in ISE
From: Mike Treseler <mike_treseler@comcast.net>
Date: Mon, 09 Apr 2007 15:51:31 -0700
Links: << >>  << T >>  << A >>
mans wrote:

>    I have an entity in VHDL that one of its ports is a record type. I am 
> trying to create a test bench wave form to test the code but when ISE 
> creating a test bench; it doesn't create the wave form for records. What is 
> the problem and how can I solve it?

I would write my own testbench.
The alternative is to change the port types
or talk to Xilinx.

            -- Mike Treseler

Article: 117755
Subject: Re: raggedstone + xc3sprog? (solution and PHY question)
From: Adam Megacz <megacz@cs.berkeley.edu>
Date: Mon, 09 Apr 2007 15:54:48 -0700
Links: << >>  << T >>  << A >>

"John Adair" <g1@enterpoint.co.uk> writes:
> You have not missed anything. The inner pins are for an enhancement of
> the DIL headers where we have inner strips with power pickup allowing
> easier use of multiple modules in a single header.  If you plug in the
> module at the top of the header the the top left and right of the
> header are 0V and 3.3V respectively.

Just to confirm that I understand correctly: to attach the EtherPHY to
the Raggedstone1, I should plug it in such that the pin marked "J1" on
the PHY goes in the hole marked "Y21" on the Raggedstone.

Is this correct?

Thanks again for all your help!

  - a

Article: 117756
Subject: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
From: "John_H" <newsgroup@johnhandwork.com>
Date: Mon, 9 Apr 2007 16:27:54 -0700
Links: << >>  << T >>  << A >>
Your opinion - as those of many who came before you - is noted.  Too often 
when a thread is active, it makes more sense and is more readable to 
top-post.  Most often bottom posting is preferred.  We occasional top 
posters are sorry for the inconvenience posed to occasional users of this 
forum.


"CBFalconer" <cbfalconer@yahoo.com> wrote in message 
news:461AA984.1D385631@yahoo.com...
> johnp wrote:
>>
> ... snip ...
>>
>> Yes, you can also force the start of a new packet using the PKTEND
>> pin, but your USB bandwidth may suffer since you will be sending
>> short packets.
>
> Please do not top-post.  Your answer belongs after (or intermixed
> with) the quoted material to which you reply, after snipping all
> irrelevant material.  See the following links:
>
> -- 
>  <http://www.catb.org/~esr/faqs/smart-questions.html>
>  <http://www.caliburn.nl/topposting.html>
>  <http://www.netmeister.org/news/learn2quote.html>
>  <http://cfaj.freeshell.org/google/>  (taming google)
>  <http://members.fortunecity.com/nnqweb/>  (newusers)
>
>
> -- 
> Posted via a free Usenet account from http://www.teranews.com
> 



Article: 117757
Subject: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
From: cs_posting@hotmail.com
Date: 9 Apr 2007 21:12:00 -0700
Links: << >>  << T >>  << A >>
On Apr 9, 4:00 pm, CBFalconer <cbfalco...@yahoo.com> wrote:

As the original poster I was quite happy to have johnp's helpful
answer, wherever
(continued below)

> > Yes, you can also force the start of a new packet using the PKTEND
> > pin, but your USB bandwidth may suffer since you will be sending
> > short packets.
>
> Please do not top-post.  Your answer belongs after (or intermixed
> with) the quoted material to which you reply, after snipping all
> irrelevant material.  See the following links:
>
> --
>   <http://www.catb.org/~esr/faqs/smart-questions.html>
>   <http://www.caliburn.nl/topposting.html>
>   <http://www.netmeister.org/news/learn2quote.html>
>   <http://cfaj.freeshell.org/google/>  (taming google)
>   <http://members.fortunecity.com/nnqweb/>  (newusers)
>
> --
> Posted via a free Usenet account fromhttp://www.teranews.com

he felt like putting it!


Article: 117758
Subject: Re: ISE on Fedora?
From: "M E" <boyscout@gmail.com>
Date: 9 Apr 2007 21:32:03 -0700
Links: << >>  << T >>  << A >>
On Apr 2, 1:28 am, "G=FCnther Jehle" <j...@gmx.at> wrote:
> I had a problem that was quite similar. Check if you have turned off
> SELinux. Use "setenforce 0" for temporary disable.
>
> regards
>   G=FCnther


Looks like that fixed it!  Thanks!  But it's kind of strange that a
user mode program, running as a normal user, with no need to access
hardware, would run afoul of SELinux...

Matt


Article: 117759
Subject: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 9 Apr 2007 22:03:24 -0700
Links: << >>  << T >>  << A >>
Hi, John. You caught the wrath of the Top-Poster Secret Police, TPSP.
Your name (and mine) will be entered into the national TPSP registry,
and will be distributed, together with the names of child-molester, to
all police stations and airport screening places. Soon we will not be
able to fly, our passports will be revoked, and our credit cards will
be confiscated. Top Posting is just the first step on a carreer of
crime, leading inevitably to mayhem and murder.
The TPSP has to protect the country from such beginnings...

"Give me liberty or give me death !"
Peter Alfke

On Apr 9, 2:00 pm, CBFalconer <cbfalco...@yahoo.com> wrote:
> johnp wrote:
>
> ... snip ...
>
> > Yes, you can also force the start of a new packet using the PKTEND
> > pin, but your USB bandwidth may suffer since you will be sending
> > short packets.
>
> Please do not top-post.  Your answer belongs after (or intermixed
> with) the quoted material to which you reply, after snipping all
> irrelevant material.  See the following links:
>
> --
>   <http://www.catb.org/~esr/faqs/smart-questions.html>
>   <http://www.caliburn.nl/topposting.html>
>   <http://www.netmeister.org/news/learn2quote.html>
>   <http://cfaj.freeshell.org/google/>  (taming google)
>   <http://members.fortunecity.com/nnqweb/>  (newusers)
>
> --
> Posted via a free Usenet account fromhttp://www.teranews.com



Article: 117760
Subject: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
From: Donald <Donald@dontdoithere.com>
Date: Mon, 09 Apr 2007 23:17:19 -0700
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> The TPSP has to protect the country from such beginnings...
> 
> "Give me liberty or give me death !"
> Peter Alfke

Not to worry, Mother CBFalconer's bark is worse then his bite.

donald

Article: 117761
Subject: File open, read and write in Xilinx EDK 7.1
From: "Andy" <acetracerbullet1000@hotmail.com>
Date: 9 Apr 2007 23:23:42 -0700
Links: << >>  << T >>  << A >>
Hi,

Iam writng a c code in Xilinx EDK 7.1 and am having problems with the
fopen construct. Iam trying to read data from a text file, process it
and then write it back. I read the documentation and found that xilinx
provides read, write and open in xilfile. However, simply including
the xilfile.h and checking the xilfile option in the software platform
settings gives me errors. Any sample code or instructions on how to
open, read and write a file in EDK would be helpful.

Thanks
Andy


Article: 117762
Subject: Re: ISE on Fedora?
From: Eric Smith <eric@brouhaha.com>
Date: 09 Apr 2007 23:31:24 -0700
Links: << >>  << T >>  << A >>
"M  E" <boyscout@gmail.com> writes:
> I am running Fedora 6, and I am having trouble installing ISE
> WebPack.  When I run the setup program it tells me that I don't have
> the right version of libstdc++, so I installed the compat-libstdc++
> package.  Now when I run setup, the program just quits immediately,
> with no error message at all.
> 
> Anybody have any ideas?

Are you running the x86_64 (64-bit) Fedora?  If so, the WebPack
startup scripts are trying to run 64-bit binaries (lin64 directory),
which doesn't exist in WebPack.  I had to edit the settings.sh file
to force PLATFORM=lin.

Eric

Article: 117763
Subject: Re: EDK 9.1i installation
From: Eric Smith <eric@brouhaha.com>
Date: 09 Apr 2007 23:36:44 -0700
Links: << >>  << T >>  << A >>
Svenand <> writes:
> Is EDK9.1i a free upgrade if you have EDK8.1 installed and does anyone
> know where it can be found.

If your EDK 8.1 license has not expired (1 year from purchase), you
should be able to download EDK 9.1 from the Xilinx web site.  Click
the "download" link.  You'll have to log in.

If your EDK 8.1 license has expired, you'll have to buy a new one.
I need to do that myself soon; I'll probably buy the Spartan 3E
Microblaze kit, which apparently includes the EDK.

Eric

Article: 117764
Subject: Re: Problem with PHY clocks on Spartan 3E Starter Kit
From: Eric Smith <eric@brouhaha.com>
Date: 09 Apr 2007 23:42:23 -0700
Links: << >>  << T >>  << A >>
"roger" <roger.jons@gmail.com> writes:
> I made a simple counter which flashes a led in 2 Hz using first the TX
> clock from the PHY as the clock input and then the RX clock as the
> clock input. When I'm using the TX clock everything works fine and
> when I'm using the RX clock I get no activity at all. I have verified
> that I have  a clock output from the PHY using an oscilloscope.

Doesn't the RX clock only appear while a frame is being received?
That was how many of the lower-speed PHY interfaces worked, but I'm not
sure about MII.

Article: 117765
Subject: Re: Clocking data into a shift register on positive AND negative edges
From: Eric Smith <eric@brouhaha.com>
Date: 09 Apr 2007 23:55:52 -0700
Links: << >>  << T >>  << A >>
Philip Pemberton <usenet07@philpem.me.uk> writes:
>    I'm trying to design a floppy disc 'raw reader' (to archive discs
> that have been written in unusual formats that PCs can't read). I've
[...]
> Now the problem I have is that in Verilog (or at least Xilinx ISE8.1
> Verilog) you can't trigger on both a positive and negative edge of a
> signal - the language allows it, but ISE complains that it can't find
> a matching 'FF or latch template' (error code Xst:899).
[...]
> or is there an easier (or just another) way to do this?

Yes.  I've done something similar, and you don't need any double-edge
clocking for that.

Put two FFs in series, clocked by a free-running oscillator
(perhaps 25 MHz or higher).  XOR the outputs together.  Now you get
a pulse one clock cycle wide every time the data line changes.

If you also have a free running counter on the same clock, you can
use the "changed" signal as a clock enable for a register to record
the time that the data line changed, or push it into a FIFO.

For a floppy (or an ST506/412 interface Winchester, or the like), you
don't actually need both edges, as only the leading edge of the data
pulse is related to the flux transition on the disk.  (The floppy drive uses
a one-shot to generate a pulse for each detected flux transition.)
Therefore instead of an XOR, you can use an AND gate and an inverter to
detect only transitions in the direction of interest.

Article: 117766
Subject: is there any opensource alternatives to platformstudio and microblaze development?
From: "CMOS" <manusha@millenniumit.com>
Date: 10 Apr 2007 01:10:08 -0700
Links: << >>  << T >>  << A >>
is there any opensource alternatives to platformstudio and microblaze
development?


Article: 117767
Subject: Re: raggedstone + xc3sprog? (solution and PHY question)
From: "John Adair" <g1@enterpoint.co.uk>
Date: 10 Apr 2007 02:49:23 -0700
Links: << >>  << T >>  << A >>
Adam

Not quite, the top pin of the outer run of J1 plugs into 0V and is the
ground pin for the module on the older style DIL headers on the
current Raggedstone1. The Y21 etc marked on board next to the headers
are the pin numbers of the FPGA that the adjacent DIL pin connects to.
It makes making up a UCF a bit easier as you don't have to wade
through schematcs.

Schematics for the Ethernet Phy module are located here
http://www.enterpoint.co.uk/moelbryn/modules/ethernet_phy.html and
will give you the module pinout.

John Adair
Enterpoint Ltd.

On 9 Apr, 23:54, Adam Megacz <meg...@cs.berkeley.edu> wrote:
> "John Adair" <g...@enterpoint.co.uk> writes:
> > You have not missed anything. The inner pins are for an enhancement of
> > the DIL headers where we have inner strips with power pickup allowing
> > easier use of multiple modules in a single header.  If you plug in the
> > module at the top of the header the the top left and right of the
> > header are 0V and 3.3V respectively.
>
> Just to confirm that I understand correctly: to attach the EtherPHY to
> the Raggedstone1, I should plug it in such that the pin marked "J1" on
> the PHY goes in the hole marked "Y21" on the Raggedstone.
>
> Is this correct?
>
> Thanks again for all your help!
>
>   - a



Article: 117768
Subject: Why I cannot use the XAUI core(generated by xilinx)
From: "mynewlifever@yahoo.com.cn" <mynewlifever@yahoo.com.cn>
Date: 10 Apr 2007 03:23:09 -0700
Links: << >>  << T >>  << A >>
I use COREGEN to generate XAUI(choose device Virtex5 110t), but I
cannot do simulation with modelsim6.1f. It is always reporting the
following error. I think maybe there is something in modelsim needed
to set. Please to help me. Thank you!

vsim work.testbench
# Loading d:\Xilinx91i\smartmodel\nt\installed_nt/lib/pcnt.lib/
swiftpli_mti.dll
# ** Error: (vsim-3193) Load of "d:\Xilinx91i\smartmodel\nt
\installed_nt/lib/pcnt.lib/swiftpli_mti.dll" failed: DLL
dependent library not found.
# ** Error: (vsim-PLI-3002) Failed to load PLI object file


Article: 117769
Subject: C/C++ for hardware (from "Re: Embedded languages based on early Ada (from "Re: Preferred OS, processor family for running embedded Ada?")")
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: 10 Apr 2007 10:31:57 GMT
Links: << >>  << T >>  << A >>
In news:uy7ma9wdw.fsf@trw.com timestamped Tue, 06 Mar 2007 16:20:27
+0000, Martin Thompson <martin.j.thompson@trw.com> posted:
"Colin Paul Gloster <Colin_Paul_Gloster@ACM.org> writes:

> I am unhappy that electronic engineers are very eager to try
> to transfer things which are unsuitable for software to hardware for
> which they are also unsuitable, e.g. C++ and UML.

That sounds like one for the .sig file!"


Thank you, I aim to please!

Prof. Giovanni De Micheli said on April 2nd, 2007 while lecturing: "I
invented HardwareC a few years ago" and after he presented two slides
after that clause he said: "Java is a great language, I like it. It's
cleaner than C/C++, but that's life." He said that C has an advantage
over VHDL because code might initially be targeted to a processor but
be migrated to hardware elsewhere in the system if the attempt on the
processor does not perform well enough.

In contrast to what is quoted above which he used his voice to say, he
showed in writing more than one slide of his promoting the SystemC(R)
approach as being good. E.g. "Processes run concurrently". I asked
whether he had tried to convey that SystemC(R) code genuinely,
literally runs concurrently. He answered that he did mean that
literally, but he admitted that in practice SystemC(R) implementations
do not run concurrently. He clarified that he was convinced that the
SystemC(R) standard was written in terms of concurrency. During a
lunch break I challenged this again (this time by email: see below): I
did not receive a response from him yet but an organizer of the
lecture sent the response below.

Regards,
Colin Paul Gloster


On Mon, 2 Apr 2007, someone wrote with Subject field: "Re:
SystemC(R) concurrency, or lack thereof":

"Dear Colin Paul,

please try to address questions to Prof. De Micheli personally just
after the
lecture or during the break. This will avoid any form of
misunderstanding
without bothering Prof. De Micheli via email. Could you imagine if all
the
students would start  sending questions to Prof. De Micheli via email
?

The presence of Prof. De Micheli is a great opportunity for all the
students
attending the course so please try to avoid asking too many questions
during the lecture in order for Professor De Micheli to have the
possibility to
address all the topics he originally planned for the course.

Thanks a lot for your understanding.

Best Regards, [..]


----- Original Message ----- From: "Colin Paul Gloster"
<Colin_Paul_Gloster@ACM.org>
To: <giovanni.demicheli[..]>
Cc: [.. some of the students who had been exposed to propaganda by the
lecturer, and also a carbon copy to the organizer]
Sent: Monday, April 02, 2007 2:05 PM
Subject: SystemC(R) concurrency, or lack thereof


> Dear Professor Giovanni De Micheli,
>
> You said on a number of occassions during one of the lectures today
that
> SystemC(R) multiprogramming is concurrent. I asked you whether you
meant that
> literally, to which you replied that you did literally mean that but
that
> implementations might use interleaved serial code instead of
parallel code but
> that you believed that the SystemC(R) definition is concurrent.
>
> I completely reject your claim that the SystemC(R) library is
defined to be
> concurrent. Please explain to me how I have misinterpreted the
definition of
> the scheduling policy of the SystemC(R) standard's as described in
4.2.1 The
> scheduling algorithm of the standard:
> "The semantics of the scheduling algorithm are defined in the
following
> subclauses.
> [..]
> An implementation may substitute an alternative scheme, provided the
> scheduling
> semantics given here are retained.
> [..]
> 4.2.1.2 Evaluation phase
> From the set of runnable processes, select a process instance and
trigger or
> resume
> its execution. Run the process instance immediately and without
interruption
> up to
> the point where it either returns or calls the function wait.
> Since process instances execute without interruption, only a single
process
> instance
> can be running at any one time, and no other process instance can
execute
> until the
> currently executing process instance has yielded control to the
kernel. A
> process shall
> not pre-empt or interrupt the execution of another process. This is
known as
> co-routine
> semantics or co-operative multitasking.
> [..]
> A process may call the member function request update of a primitive
channel,
> which will cause the member function update of that same primitive
channel to
> be
> called back during the very next update phase.
> Repeat this step until the set of runnable processes is empty, then
go on to
> the
> update phase.
> NOTE 1-The scheduler is not pre-emptive. An application can assume
that a
> method process will execute in its entirety without interruption,
and a thread
> or clocked
> thread process will execute the code between two consecutive calls
to function
> wait
> without interruption.
> [..]
> NOTE 3-An implementation running on a machine that provides hardware
support
> for concurrent processes may permit two or more processes to run
concurrently,
> provided that the behavior appears identical to the co-routine
semantics
> defined in
> this subclause. In other words, the implementation would be obliged
to analyze
> any
> dependencies between processes and constrain their execution to
match the
> co-routine
> semantics."
>
> Thanks,
> Colin Paul Gloster
>
> P.S. Other parts of the lecture were interesting."

Article: 117770
Subject: VIrtex-4 FIFO16
From: "=?utf-8?B?R2FMYUt0SWtVc+KEog==?=" <taileb.mehdi@gmail.com>
Date: 10 Apr 2007 03:33:45 -0700
Links: << >>  << T >>  << A >>
Hi everybody,
In the new version (2.1) of the Virtex-4 User Guide (ug070), in the
FIFO chapter is described the synchronous clock work-around (page 161)
to solve the FIFO bug. At the end of the paragraph the following is
written: "The connections between the input registers and the FIFO16
must be tightly constrained, as this part of the circuit effectively
runs at  twice the clock rate."
Can anybody explain me which contraints are needed? placement? timing?
an example is wellcome!

Thanks
Mehdi


Article: 117771
Subject: Newbie with bus width mismatch problem. Quartus II
From: "PeterK" <meltyb@hotmail.com>
Date: Tue, 10 Apr 2007 11:39:48 +0100
Links: << >>  << T >>  << A >>
Dear Altera experts,

My very first project is a PWM in Quartus II 7.0. I've drawn up a block 
diagram with a 17 bit lpm_counter going into a 5 bit lpm_compare. All I want 
is the top five bits of the counter to go into the comparator. After several 
days of trying I still have no idea how to split the 17 bits to just use the 
top five bits. With a normal bus connection it compiles with a Width 
mismatch error.

Peter 



Article: 117772
Subject: SetJmp/LongJmp for Microblaze
From: "Pablo" <pbantunez@gmail.com>
Date: 10 Apr 2007 03:46:23 -0700
Links: << >>  << T >>  << A >>
Does anybody use Setjmp.h for Microblaze?. I have to use this library
but something is wrong, so I have decided to open smtjmp.h and I have
seen that there is no definition for Microblaze. Does anyone use this
library?Does I must define some flag to compile?

Thanks.


Article: 117773
Subject: Re: SetJmp/LongJmp for Microblaze
From: "Jon Beniston" <jon@beniston.com>
Date: 10 Apr 2007 05:35:51 -0700
Links: << >>  << T >>  << A >>
It will either be in the newlib/libgloss source code or built in to
GCC.

Alternatively, just disassemble a program that uses it.

Cheers,
Jon


Article: 117774
Subject: Re: is there any opensource alternatives to platformstudio and microblaze development?
From: "Gabor" <gabor@alacron.com>
Date: 10 Apr 2007 06:02:10 -0700
Links: << >>  << T >>  << A >>
On Apr 10, 4:10 am, "CMOS" <manu...@millenniumit.com> wrote:
> is there any opensource alternatives to platformstudio and microblaze
> development?


Do you want open source for microblaze development specifically?
Or opensource for any open source 32-bit embedded micro?

Lattice Mico32 development might fit the bill for the second...




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