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Messages from 115075

Article: 115075
Subject: Re: USB 2.0 Streaming using FPGAs
From: "Will Dean" <will@nospam.demon.co.uk>
Date: Tue, 30 Jan 2007 17:46:27 -0000
Links: << >>  << T >>  << A >>
"johnp" <johnp3+nospam@probo.com> wrote in message 
news:1170169040.672601.99810@m58g2000cwm.googlegroups.com...
>
> I hope someone has expererience (and tips) that show me to be wrong!

I would expect to be able to do data OUT in the high 30s of MB/s without 
much problem but you do need to do big writes, and probably have lots of 
them overlapped and queued.

Of course there's always the possibility that part of your USB capacity has 
been reserved by interrupt or isoch devices, too.

Like you, I find that the FX2 can require a fair amount of sweat and tears 
to get it working, though I have done enough different products with it now 
that I can usuaully find a reasonably example of how to set it up...

Anybody who needs an absolutely unstoppable stream of data at 480MB/s should 
certainly be avoiding a general-purpose desktop OS running a bus at 100% of 
its theoretical capacity.

Will 



Article: 115076
Subject: Re: How to perform a boundary scan test BEFORE configuration on Spartan-3 Starter Board ?
From: "davide" <davide@xilinx.com>
Date: Tue, 30 Jan 2007 09:46:54 -0800
Links: << >>  << T >>  << A >>
Well, the simplest way to verify that the Spartan device was configured 
properly is to monitor the DONE pin.  Is it high?  You can also generate a 
mask file and do a verify after configuration.  There are other methods such 
as readback, but lets start with some basics for now.  Check out the iMPACT 
Users Guide for more details or the Spartan-3 Configurations Users Guide:
http://toolbox.xilinx.com/docsan/xilinx9/help/iseguide/mergedProjects/plugin_imp/plugin_imp.htm
http://direct.xilinx.com/bvdocs/userguides/ug332.pdf

-David

"BODDU Lokesh" <lokesh.boddu@gmail.com> wrote in message 
news:eea0f0e.1@webx.sUN8CHnE...
> hi
>
> how to perform a boundary scan test after the FPGA is configured or in 
> other words how do i know that the FPGA is configured properly
>
> Thanks and Regards Lokesh BODDU 



Article: 115077
Subject: Re: USB 2.0 Streaming using FPGAs
From: "billu" <bkamakot@gmail.com>
Date: 30 Jan 2007 09:49:26 -0800
Links: << >>  << T >>  << A >>
Thx for everyones input.

It looks like the PC is going to be the real bottleneck in the whole 
setup. So assuming a maximum data rate of around 240 Mbits/sec, whats 
the best way to interface the PC data stream with the SMA interface. 
This is what came to my mind. Cypress FX2 board takes in a data stream 
from the PC, and the slave fifo interface sends the data to the FPGA. 
The FPGA takes in the data and sends it out through the SMA MGTs. Is 
this reasonable? Any pointers on working with FX2-FPGA board setups. 
Can a Xilinx ML321 board be used?

As far as requirements:
  * Throughout: Maximum possible data rate
  * Latency: Would like it to be small, but not critical
  * Ease of use: Somewhat important, but not the driving factor
  * Ubiquity: Again somewhat important, b/c we would like to 
communicate between PC-PC or PC-Smartphone using a USB port.

Really appreciate everyones response.

On Jan 30, 10:47 am, Tim <s...@nooospam.roockyloogic.com> wrote:
> johnp wrote:
> >>From my experience, the maximum data rate should plan for on the USB
> > is
> > 25 to 30 MB/sec, ie, 240 Mbits/sec.  This is far below the 480Mb raw
> > data
> > rate, but I think it's hard to get a lot better than this given the s/
> > w driver
> > overhead, etc.And the Windows XP latency can be several seconds.
>
> --
> Tim


Article: 115078
Subject: Re: 1 Gbps - state of the art?: PCIe is 2.5Gb/s, and PCIe V2.x will
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 30 Jan 2007 09:54:45 -0800
Links: << >>  << T >>  << A >>
Geronimo,

10 Gb/s electrical, or optical is not unusual, and even has been
standardized for many uses (ie SONET/STH OC-192).

Using wavelength division multiplexing there are commercial optical
systems with n times 10 Gb/s channels (each to its own color).

Nothing even fancy here.  ON/OFF keying of the laser diode.  Perhaps as
much as ten years old now.

10 Gb/s electrical is challenging, as you need to transmit the signal
the required distance without loss, noise, reflections, phase
distortion.  That means perhaps 10 meters maximum with exotic material,
exotic electronics; and only a half a meter or less using regular
printed circuit boards and less exotic circuits.

PCI Express is a new standard that now is in every backplane of every
new PC, and offers up to 16 2.5 Gb/s channels.  If that isn't "proof" of
a technology gaining a hold, I don't know what is.

In fact, there are so many applications from 622 Mb/s to ?? Mb/s that it
is difficult to keep track of all of them.

A suggested set of solutions for many of these standards:

http://direct.xilinx.com/bvdocs/userguides/ug196.pdf

and

http://direct.xilinx.com/bvdocs/userguides/ug197.pdf

for PCIe.

You will note all these standards use simple ON/OFF electrical keying,
with no complex signal modulation.  Transmit symbol pre-shaping, and
receive signal equalization is used to maintain the eye opening in most
devices running higher than 3 Gb/s.  Run length codes are used to
prevent long strings of zeroes or ones from being a challenge to IC
designers (8b10b, 64b66b).

Just one more reason why you tend to find a Xilinx FPGA inside just
about every box nowadays.

Austin

Article: 115079
Subject: how does z-transforms (basically the mathematical techniques in designing digital systems) map with FPGA implementations
From: "CMOS" <manusha@millenniumit.com>
Date: 30 Jan 2007 10:07:11 -0800
Links: << >>  << T >>  << A >>
hi,

how does z-transforms (basically the mathematical techniques in 
designing digital systems) map with
FPGA implementations. is there a systamatic flow that is used in the 
industry when implementing a  given algorythm in verilog/VHDL.

thank you


Article: 115080
Subject: Re: 1 Gbps - state of the art?
From: PeteS <peter.smith8380@ntlworld.com>
Date: Tue, 30 Jan 2007 18:10:32 GMT
Links: << >>  << T >>  << A >>
Geronimo Stempovski wrote:
> Hi all,
> 
> I wonder what is curently state-of-the art in serial high-speed transmission 
> and what are the prevailing data rates? I know about some SerDes in the 
> gigabit-per-second range but I cannot imagine if 10 Gbps are really a 
> challenge or the applied method or if it's 1 Gbps (or something in 
> between)...?
> I recently heard about some 60 GHz in the mobile communication sector and 10 
> Gbit Ethernet but as far as I know there are those multi-level modulation 
> methods (like QAM for example) that are able to provide 10 Gbit bandwidth 
> with a bitrate of some Mbps (is that correct?).
> I'm not interested so much in those higher modulation methods (nor in 
> optical transmission) but in the baseband communication where bitrate = 
> clockrate, i.e. the line rate. What can be efficiently transmitted today 
> electrically (over wire or PCB)? What is the prevailing technology of those 
> circuits, is it CMOS or are there alternatives?
> I am a senior electrical engineer and unfortunately did not manage to keep 
> up-to-date. After googling all night I'm really depressed because I finally 
> couldn't find an unambiguous answer.
> Maybe some guys in the silicon-business or practitioners know the anser and 
> are willing to share there knoledge with me?
> 
> Best regards
> Geronimo 
> 
> 

In terms of bitrates, then I designed a board with serial links at 5Gb/s 
*per pair* a couple of years ago. Before that I designed some switches 
and gateways with 2.5Gb/s pairs (lots and lots of them). PCI Express has 
just released the 5Gb/s signalling revision (within the last month or 
so, I believe). The things I designed a few years ago were Infiniband 
(my name is actually one of many on the latest spec).

Over FR4 (or other materials less than totally exotic) 5Gb/s is about 
the most you'll get except for _very_ short runs, and as Joel notes 
everything's a transmission line at those rates. I've seen 2.5Gb/s 
Infiniband on a 4x cable (4 pairs in each direction) achieve 10 metres 
within the signalling budget. At 5Gb/s things are more difficult.

10G ethernet is actually 4 signals, incidentally.

So state of the art in terms of practical, shipping and costs less than 
a trip to the moon is currently in the 5Gb/s per pair range.

Cheers

PeteS

Article: 115081
Subject: Re: how does z-transforms (basically the mathematical techniques in designing digital systems) map with FPGA implementations
From: Derek <derekp@xilinx.com>
Date: Tue, 30 Jan 2007 10:40:17 -0800
Links: << >>  << T >>  << A >>
CMOS, This is a very broad topic. I'd suggest you read the following article from a recent Xilinx magazine. <http://www.xilinx.com/publications/magazines/dsp_02/xc_pdf/p45-47_2dsp-avnet.pdf> Regards,

Derek

Article: 115082
Subject: Re: 1 Gbps - state of the art?
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 31 Jan 2007 07:48:57 +1300
Links: << >>  << T >>  << A >>
PeteS wrote:
> 
> In terms of bitrates, then I designed a board with serial links at 5Gb/s 
> *per pair* a couple of years ago. Before that I designed some switches 
> and gateways with 2.5Gb/s pairs (lots and lots of them). PCI Express has 
> just released the 5Gb/s signalling revision (within the last month or 
> so, I believe). 

Latest boasting on this is here
http://www.altera.com/corporate/news_room/releases/products/nr-pcie2.html?f=hp&k=wn2

and here

http://www.xilinx.com/prs_rls/2007/silicon_vir/0706_V5PCIe-compliance.htm

I presume there _is_ some important BER threshold to set the distance, 
and that this fluff is marketing's effort :

".. reliably transmit data over an unprecedented 30 m "

- how 'reliably' exactly ? - giving a distance without any error rate is
getting a bit slack...

I also see they spec thus "5-GT/s PCIe 2.0 specification"

( Transistions per second )which seems more sensible than Gbps.

-jg


Article: 115083
Subject: Re: Differential pairs per Bank
From: Sean Durkin <news_jan07@durkin.de>
Date: Tue, 30 Jan 2007 20:03:18 +0100
Links: << >>  << T >>  << A >>
Thomas Reinemann wrote:
> Hello,
> 
> we want to use a Spartan-3A to collect signals of about 100 
> differential lines. This type offers the possibility for on-chip LVDS 
> termination. Is there a limit how many pairs per bank can be 
> terminated via the on-chip resistor?
I'm not really fluent in the Spartan-3A-architecture, but if it's
anything like Virtex, then there should be no limit. The only
restriction is that for some I/O-pins in a bank, there is no second pin
for the differential pair, i.e. some pins can only be used single-ended.
So the overall total of differential pairs you can use in the FPGA does
not equal the total number of IOs/2.

But in Spartan-3A, your VCCO needs to be 3.3V if you want the internal
terminations to be 100R (see page 339 of ug331 from Dec 5, 2006).
Strange enough, in Spartan-3E, Virtex-II Pro and Virtex-4, VCCO needs to
be 2.5V for the correct termination value, so this is something one has
to look out for.

As I found out after installing on Friday, ISE9.1 stops the place and
route with an error message if you don't watch out for this. In earlier
versions of the tools, this did not even produce a warning.

-- 
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

Article: 115084
Subject: Re: help with Design Compiler -> Quartus
From: Ben Twijnstra <btwijnstra@gmail.com>
Date: Tue, 30 Jan 2007 20:16:21 +0100
Links: << >>  << T >>  << A >>
Sebastian Schüppel wrote:

> I have a source code which is compiled by the Design Compiler from
> Synopsys. I also mapped my technology library to that, so it will generate
> a VHDL netlist.
> 
> My problem is that there are Components declarations and instantiations in
> the netlist with no architecture.

Can you give one or two examples of such components? It may be that these
are Altera primitives which are known to the Quartus software.

Best regards,


Ben


Article: 115085
Subject: Help with Xilinx i/o constracint for ps/2 port
From: "fp" <fpga002006@yahoo.com>
Date: 30 Jan 2007 11:18:07 -0800
Links: << >>  << T >>  << A >>
I am designing a PS2 interface for a board with Xilinx
Spartan-3 device.  The clock and data signals of
the PS2 port are bi-directional and use open-collector circuit.
On the board, there is a serial resistor
between an FPGA pin and PS2 port.
The following constraint is used in ucf file:

NET "ps2_clock" LOC = "..." | IOSTANDARD = LVCMOS33 | SLEW = SLOW | 
PULLUP;

Can anyone advice me whether it is ok?  Can the "PULLUP" option be 
used to emulate
the pull-up resistor in a open-collector circuit?

Thanks in advance.

S. C.


Article: 115086
Subject: Re: How to use the test bench wave form simulator?
From: <boled>
Date: Tue, 30 Jan 2007 19:18:39 -0000
Links: << >>  << T >>  << A >>
yes!



Article: 115087
Subject: Re: 1 Gbps - state of the art?
From: PeteS <peter.smith8380@ntlworld.com>
Date: Tue, 30 Jan 2007 19:31:38 GMT
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> PeteS wrote:
>>
>> In terms of bitrates, then I designed a board with serial links at 
>> 5Gb/s *per pair* a couple of years ago. Before that I designed some 
>> switches and gateways with 2.5Gb/s pairs (lots and lots of them). PCI 
>> Express has just released the 5Gb/s signalling revision (within the 
>> last month or so, I believe). 
> 
> Latest boasting on this is here
> http://www.altera.com/corporate/news_room/releases/products/nr-pcie2.html?f=hp&k=wn2 
> 
> 
> and here
> 
> http://www.xilinx.com/prs_rls/2007/silicon_vir/0706_V5PCIe-compliance.htm
> 
> I presume there _is_ some important BER threshold to set the distance, 
> and that this fluff is marketing's effort :
> 
> ".. reliably transmit data over an unprecedented 30 m "
> 
> - how 'reliably' exactly ? - giving a distance without any error rate is
> getting a bit slack...
> 
> I also see they spec thus "5-GT/s PCIe 2.0 specification"
> 
> ( Transistions per second )which seems more sensible than Gbps.

Actually, I think it's Transfers per second (which for NRZ data is the 
same as the bit rate). That's commonly used in HT (formerly LDT) for the 
data rate.


> 
> -jg
> 

Well, I have seen 2.5Gb/s go 17 metre with 10dB loss and that was 5 
years ago; the new distance looks to be a single lane which might sound 
good to the marketdroids, but isn't much use or very practical.

Note that the later versions of the specifications don't put a loss 
limit, but rather refer to eye closure (at least that's true for IB).

To claim compliance, the link has to exhibit <1E-12 BER, at least for 
earlier versions. As I don't have a copy of the PCI-e 2.0 spec I'll 
assume (as a SWAG) that's still true.

Cheers

PeteS

Article: 115088
Subject: Re: Differential pairs per Bank
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Tue, 30 Jan 2007 20:14:41 +0000 (UTC)
Links: << >>  << T >>  << A >>
Thomas Reinemann <tom.reinemann@gmx.net> wrote:
> Hello,

> we want to use a Spartan-3A to collect signals of about 100 
> differential lines. This type offers the possibility for on-chip LVDS 
> termination. Is there a limit how many pairs per bank can be 
> terminated via the on-chip resistor? Where may I find further 
> information?

Often LVDS on-chip Termination is a  power hog  on Xilinx chips. 
Consider using a multi channel LVDS transceiver. like the SN65LVDM1677. It
eases layout and spares you a lot of pins.

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 115089
Subject: Re: Help with Xilinx i/o constracint for ps/2 port
From: "Andy Peters" <google@latke.net>
Date: 30 Jan 2007 12:18:07 -0800
Links: << >>  << T >>  << A >>
On Jan 30, 12:18 pm, "fp" <fpga002...@yahoo.com> wrote:
> I am designing a PS2 interface for a board with Xilinx
> Spartan-3 device.  The clock and data signals of
> the PS2 port are bi-directional and use open-collector circuit.
> On the board, there is a serial resistor
> between an FPGA pin and PS2 port.
> The following constraint is used in ucf file:
>
> NET "ps2_clock" LOC = "..." | IOSTANDARD = LVCMOS33 | SLEW = SLOW |
> PULLUP;
>
> Can anyone advice me whether it is ok?  Can the "PULLUP" option be
> used to emulate
> the pull-up resistor in a open-collector circuit?

The FPGA pull-ups are pretty weak, as they're basically intended to 
keep CMOS inputs at a known state.  This means that the pull-up is 
slow.  As long as you can tolerate that, you'll be OK.  But the bad 
news is that you don't really know how weak they are.  A proper pull-
up resistor is a good thing.

-a


Article: 115090
Subject: Re: How to use the test bench wave form simulator?
From: "Andy Peters" <google@latke.net>
Date: 30 Jan 2007 12:19:37 -0800
Links: << >>  << T >>  << A >>
On Jan 30, 7:58 am, <boled> wrote:
> Hello, can anyone explain to me how to use the test bench
> waveform simulator. I am receiving a clock and another
> signal and some yellow spikes on the screen.
> Reg.

you'd get a lot more help if you told us what simulator you're using.

-a


Article: 115091
Subject: Re: how does z-transforms (basically the mathematical techniques
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 30 Jan 2007 12:28:05 -0800
Links: << >>  << T >>  << A >>
CMOS wrote:

> how does z-transforms (basically the mathematical techniques in 
> designing digital systems) map with
> FPGA implementations. is there a systamatic flow that is used in the 
> industry when implementing a  given algorythm in verilog/VHDL.

You might ask on comp.dsp, for the more mathematical side.

Otherwise, the easy answer is that Z**(-1) is a register
(set of FFs).  I like systolic arrays, though they may or
may not work for your application.

-- glen


Article: 115092
Subject: ahdl --> vhdl
From: "zlotawy" <spawnek@NNOOSSPPAAMM.wp.pl>
Date: Tue, 30 Jan 2007 21:37:43 +0100
Links: << >>  << T >>  << A >>
hi,
i have project in ahdl (max plus II). Is it possible to convert it to vhdl?

I tried to use XPort, but there were errors.

zlotawy



Article: 115093
Subject: Re: Problem with verilog program
From: "motty" <mottoblatto@yahoo.com>
Date: 30 Jan 2007 12:51:57 -0800
Links: << >>  << T >>  << A >>
Yeah, I guess I see how you can meet a setup time depending on how you 
define your data.  And Xilinx logic may have 0 hold time.  But why 
would you want to use your clock input as data?  There will almost 
certainly be a better way to do whatever it is you are trying to do.  
It makes my head hurt to think of all the problems that may arise.


Article: 115094
Subject: Re: How to use the test bench wave form simulator?
From: <boled>
Date: Tue, 30 Jan 2007 21:05:54 -0000
Links: << >>  << T >>  << A >>
> you'd get a lot more help if you told us what simulator you're using.

OK, here is a simpler question. I am viewing qst.pdf   help  file.
In this document there is Figure 8 Test Bench Waveform.
Down below there is Figure 11 Test Bench Waveform with Results.
How do I get from Figure 8 to Figure 11 ?
My screen shows all these yellow spikes of the simulation, but all the
signals are unchanging, i.e. I do not see any counting going on?

>
> -a
>



Article: 115095
Subject: UNKNOWN Processor Version (0) in XMD
From: "Shant" <shantchandrakar@gmail.com>
Date: 30 Jan 2007 13:49:54 -0800
Links: << >>  << T >>  << A >>
Hi All,

I am a Newbie and I am trying to load my C program on an FPGA using 
through EDK 8.1i without using BSB (since it does not support multiple 
processors). I am using Xilinx's ML310 development board for the same 
and. I am using Jtag cable for connection. After downloading my 
program on the FPGA and launching XMD I am getting the following 
messages:





Xilinx Microprocessor Debug (XMD) Engine
Xilinx EDK 8.1.02 Build EDK_I.20.4
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

XMD%
Loading XMP File..
Processor(s) in System ::

Microblaze(1) : microblaze_0
Address Map for Processor microblaze_0
  (0x00000000-0x00001fff) lmb_bram_if_cntlr_1   lmb_v10_0
  (0x00000000-0x00001fff) lmb_bram_if_cntlr_0   lmb_v10_1
  (0x80000000-0x800000ff) opb_uartlite_0        opb_v20_0
  (0x80000100-0x800001ff) opb_mdm_0     opb_v20_0

Connecting to cable (Parallel Port - LPT1).
Checking cable driver.
 Driver windrvr6.sys version = 7.0.0.0. LPT base address = 0378h.
 ECP base address = 0778h.
 ECP hardware is detected.
Cable connection established.
Connecting to cable (Parallel Port - LPT1) in ECP mode.
Checking cable driver.
 Driver xpc4drvr.sys version = 1.0.4.0. LPT base address = 0378h.
 Cable Type = 1, Revision = 3.
 Setting cable speed to 5 MHz.
Cable connection established.

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       0a001093           8        System_ACE
 2       0127e093          14        XC2VP30
Assuming, Device No: 2 contains the MicroBlaze system
Connected to the JTAG MicroProcessor Debug Module (MDM)
No of processors = 1

UNKNOWN Processor Version (0)
        Verify if FPGA Bitstream was downloaded and DONE pin went High





During download process, LEDs for OPB ERR and PLB ERR becomes Red for 
a while and then becomes green again. Once the Download process 
finishes, the INIT LED goes Low and DONE LED goes Green.
For Verifying the download, I also tried downloading my program 
through iMPACT and doing the verification afterwards, but then also I 
am getting the same message again.

Apart from this, the tutorial also asks for invoking the HyperTerminal 
before starting the download process, I also did the same using COM1 
(after connecting the serial port cable ) with
Baud rate of 9600,
Data 8 bits,
Parity None,
Stop 1 and
Flow Control None

And it mentions about the print statements getting displayed on the 
HyperTerminal. But I could not see anything on the HyperTerminal.

I am not in a position to understand why it is happening. So please 
suggest your expert comments on this problem of mine.

Thanks,
Shant Chandrakar


Article: 115096
Subject: Re: ahdl --> vhdl
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 30 Jan 2007 14:50:34 -0800
Links: << >>  << T >>  << A >>
zlotawy wrote:

> i have project in ahdl (max plus II). Is it possible to convert it to vhdl?

Yes, but it will cost you either time or money.

       -- Mike Treseler

Article: 115097
Subject: Re: USB 2.0 Streaming using FPGAs
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Wed, 31 Jan 2007 11:42:51 +1000
Links: << >>  << T >>  << A >>
Nitro wrote:

>>
> 
> I would look at the Xilinx ML403 eval board.  I don't remember the speed of
> the USB but it does have ethernet 10/100/1000 trimode and a a Vertex 4 (and a
> bunch of other I/O's.)  It runs about $500 US

It's USB1.1 only - 12Mbps max.

John

Article: 115098
Subject: Re: Minimal design for xilinx?
From: Ray Andraka <ray@andraka.com>
Date: Tue, 30 Jan 2007 23:22:43 -0500
Links: << >>  << T >>  << A >>
canest wrote:

>>Rather than making and then debugging your own board, go to the Xilinx
>>website and look for the evaluation boards.  Diligent sells one for
>>$49.00 that has an xc9572 and a coolrunner on it along with power supply
>>and a breadboard area and a few LEDs.  They also sell one through xilinx
>>that has one CPLD, plus a solderless breadboard, switches, 7 segment
>>display and leds for $49-59.  For those costs, especially if it is a
> 
> 
> Yes, and then they charge another $80 for sending it to the UK.
> 
> 
>>one-off to get you up the learning curve, you can't beat the kits.
> 
> 
> 

OK, fine, but even at $129-139, that is far cheaper than what it will 
cost to get your own board made.  You'll probably spend more than half 
of that just on the components, then you've got to do the artwork, have 
a board fabricated, stuff it, and debug it (which in itself is going to 
be non-trivial if you havent worked with CPLDs before) before you ever 
get to play with your simple design.  Even if your time is worth 
nothing, you'll come out ahead buying the eval board AND paying to have 
it shipped to you.

Article: 115099
Subject: Re: How to use the test bench wave form simulator?
From: "Duth" <premduth@gmail.com>
Date: 30 Jan 2007 21:46:28 -0800
Links: << >>  << T >>  << A >>
On Jan 31, 2:05 am, <boled> wrote:
> > you'd get a lot more help if you told us what simulator you're using.
>
> OK, here is a simpler question. I am viewing qst.pdf   help  file.
> In this document there is Figure 8 Test Bench Waveform.
> Down below there is Figure 11 Test Bench Waveform with Results.
> How do I get from Figure 8 to Figure 11 ?
> My screen shows all these yellow spikes of thesimulation, but all the
> signals are unchanging, i.e. I do not see any counting going on?
>
>
>
> > -a

Hi,

You will not see these yellow boxes any more in ISE 9.1i. The flow has
changed from 8.xi where the generated expected results is completely
changed. Now it is called generate self checking test bench and the
flow has improved significantly. If you are using 9.1i, please use the
QST for the 9.1i as well

Thanks
Duth




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