Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"vlsi_learner" <bajajk@gmail.com> wrote in message news:1170693557.608366.287660@j27g2000cwj.googlegroups.com... > Hi, > > what is the best way of moving data from a faster clock domain (100 > mhz ) to slower one(75 Mhz)? > > thanks I liked the way some code came together for a similar asynchronous transfer. Specifically targeting a distributed RAM architecture like the Xilinx families, the footprint is rather small. Use a 4-entry, dual-port distributed CLB Select RAM (or equivalent). Use two 2-bit Gray-coded indexes for the write and read time domains. Increment the write index for each write. Generate a new-value flag by registering when the read and write indicies are different in the read domain. Increment the read index with the new-value flag as you read the new value. By having the one read flag dealing with the Gray-coded write index, appropriate timing constraints can be applied to overconstrain the timing from the flag to where it's used, reducing metastability to effectively "never" be a problem. The Gray coding on the write index keeps the new-value flag honest. The write is in its own timing domain with no concern for the read. The new-value flag should use a combination of the read index and the current new-value flag to generate the next state. Total footprint is 3 slices of overhead with 1 slice per bit-width for the intermediate buffer. It's simple and it gets the job done. There will always be at least one cycle of latency in the read timing domain to let the new-value flag settle and get used. If one tried to generate the flag as a qualifier at the same time as an unqualified read, there's a chance the write index change kicks off the new-value flag before the write value has stabalized so the cycle of delay is helpful on both read and write sides. This is the fun stuff.Article: 115276
On Feb 5, 12:20 pm, Joseph Samson <jsam...@the-company-name.com> wrote: > yttrium wrote: > > it also seems impossible to add xco files that are in the working > > directory to the GUI, from the moment they are in a sub-directory or > > other directory you can add them? > > I keep all the verilog source and xco files in the same Verilog > subdirectory. In all previous versions, I could choose 'Add Source", > then select all the files in the Verilog subdirectory. In 9.1i, the xco > files can only be added using 'Add Copy of Source'. Apparently 'Add > Source' is no longer good enough for xcos. oh, that's a great step BACKWARDS. -aArticle: 115277
Hi !! I sent an inquiry about 3 weeks before to digilent, but neither an answer, nor a reply yet. Same for the 2nd & 3rd try... Are they still in business ?? THX ! -- XAKiChaosArticle: 115278
ram, >> I am a doing design.I am emulating FPGA.My problem is whenever i >> change one line of code(verilog) on top model i am getting getting >> most worst result.How to preserve the previous information.My time is >> wasting really like hell.I dont know how to end this design also.But >> functionally i proved the design is working.due to P& R result is >> changing. Have you looked at this part of the Quartus manual yet: http://www.altera.com/literature/hb/qts/qts_qii51015.pdf It describes a way to partition your design so that the parts that do not change also do not need to be re-synthesized or re-P&Red. Also, have you properly constrained your design? (i.e. clock constraints on clock pins, Tsu, Tco etc on the I/O pins etc etc?) If Quartus does not know what to aim for, it won't try, in order not to waste excessive electricity. >> Really i am getting anger on the altera guys.Can you suggest >> me a solution First, read the abovementioned documentation (aka RTFM). Second, read some more documentation on design constraints. Third, check your constraints. Fourth, post detailed questions to comp.arch.fpga, including bits of sample code, concrete results of what happens when you change what etc etc Best regards, BenArticle: 115279
They have a phone number, too. Look at the bottom of the page: http://digilentinc.com/ "Kosta Xonis" <ChaosKosta@web.de> wrote in message news:eq84us$3ij$00$1@news.t-online.com... > Hi !! > > I sent an inquiry about 3 weeks before to digilent, but neither an answer, > nor a reply yet. > > Same for the 2nd & 3rd try... > > Are they still in business ?? > > > > THX ! > > -- > XAKiChaosArticle: 115280
John_H schrieb/wrote: > They have a phone number, too. Look at the bottom of the page: I already saw this, but its overseas (me from DE), and my spoken english is worse than my written. Thanks [...] -- XAKiChaosArticle: 115281
I haven't talked to them myself in the last 60 days but they appear to be going strong. The Spartan-3A starter board just entering the market is a digilent product, though not necessarily (initially) sold directly by them. It's a small outfit that was started (I believe) by a college professor or two to help supply students with decent hardware. A slow/no response may be that the one person you're trying to contact is stuck under a deluge of other email or new-product issues. It's also possible that strange spam-filtering had problems with the email (false positives are a problem sometimes). If you reply to me directly with quick questions (and where/when you sent them before) I would happily devote 15 minutes of my morning trying to get the right people connected. I'd reply directly back to your email 20 hours from now if you'd like to take me up on the offer. "Kosta Xonis" <ChaosKosta@web.de> wrote in message news:eq84us$3ij$00$1@news.t-online.com... > Hi !! > > I sent an inquiry about 3 weeks before to digilent, but neither an answer, > nor a reply yet. > > Same for the 2nd & 3rd try... > > Are they still in business ?? > > > > THX ! > > -- > XAKiChaosArticle: 115282
They are in business. They are associated with the university in Spokane, Washington State, and I think they are as solid as the "rock of Gibraltar". Send them an e-mail if you prefer written English. Oder brauchst Du Hilfe auf Deutsch? Peter Alfke On Feb 5, 2:00 pm, Kosta Xonis <ChaosKo...@web.de> wrote: > John_H schrieb/wrote: > > > They have a phone number, too. Look at the bottom of the page: > > I already saw this, but its overseas (me from DE), and my spoken english > is worse than my written. > > Thanks > [...] > > -- > XAKiChaosArticle: 115283
On Jan 23, 3:49 am, "Jon Beniston" <j...@beniston.com> wrote: > > I am a college student experimenting with VHDL and currently using the > > Spartan 3 starter kit. This particular kit (unlike the Spartan3e) does > > not come with an onboard usb connector. I was hoping to add one and > > bring in the D+ and D- lines directly into the FPGA I/O pins. I realize > > that these signals are RS485 differential, and that the FPGA would > > require LVTTL input. > > > I plan to hook a device like a usb mouse to this board, which would > > only use USB1.1 standard, and I expect the swing to be somewhere around > > 3.3 to 3.6V, and the the tolerance would be safe enough to bring into > > the FPGA. Is this something that can be done? I am still fumbling > > around the thick USB manual, but I believe that it is possible. > > > Assuming that I am stuck with the current Spartan3 board, how can I > > allow a low speed device like a mouse to interface with the FPGA? Thank > > you very much for any insight you can offer. > > USB transceivers are cheap: > > http://www.nxp.com/pip/isp1106.html > > USB HDL can be found here: > > http://www.opencores.org/projects.cgi/web/usbhostslave/overview > > Cheers, > Jon Jon, Does one of these USB transceivers exist in a dual in line package, in 1/10 '' spacing, where I can easily solder to my test board? Thanks.Article: 115284
Peter Alfke wrote: [snip] > Therefore, in the Virtex-5 DDR/DDR2 SDRAM memory controller, we now > provide multiple-bank support to increase the efficiency of data > throughput. Any hope that this will migrate down to the V4 and Spartan 3 designs?? --- Joe Samson Pixel VelocityArticle: 115285
Lancer wrote: > On 30 Gen, 00:39, John Williams <jwilli...@itee.uq.edu.au> wrote: > >>I suggest you purchase one of the S3E-50 or -160 starter kits to get a >>platform that will happily run embedded Linux on the MicroBlaze. These >>boards have plenty of memory and were more or less designed with >>MicroBlaze/Linux in mind. > > S3 Starter board isn't mine, I'm using it in University Lab. > But we have also XUPV2P, that run very well uclinux, but my work it's > to port uclinux on S3... > Do you think is it possible? Sure, it's possible, but as I said your 1M memory limit will be challenging. Kernel boot from flash is supported in the kernel and petalinux distribution - once you have selected your vendor/platform combo, in "Kernel settings -> Processor options", choose "ROM" for the memory model, instead of RAM. You'll need to enter the start address and size of the flash region that will host the kernel image. The kernel link script will be automatically adjusted to link it from the correct address. To boot the board you'll have to write the image into the flash memory. You can use the EDK's flash_writer XMD/TCL scripts for this. Finally, to boot the board just use PetaLinux's fs-boot or some trivial bootloader to jump to the correct start address in flash. Having to write the kernel inrto flash each time you rebuild might get painful, but it's possible. Regards, JohnArticle: 115286
> Bresenham's circle drawing algorithm is far simpler to implement. It > was originally developed for exactly this application. Google > "bresenham circle" to get all the info you'll need. This is a great algorithm and each and every engineer should read it up and understand it's workings. But as most FPGA designs have no use for the amount of hardware multipliers available in todays FPGAs, x*x + y*y < r*r might actually be a lot simpler. Kolja SulimaArticle: 115287
Hey guys, is there anyone who uses Virtex2p with compact flash card as Inst Mem and DDR as data mem?..I am a newbie for FPGAs and desperately need some help..pls help me :) AngeloArticle: 115288
hi, thak you very much for all the information. im gonna have a look at both of the recomondations. CMOSArticle: 115289
Having read through a bunch of Xilinx DDR app notes, I'm confused. It seems that the only way to use DDR with a Spartan-3 at high speed is to deal with a carefully constructed LUT-delay chain, subject to manual routing and other nightmares. Other competing products, such as the Cyclone I & II have programmable delays in some of the IOBs, making centering on the DQS trivial in comparison. The OP (Mounard Le Fougueux) didn't mention *which* FPGA he was targeting. It seems to me the answer depends crucially on this. Tommy On Feb 5, 10:18 am, "Peter Alfke" <p...@xilinx.com> wrote: > I checked with the Xilinx Applications group, and here is their > answer: > > "The free memory interface designs developed by the Xilinx memory > applications team have one primary goal: to prove that the FPGA device > can interface with given external memory devices at the specified > performance, using the IO standard specified by the memory vendor > (JEDEC). > We therefore focus on the physical layer that comprises the read data > capture logic, and the write data transmit logic. > The memory controller that we provide with the interface design is > very basic, handling memory initialization, auto refresh commands, and > other user requested commands like reads and writes. Such a basic > controller can be efficient (high data throughput) for streaming video > applications with consecutive reads and writes to the same row and > bank. But such a controller is very inefficient in applications > requiring random accesses to different rows and banks. > Therefore, in the Virtex-5 DDR/DDR2 SDRAM memory controller, we now > provide multiple-bank support to increase the efficiency of data > throughput. Multiple-bank support may still not be the solution for > certain applications, and our customers usually replace just the > Xilinx-provided controller with one that they designed to specifically > handle their system's traffic pattern. > > With our free Virtex-5 applications the memory interface designs are > modular and provide a clean partition between the optimized physical > layer and the controller, making it easy to replace the controller > while retaining the physical layer design." > > Hope this explanation helps. > Peter Alfke, Xilinx > > On Feb 1, 5:55 pm, Ray Andraka <r...@andraka.com> wrote: > > > I think what Nico was trying to say is you get what you pay for. In my > > experience, the free DDR designs are generally not worth much. Either > > they only support basic operation, or they won't work at full speed, or > > they are so littered with bugs that you are better off starting from > > scratch. Yes, there are "free" cores out there, but you'll likely put > > as much effort into getting them to work in your design as you would > > starting with a clean sheet.Article: 115290
Yes. I ordered and received a board from them two weeks ago. When I called, they answered the phone (business hours are posted on the Contacts page), and answered all the questions I had. Regards, SH "John_H" <newsgroup@johnhandwork.com> wrote in message news:12sfcq68j64a513@corp.supernews.com... >I haven't talked to them myself in the last 60 days but they appear to be >going strong. The Spartan-3A starter board just entering the market is a >digilent product, though not necessarily (initially) sold directly by them. >It's a small outfit that was started (I believe) by a college professor or >two to help supply students with decent hardware. A slow/no response may >be that the one person you're trying to contact is stuck under a deluge of >other email or new-product issues. It's also possible that strange >spam-filtering had problems with the email (false positives are a problem >sometimes). > > If you reply to me directly with quick questions (and where/when you sent > them before) I would happily devote 15 minutes of my morning trying to get > the right people connected. I'd reply directly back to your email 20 > hours from now if you'd like to take me up on the offer. > > > "Kosta Xonis" <ChaosKosta@web.de> wrote in message > news:eq84us$3ij$00$1@news.t-online.com... >> Hi !! >> >> I sent an inquiry about 3 weeks before to digilent, but neither an >> answer, nor a reply yet. >> >> Same for the 2nd & 3rd try... >> >> Are they still in business ?? >> >> >> >> THX ! >> >> -- >> XAKiChaos > >Article: 115291
Hi,
We are trying to implemnt a very huge design. For that we need a
v5lx330 fpga. Also we need video in/out, AD/DA converter greter than
128 MB DDR ram, expansion slot by which we can connect a daughter
board with atleast 200 signals. We serached on the net but no reday
avialble borads suits our requirement. Is there any way to modify the
design of existing boards and a make a custom board which suits our
requirement. If any boady knows about firms doing this type of
activity please send me a link. Thanks in adavance.
regards
Sumesh V S
Article: 115292Joseph Samson wrote: > yttrium wrote: >> it also seems impossible to add xco files that are in the working >> directory to the GUI, from the moment they are in a sub-directory or >> other directory you can add them? > > I keep all the verilog source and xco files in the same Verilog > subdirectory. In all previous versions, I could choose 'Add Source", > then select all the files in the Verilog subdirectory. In 9.1i, the xco > files can only be added using 'Add Copy of Source'. Apparently 'Add > Source' is no longer good enough for xcos. > > --- > Joe Samson yes indeed, that is what the warning says ... but the strange thing even then i can't add them?Article: 115293
xingzhi kirjutas: > I was trying to installing Xilinx ISE 9.1i full version on RHEL 4 AS 64-bit and I got following errors: > > error while loading shared libraries: libstdc++.so.5: cannot open shared object file: No such file or directory > > The Xilinx Webpage says RHEL 4 WS 64-bit is supported. Does this mean only WS not AS is supported? Any one succeed on installing 9.1i on AS/ES ? > > Thanks Yoa have to install compat-libstdc++-33 package to get that library. PriitArticle: 115294
On Jan 12, 2:43 pm, "mmihai" <iia...@yahoo.com> wrote: > > Last December I've migrated my changes to this source base since it > seemed more active; however, reading the posts regardingxc3sprogon > this newsgroup and sourceforge you'll find people trying to commit > changes and not being able to. May be you can try to get in touch with > the sourceforge project owner and help with managing new patches (I'll > be more than happy to submit my changes if somehow is possible). Current version of xc3sprog in SVN incorporates all of the patches submitted so far. I pulled them in a couple of days ago, partially in response to this thread. Please submit your new patches - I will try to keep the project up to date.Article: 115295
On 6 Feb., 05:43, "Tommy Thorn" <tommy.th...@gmail.com> wrote: Tommy, > Having read through a bunch of Xilinx DDR app notes, I'm confused. It > seems that the only way to use DDR with a Spartan-3 at high speed is > to deal with a carefully constructed LUT-delay chain, subject to > manual routing and other nightmares. Other competing products, such as I've done my own DDR controller (targeted at the Spartan3E-Starter Kit) some months ago and it wasn't that hard. It interfaces 16 Bit, 130MHz DDR to a 64 bit wishbone bus at 65 MHz. [1] It's not very felxible, and in retrospective i should have done an asyncronous design where the wishbone bus can be arbitraty clocked... But.. hey, it was one of my very first VHDL projects. j. [1] https://roulette.das-labor.org/trac/wiki/wb_ddrArticle: 115296
Joseph Samson wrote:
> Francesco wrote:
>
>> Hi, I'm just wondering how many people here are using ISE 9.1.
>> Could you post your experience here?
>
>
> I just got my full version of ISE (not webpack) and tried routing my
> current design. As part of the design, I use the DCM Standby workaround.
> I can import all the DCM Standby code into the GUI, but XST gives an
> error saying that there are missing modules. I opened a webcase, and my
> tech support person gets the same error that I do.
I have received a fix. The top level module, dcm_standby.v, uses a meta
comment:
module dcm_standby (
CLK0,
CLK180,
CLK270,
CLK2X,
CLK2X180,
CLK90,
CLKDV,
CLKFX,
CLKFX180,
LOCKED,
DO,
PSDONE,
CLKFB,
CLKIN,
PSCLK,
PSEN,
PSINCDEC,
RST
)/* synthesis syn_noclockbuf=1 */;
This was OK in previous versions of XST, but not 9.1i. To fix it, remove
the comment and place it in the code after the STANDBY and RINGOSC
modules have been instantiated.
As for 9.1i breaking the 8.1i console window scrolling, I am out of
luck; no working on 8.1i problems now that 9.1i has been released.
---
Joe Samson
Pixel Velocity
Article: 115297"vu_5421" <nugentoffer@gmail.com> schrieb im Newsbeitrag news:1170720006.639269.187300@k78g2000cwa.googlegroups.com... > On Jan 23, 3:49 am, "Jon Beniston" <j...@beniston.com> wrote: >> > I am a college student experimenting with VHDL and currently using the >> > Spartan 3 starter kit. This particular kit (unlike the Spartan3e) does >> > not come with an onboard usb connector. I was hoping to add one and >> > bring in the D+ and D- lines directly into the FPGA I/O pins. I realize >> > that these signals are RS485 differential, and that the FPGA would >> > require LVTTL input. >> >> > I plan to hook a device like a usb mouse to this board, which would >> > only use USB1.1 standard, and I expect the swing to be somewhere around >> > 3.3 to 3.6V, and the the tolerance would be safe enough to bring into >> > the FPGA. Is this something that can be done? I am still fumbling >> > around the thick USB manual, but I believe that it is possible. >> >> > Assuming that I am stuck with the current Spartan3 board, how can I >> > allow a low speed device like a mouse to interface with the FPGA? Thank >> > you very much for any insight you can offer. >> >> USB transceivers are cheap: >> >> http://www.nxp.com/pip/isp1106.html >> >> USB HDL can be found here: >> >> http://www.opencores.org/projects.cgi/web/usbhostslave/overview >> >> Cheers, >> Jon > > Jon, > > Does one of these USB transceivers exist in a dual in line package, in > 1/10 '' spacing, where I can easily solder to my test board? Thanks. > NO.Article: 115298
On 05 Feb 2007, you wrote in comp.arch.fpga: > On Jan 30, 8:04 am, "Sebastian Schüppel" <sch...@hrz.tu-chemnitz.de> > wrote: >> I have a source code which is compiled by the Design Compiler from >> Synopsys. I also mapped my technology library to that, so it will >> generate a VHDL netlist. >> >> My problem is that there are Components declarations and >> instantiations in the netlist with no architecture. >> >> And I'd like to use this netlist as a component of my design in >> Altera's Quartus software. >> >> Can someone tell me how I get this fixed. >> >> Thanks > > Is there some reason you don't want to synthesize the original source > code in quartus, instead of importing the netlist? Quartus will > undoubtedly do a better job of synthesizing to the altera fpga > architecture than design compiler will. > > Andy Yes, the reson why I use the design compiler (better to say I use a gui which sits on top of it. called coreConsultant) is because it is a designware source which is encrypted.Article: 115299
Is there a way of generating VHDL code from Matlab code for DSP, more precisely image processing using wavelet transform? I want to implement a small 8X8 image processing layout that will use wavelet transform and it is not easy to come up with the VHDL code for that. Any help would be highly appreciated! Thanks, Dan
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z