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Messages from 42150

Article: 42150
Subject: Re: Looking for SpartanXL demo board
From: spam_hater_7@email.com (Spam Hater)
Date: Wed, 17 Apr 2002 05:33:19 GMT
Links: << >>  << T >>  << A >>

Needs to be 3.3V


On Mon, 15 Apr 2002 21:52:55 -0500, Kevin Brace
<ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote:

>Why not go with a Spartan-II demo board?
>It seems more readily avaiable.
>
>Kevin Brace (In general, don't respond to me directly, and respond
>within the newsgroup.)
>
>Spam Hater wrote:
>> 
>> Hi,
>> 
>> I'm looking for a SpartanXL demo board.  Any good ones out there?
>> 
>> Something I can download with my XChecker cable, and get at all the
>> pins.
>> 
>> TIA


Article: 42151
Subject: Re: Virtex Development Board with a 4M or more gates
From: "Vincent Vendramini" <Vincent.Vendramini@cern.ch>
Date: Wed, 17 Apr 2002 09:14:55 +0200
Links: << >>  << T >>  << A >>
Bonjour,
Memec Insight est un distributeur officiel de xilinx,
http://www.insight-electronics.com
Cordialement.

"Cyrille de Brébisson" <cyrille_de-brebisson@hp.com> wrote in message
news:a9hn2r$9v1$1@web1.cup.hp.com...
> Hello,
>
> We are working on a BIG design, and we are looking for a Virtex II based
> development board with a XC2V4000 or higher. Does someone has an idea of
> where to find one?
>
> Regards, Cyrille
>
>



Article: 42152
Subject: problem installing xilinx foundation 3.1 on a P4
From: Vaggelis Tripolitakis <tripol@mhl.tuc.gr>
Date: Wed, 17 Apr 2002 11:28:05 +0300
Links: << >>  << T >>  << A >>
Hello ppl ,

I 'm trying to install Xilinx Foundation 3.1 (Licensed version) on a
P4 machine and during the installation it crashed repeatedly showing
the following error :

"java.exe Application error...."

I tried to install Foundation 4.1 and it worked OK but I don't have
a license version...So anyone can help ?


Thanks in advance

Vaggelis Tripolitakis
Undergraduate Student
Microelectronics & Hardware Lab
Technical University of Crete
Greece


Article: 42153
Subject: Re: JTAG cable and iMPACT
From: MICHAEL ALEX <michaelalex@attbi.com>
Date: Wed, 17 Apr 2002 08:41:50 GMT
Links: << >>  << T >>  << A >>
Jon - 

    Had the same problem with a Parallel III cable on a WIN'2K laptop,
but not on some other machines, including other laptops.  Tried
everything, especially all the different modes for the parallel port in
the machine BIOS (EPP, Bidirectional, etc.).  No dice after a week, as
well as much patient assistance by an FAE from NuHorizons.  I was on the
verge of sending my cable AND Spartan IIE board back.  But then ...
     Finally saw that my external USB CDRW drive had "comandeered" my
parallel port in Windows, even though I use it in only with a USB cable
(The drive has parallel port capability for older machines.).  I simply
disabled all parallel port capabilities for the drive in the Windows
control panel and rebooted, and iMPACT saw my JTAG cable and board right
off the bat.  
     Make sure nothing is stealing the parallel port without your
knowledge.  Even if BIOS is set up fine, something else in Windows may
take it without being too obvious ....

Good luck,
Michael


Jon Schneider wrote:
> 
> In article <3CBB6B46.54DF2EA5@xilinx.com>, micholba@xilinx.com (Michol
> Bauer) wrote:
> 
> > (NOTE: W95 is not supported.)
> 
> Are you saying that the parallel cable isn't supported or the software.
> 
> I say that because I have a shiny new Parallel IV cable and can only
> almost get it to work with Webpack on one machine (Win 98) but not at
> all on another.
> 
> Should I send it back ?
> 
>         Jon

Article: 42154
Subject: Re: FPGA Timing Problem
From: MICHAEL ALEX <michaelalex@attbi.com>
Date: Wed, 17 Apr 2002 08:45:33 GMT
Links: << >>  << T >>  << A >>
Crap.  I've been doing it wrong for like 20 years.  I thought we were
supposed to arrive late and leave early....

John Larkin wrote:
> 
> Why is it that all the production people like to get to work real
> early and then leave early, while the engineers arrive late and work
> late, so that when you really need a big chip replaced there's nobody
> around to do it for you?
> 
> John

Article: 42155
Subject: Re: Virtex Development Board with a 4M or more gates
From: gs@alphadata.co.uk (Graham Smart)
Date: 17 Apr 2002 03:30:27 -0700
Links: << >>  << T >>  << A >>
Cyrille,

Alpha Data are shipping PCI and PMC cards based on the V-II 2V6000
FF1156. Software Development Kit has template designs and drivers for
Windows, linux and VxWorks.

http://www.alphadata.co.uk has more information.

Regards, Graham

"Cyrille de Br?isson" <cyrille_de-brebisson@hp.com> wrote in message news:<a9hn2r$9v1$1@web1.cup.hp.com>...
> Hello,
> 
> We are working on a BIG design, and we are looking for a Virtex II based
> development board with a XC2V4000 or higher. Does someone has an idea of
> where to find one?
> 
> Regards, Cyrille

Article: 42156
Subject: GND Outputs being optimized out using FPGA Express 3.6.1 in ISE4.2.01
From: "William L Hunter Jr" <wlhunterjr@attbi.com>
Date: Wed, 17 Apr 2002 10:38:18 GMT
Links: << >>  << T >>  << A >>
Hi

I am doing a Virtex-II design using ISE 4.2.01 and FPGA Express 3.6.1.  I
have a few pins on my top level entity configured as outputs which are used
to set the address of some external devices.  In my architecture, I assign
these outputs a '0'.  FPGA express is optimizing out this connection.  If I
look at the synthesis optimized schematic viewer the connection to gnd and
output pad are missing.  How do you connect outputs to GND in VHDL?  I have
always assigned them a '0' in the VHDL and this always worked.  Any ideas on
what could be wrong??

Thanks in advance
Bill



Article: 42157
Subject: Re: GND Outputs being optimized out using FPGA Express 3.6.1 in ISE4.2.01
From: "Paul Baxter" <pauljnospambaxter@hotnospammail.com>
Date: Wed, 17 Apr 2002 12:12:49 +0100
Links: << >>  << T >>  << A >>
"William L Hunter Jr" <wlhunterjr@attbi.com> wrote in message
news:ugcv8.237269$Yv2.68162@rwcrnsc54...
> Hi
>
> I am doing a Virtex-II design using ISE 4.2.01 and FPGA Express 3.6.1.  I
> have a few pins on my top level entity configured as outputs which are
used
> to set the address of some external devices.  In my architecture, I assign
> these outputs a '0'.  FPGA express is optimizing out this connection.  If
I
> look at the synthesis optimized schematic viewer the connection to gnd and
> output pad are missing.  How do you connect outputs to GND in VHDL?  I
have
> always assigned them a '0' in the VHDL and this always worked.  Any ideas
on
> what could be wrong??

I'm not familiar with those particular tools or devices, but do you already
have a global setting 'set unused pins to GND' and so this default would
accomplish what you are requesting?

Try setting some of the outputs to a permanent high state and some low and
look at the result.



Article: 42158
Subject: does multilinx driver work on winxp?
From: ahgu@yahoo.com (Andrew Xiang)
Date: 17 Apr 2002 06:54:18 -0700
Links: << >>  << T >>  << A >>
I tried to install multilinx driver on xp and it crashes the xp. 
get a blue screen when I starts up. Cannot believe a big company like
Xilinx cannot get a USB driver to work correctly.

Anyway tried that? let me know? 
Also, how much fast is multilinx compared to parallel cable download?

thanks
Andrew
ahgu@yahoo.com

Article: 42159
Subject: Re: Virtex Development Board with a 4M or more gates
From: "Eric Pearson" <epearson@videolocus.com>
Date: Wed, 17 Apr 2002 10:23:44 -0400
Links: << >>  << T >>  << A >>
Try http://www.dinigroup.com, their DN3K10 supports from 1 to 5 of the
XC2V4000 or XC2V6000's.
One of the useful and *very* handy configuration methods they have is
loading from smart meadia cards.

Eric Pearson

"Vincent Vendramini" <Vincent.Vendramini@cern.ch> wrote in message
news:a9j7df$4pk$1@sunnews.cern.ch...
> Bonjour,
> Memec Insight est un distributeur officiel de xilinx,
> http://www.insight-electronics.com
> Cordialement.
>
> "Cyrille de Brébisson" <cyrille_de-brebisson@hp.com> wrote in message
> news:a9hn2r$9v1$1@web1.cup.hp.com...
> > Hello,
> >
> > We are working on a BIG design, and we are looking for a Virtex II based
> > development board with a XC2V4000 or higher. Does someone has an idea of
> > where to find one?
> >
> > Regards, Cyrille
> >
> >
>
>



Article: 42160
(removed)


Article: 42161
Subject: Problems with Nios 2.0
From: izuazua@ikerlan.es (Itsaso Zuazua)
Date: 17 Apr 2002 07:25:48 -0700
Links: << >>  << T >>  << A >>
Hi,

  I have several problems with the Nios 2.0:

    1-When I want to generate a Nios system module with the
SOPC_BUILDER it gives me errors saying that:"does´nt find boot
monitor, uname:unknown, grep:unknown...
    2-On the other hand, when I try to run the bash shell I have also
problems.It says me that 'bash.exe:can´t find /tmp file;create one'

   I´m thinking that I haven´t installed the NDK (HDK and SDK) tool
properly, despite the fact that I have installed it step by step as
it´s described in the documentation. Should I consider some
environment variables as PATH,TMP_DIR...? Is important the path where
I install the cygwin software? Should this path be the same or
relative to the SDK´s path?
Could anybody help me, please? 

   Thanks a lot,

      ITSASO

Article: 42162
Subject: Re: FPGA Timing Problem
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 17 Apr 2002 07:36:07 -0700
Links: << >>  << T >>  << A >>
John,

Traffic is so bad that if I leave late, I never get here.

Note the time on this email.

Austin

John Larkin wrote:

> Why is it that all the production people like to get to work real
> early and then leave early, while the engineers arrive late and work
> late, so that when you really need a big chip replaced there's nobody
> around to do it for you?
>
> John


Article: 42163
Subject: Knowing the design from the compilation report
From: izuazua@ikerlan.es (Itsaso Zuazua)
Date: 17 Apr 2002 08:05:10 -0700
Links: << >>  << T >>  << A >>
Hi,

   Is possible converting a .rpt file to a schematic file(.bdf) or to
a VHDL file? If I only have a .rpt file (compilation report file) of a
design, how could I obtain a more readablel logic of the design?

  Thanks a lot,

                Itsaso

Article: 42164
Subject: Re: FPGA Timing Problem
From: spam_hater_7@email.com (Spam Hater)
Date: Wed, 17 Apr 2002 15:31:44 GMT
Links: << >>  << T >>  << A >>

They have this thing called "a life".

I read about it in the Sunday paper once.  Always wondered what it
was, but none of them ever stayed late enough for me to ask them.


On Tue, 16 Apr 2002 19:32:04 -0700, John  Larkin
<jjlarkin@highlandSNIPTHIStechnology.com> wrote:

>
>Why is it that all the production people like to get to work real
>early and then leave early, while the engineers arrive late and work
>late, so that when you really need a big chip replaced there's nobody
>around to do it for you?
>
>John
>
>


Article: 42165
Subject: VHDL or Verilog SW to implement GPS receiver on FPGA
From: "Kent Krumvieda" <kentkr@datafusion.com>
Date: Wed, 17 Apr 2002 09:33:24 -0600
Links: << >>  << T >>  << A >>
Hi all

Does anyone know of a company out there selling VHDL or Verilog Source Code
that implements a GPS receiver on a FPGA?

Kent Krumvieda
Data Fusion Corp



Article: 42166
Subject: Re: Reconfiguring Spartan II after boot-up
From: koziar.pete@orbital.com (Pete Koziar)
Date: 17 Apr 2002 09:22:38 -0700
Links: << >>  << T >>  << A >>
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<a9hnim$3akmp$1@ID-84877.news.dfncis.de>...
> "Pete Koziar" <koziar.pete@orbital.com> schrieb im Newsbeitrag
> news:2951d198.0204160412.2414e128@posting.google.com...
> > We have an application where we desire to remotely program a new FPGA
> > image into a flash ROM then signal the system to reinitialize itself,
> > including reloading the Spartan II.
> >
> > The Spartan II is configuring through slave parallel mode.
> >
> > How do I get the Spartan II to clear its internal memory and reload
> > itself? I've tried just dropping the Program line, but neither Init or
> > Done ever goes low.
> 
> Pulse PROGRAM LOW (>300ns), then some hundred us after PROGRAM is HIGH
> again, DONE is LOW and INIT is HIGH (both are open drain).
> Then you start to clock in the data, if there is a CRC error, INIT will go
> LOW.
> After all bytes are transfered, you need some additional clocks (4 or 6, not
> sure at the moment) to start te FPGA (release global reset, Tristate etc.)
> Then DONE will go HIGH.


Thanks! I don't think I left PROGRAM down long enough and/or didn't
realize that PROGRAM needed to go back high before the magic started.
I was thinking DONE would go low while PROGRAM was low.

- Pete

Article: 42167
Subject: Re: Command-line utility for loading Xilinx XC9572XL and Spartan II via JTAG
From: koziar.pete@orbital.com (Pete Koziar)
Date: 17 Apr 2002 09:25:19 -0700
Links: << >>  << T >>  << A >>
Thanks! That should do it.

- Pete

Article: 42168
Subject: Re: GND Outputs being optimized out using FPGA Express 3.6.1 in
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 17 Apr 2002 09:27:56 -0700
Links: << >>  << T >>  << A >>



William,

See:

 http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=9780

For how to "keep" and "don't touch" instantiations so the tools don't rip them
out....

Austin

William L Hunter Jr wrote:

> Hi
>
> I am doing a Virtex-II design using ISE 4.2.01 and FPGA Express 3.6.1.  I
> have a few pins on my top level entity configured as outputs which are used
> to set the address of some external devices.  In my architecture, I assign
> these outputs a '0'.  FPGA express is optimizing out this connection.  If I
> look at the synthesis optimized schematic viewer the connection to gnd and
> output pad are missing.  How do you connect outputs to GND in VHDL?  I have
> always assigned them a '0' in the VHDL and this always worked.  Any ideas on
> what could be wrong??
>
> Thanks in advance
> Bill



Article: 42169
Subject: Re: Reconfiguring Spartan II after boot-up
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 17 Apr 2002 12:46:02 -0400
Links: << >>  << T >>  << A >>
Pete Koziar wrote:
> 
> "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<a9hnim$3akmp$1@ID-84877.news.dfncis.de>...
> > "Pete Koziar" <koziar.pete@orbital.com> schrieb im Newsbeitrag
> > news:2951d198.0204160412.2414e128@posting.google.com...
> > > We have an application where we desire to remotely program a new FPGA
> > > image into a flash ROM then signal the system to reinitialize itself,
> > > including reloading the Spartan II.
> > >
> > > The Spartan II is configuring through slave parallel mode.
> > >
> > > How do I get the Spartan II to clear its internal memory and reload
> > > itself? I've tried just dropping the Program line, but neither Init or
> > > Done ever goes low.
> >
> > Pulse PROGRAM LOW (>300ns), then some hundred us after PROGRAM is HIGH
> > again, DONE is LOW and INIT is HIGH (both are open drain).
> > Then you start to clock in the data, if there is a CRC error, INIT will go
> > LOW.
> > After all bytes are transfered, you need some additional clocks (4 or 6, not
> > sure at the moment) to start te FPGA (release global reset, Tristate etc.)
> > Then DONE will go HIGH.
> 
> Thanks! I don't think I left PROGRAM down long enough and/or didn't
> realize that PROGRAM needed to go back high before the magic started.
> I was thinking DONE would go low while PROGRAM was low.
> 
> - Pete

Certainly there is a minimum low time for the PROGRAM- signal.  That
should be in the data sheet. 

I could be wrong, but I don't think you need to pulse the PROGRAM-
signal to start the reconfiguration process.  In fact, I don't think you
can pulse PROGRAM- low by the FPGA itself.  The output will go tristate
before you can pull it up again.  You will need an external pullup
resistor to do that.  

I don't have the data sheet in front of me, but I am pretty sure that if
you pull PROGRAM- low (long enough), the chip begins the inititalization
by clearing the configuration memory.  This is indicated by DONE going
low and INIT- going low.  The memory clearing process repeats until you
release the PROGRAM- signal to a high state and the chip does one more
complete clear of config memory.  Then it releases INIT- and
configuration may begin.  

At least that is how it worked in the 4000 series and I have not seen
anything in the Spartan II data sheets that says otherwise.  But it is
possible I have not read carefully enough.  I often make assumptions
based on my prior knowledge.  That will get you in trouble every time.  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 42170
Subject: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Wed, 17 Apr 2002 11:52:37 -0600
Links: << >>  << T >>  << A >>




andreas wrote:

> On Tue, 09 Apr 2002 03:50:25 GMT, Ray Andraka <ray@andraka.com> wrote:
> Hi,
> I recently discovered a problem that not all applicable paths covered
> by a timespec were checked by the software.
>
> I had a multichannel design and the same timespec for all channels.
> But in the report I saw that the parts covered were only half for a
> certain channel. There were paths not meeting the timespec which
> didn't get reported !!!

I can't comment on your issue as I have never heard of this particular problem
however it does lead in very well to my point about timing simulation.  Even if you
feel you constrained your design well, even if the timing report has 100% coverage
of all paths in the design, mistakes can be made either by the software or many
times more likely, by the designer that will make it easy to mis-interpret the
static timing analysis.  I have used this story before on this news group but I will
use it again because it illustrates my point very well.  I was looking at another
designer's FPGA design that passed static timing analysis but failed in timing
simulation with timing violations.  The timing constraints were very well thought
out, covered most of the design including the failing path and was reported as
passing the constraint with some margin.  As for the timing simulation, the same
path had an event that landed smack dab in the middle of the setup window and would
fail after a few uS of simulation.  After a bit of investigation, I found that the
path in question was covered with a proper PERIOD constraint that matched what was
provided in the testbench however the same path had a MAXDELAY constraint set to the
same period value.  At first, this did not look to be a problem as they are set to
the same value and that path was indeed constrained to what is thought to be the
proper value.  However it turns out that this particular clock network, clocking was
being performed on both edges of the clock so some paths have half-period.  Again,
this generally would not be a problem if just the PERIOD constraint was used as it
will automatically accounts for dual-edge clocking however since a MAXDELAY was put
on the same path and the MAXDELAY has a greater precedence than the PERIOD
constraint it over-rode the PERIOD constraint thus putting an entire period
constraint on a path which needed a half-period constraint.  That path was easily
made in timing analysis as it had twice the necessary time to make the path however
timing simulation quickly identified that mistake that easily could have shown up
infrequently as data errors on some systems and look to the designer like there is a
problem in the silicon when in reality you can trace the problem back to a mistake
in timing constraints.

The moral of the story is people make mistakes and having different methods of
verification gives more opportunity to find those mistakes.  Not utilizing those
methodologies leaves the door open to possibly not identifying those problems until
it is too late.



> And concerning the post P&R simulation, there are a lot of cases were
> timing errors will be not found by this simulation. The simulator uses
> the max. time in all paths, also the clock paths. So a design might
> work in the simulator but since there is a skew between paths in
> practise the real implementation might have problems!

There is truth in what you say however timing simulation is not as inaccurate as you
might think or have others think with that statement.  It is true that simulators
can only choose one set of numbers for simulation and therefore when doing a true
worst-case simulation, all numbers are worst case including clock paths which for
absolute worst timing conditions does not paint an accurate picture, however for
most internal paths in the FPGA, the delays will track with each other.  You are not
going to have a data path and part of the clock domain running at min voltage, max
temperature and have another part of the same clock domain running at max voltage
and min temperate all at the same time.  Generally process variations can occur from
chip to chip and possibly different mask sets can change timing for two chips from
the same family however you will not see drastic process variations across a single
die and obviously it will use the same mask set.  These are the factors that
determine timing in the MIN and MAX timing in FPGAs therefore doing a true MIN-MAX
analysis is not going to yield you a true picture of the timing.  There may be very
small differences in timing from one routing resource to another similar resource or
from one LUT to another LUT in the same die however the safe-guards in the timing
numbers generally give you a large enough buffer to account for these differences.

The one place where this can be a big difference is clocked paths entering the chip
as external variances may not track as well as the internal variances I mention
above.  To address this, Xilinx has added to its simulation netlists a component
called the X_SUH (Guaranteed SetUp and Hold).  This is a component that sits
parallel with all registers who's input comes from an external pin (be it a CLB
register or IOB register) in which the Setup and Hold values are calculated uses the
MAX and MIN values for that data path.  If an input changes relative to its clock
within the Guaranteed window reported by the static timing analysis tool in the Data
Sheet Reports, External Setup and Hold section a timing violation should occur on
the X_SUH component and the instance name on that component should alert you to
which input relative to which clock had a violation.  This is one way to get around
the issue of simulators only being able to read in one set of numbers and we applied
it to what is in my opinion, the most relevant and only logical place to do that.

I probably got into more details than I should in this small discussion but I wanted
to address the statements made in this post.  Timing simulation may not be perfect
in how fast it runs, how easy it is to debug or even in the timing numbers it
provides however it does provide another outlet to verify the design ends up the way
it is intended and I feel it provides far more usefulness than most seem to realize
from the reading of these posts.  I would never call it a waste of time however some
designers may not have the time to do it and can yet produce a functional system.

--  Brian,  Stepping off my soapbox now



>
>
> Regards
> Andreas
>
> >You mention all timing constraints were met.  What about constraint coverage?
> >It is entierly possible to have all constraints met with only a small portion
> >of the design actually constrained.  If your design is passing a functional
> >simulation and timing, but does not work, the next step is to carefully examine
> >your timing constraints to make sure you haven't got something important
> >unconstrained, followed by doing a post-route simulation to verify that the
> >routed design does indeed match the input design.  There have been a few cases
> >where the xilinx tool is the culprit, but much more often it is the result of a
> >change in the synthesizer.
> >
> >al wrote:
> >
> >> We were using 3.1i and works fairly stable with no major problems. Last
> >> week, we loaded up the 4.1i and decided to give it a try. We used the same
> >> set of VHDL design files, UCF constraint and batch file. At first, tool
> >> seems working fine -- we are able to save compile time by about 40% and all
> >> timing constraints are meet. Well, not so happy yet -- the output binary
> >> doesn't not work in our hardware, seems like there is some sort of timing
> >> problem somewhere. We called up xilix hotline, this support guy by the name
> >> of Justin have no idea of what he is talking about -- keep telling me to do
> >> a post route timing simulation on my 1.6 million gate design. Anyway, bad
> >> tool + bad support = unhappy customer.



Article: 42171
Subject: Re: GND Outputs being optimized out using FPGA Express 3.6.1 in ISE4.2.01
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Wed, 17 Apr 2002 20:52:11 +0200
Links: << >>  << T >>  << A >>
"Austin Lesea" <austin.lesea@xilinx.com> schrieb im Newsbeitrag
news:3CBDA28C.8496D40F@xilinx.com...
> William,
>
> See:
>
>
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
1&getPagePath=9780
>
> For how to "keep" and "don't touch" instantiations so the tools don't rip
them
> out....

Hmm, strange, usually a simple

my_output <= '0';

works.

--
MfG
Falk





Article: 42172
Subject: Re: Problems with Nios 2.0
From: "James Srinivasan" <James_nospamSrinivasan@nospam.yahoo.com>
Date: Wed, 17 Apr 2002 20:25:40 +0100
Links: << >>  << T >>  << A >>
>     1-When I want to generate a Nios system module with the
> SOPC_BUILDER it gives me errors saying that:"does´nt find boot
> monitor, uname:unknown, grep:unknown...
>     2-On the other hand, when I try to run the bash shell I have also
> problems.It says me that 'bash.exe:can´t find /tmp file;create one'

The two problems are probably related to an incorrect install of CygWin. I'd
guess that the root (/) isn't set properly. In a *Windows* command prompt,
unmount / with "umount /" then remount e.g. "mount E:\\Altera\\CygWin /"
where E:\\Altera\\CygWin is where CygWin was installed, noting the double
\s.

Hopt this helps,

James





Article: 42173
Subject: Re: problem installing xilinx foundation 3.1 on a P4
From: Hari Devanath <harid@xilinx.com>
Date: Wed, 17 Apr 2002 14:49:31 -0600
Links: << >>  << T >>  << A >>
VAggelis,
Pentium 4 Processors were not available when Foundation 3.1i Software
was released, and this solution has not been fully tested by Xilinx.
Please refer this Answer for a work around:
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10634

Hope this helps,
Hari.

Vaggelis Tripolitakis wrote:

> Hello ppl ,
>
> I 'm trying to install Xilinx Foundation 3.1 (Licensed version) on a
> P4 machine and during the installation it crashed repeatedly showing
> the following error :
>
> "java.exe Application error...."
>
> I tried to install Foundation 4.1 and it worked OK but I don't have
> a license version...So anyone can help ?
>
> Thanks in advance
>
> Vaggelis Tripolitakis
> Undergraduate Student
> Microelectronics & Hardware Lab
> Technical University of Crete
> Greece


Article: 42174
Subject: Re: Programming for FPGA or ASIC
From: Hari Devanath <harid@xilinx.com>
Date: Wed, 17 Apr 2002 14:54:56 -0600
Links: << >>  << T >>  << A >>
Hi Prashanth,
In particular, if you want to write HDL for Xilinx devices, this is a good
place to start:
http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/preface.html
Hari.

Prashant wrote:

> hi,
> I read in a post previously that VHDL/Verilog programming style
> differs when being written for an FPGA from being written for an ASIC.
> Is there any website which mentions these differences ? I'm looking to
> see what should I take care of when programming for an FPGA.
>
> Thanks,
> Prashant




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