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Messages from 53000

Article: 53000
Subject: Re: Newbie Qn: Power connections with virtex FPGAs
From: chris.rosewarne@calyptech.com (Chris Rosewarne)
Date: 27 Feb 2003 18:38:22 -0800
Links: << >>  << T >>  << A >>
Jeniffer,

There are application notes on the Xilinx website explaining how to
connect serial EEPROMs to FPGA's for configuration, and others
explaining about the power requirements - these should answer your
questions,

regards,
Chris

J_Jeniffer@excite.com (Jeniffer) wrote in message news:<ded21c45.0302270252.7d1bb462@posting.google.com>...
> Hello,
> 
> This is a newbie question. Apologies if it is already discussed.
> I can't seem to find it.
> 
> I am a student and developing a PCB with virtex (2.5V) device. The 
> device is to be programmed with XC1800 series serial EEPROM. The 
> serial EEPROM is to be programmed through the JTAG interface.
> 
> My question is what are the values to which VCC and VCCO should
> be tied in order for a proper operation? From data sheets, I 
> understand, 
> 
> Virtex VCC=2.5 and VCC0=3.3V for bank 2 and 3 so that it can operate
> with the 3.3V serial EEPROM. And for XC1800, VCC=3.3V and VCCO=2.5V
> so that it can operate with virtex (am I right?). And I tie VREF of 
> JTAG connector to 3.3V so that its output is 3.3V compatible with
> serial EEPROM. Now my question is, since VCCO is 2.5V for a serial 
> EEPROM, the output of serial EEPROM is 2.5V compatible and will this
> be o.k with the JTAG circuitry in the parallel cable? And if I later
> use a virtex-E device, then this voltage will be 1.8V. Will the 
> JTAG circuitry make the necessary adjustment to be compatible with
> 1.8V? 
> 
> Is it possible to get internal details (say at transistor diagram
> level) of this voltage conversion circuits?
> 
> If I use a serial EEPROM to program the device, then what would I
> do with other modes of configuration pins? Say selectMAP or JTAG?
> Can I leave them unconnected? Is it safe?
> 
> Thankyou for your time,
> Jeniffer

Article: 53001
Subject: Implementing Picoblaze with Xilinx Webpack 4.2
From: scottiecs@yahoo.com (Scott)
Date: 27 Feb 2003 23:32:02 -0800
Links: << >>  << T >>  << A >>
Hi all.  I am new to programming FPGA's.  Ken Chapman from Xilinx
suggested using his Picoblaze to implement UART on the Xilinx Spartan
IIe FPGA (he suggested this over his XAPP223).  That is the main
function I need as of now (I will also need other functions of
Picoblaze later on).  Right now i just want to test the UART
communication(PC to FPGA).  Like I said I am new to VHDL and FPGA's so
I am in the need for a tutorial on how to acutally implement the given
Picoblaze files with Xilinx Webpack 4.2.  I know this is probably
asking a lot, but I do not know where else to turn.  Any help in would
be much appreciated. Also if anyone could suggest an easy to follow
and understand tutorial/website/book on the start to finish steps of
designing, synthesizing, test benching etc... that would be awesome.

Thanks in advance
Scott Sullivan

Article: 53002
Subject: 10 MHz Clock out of 30 MHz
From: "Dirk Dörr" <dirk.doerr@delsy.de>
Date: Fri, 28 Feb 2003 10:33:47 +0100
Links: << >>  << T >>  << A >>
Hello!

Does anyone know how to generate a 10 MHz Clock (and 2 other signals)
derived from 30 MHz?

What I need would look like:

30 MHz:        _-_-_-
10 MHz:        ___---

SigA:             --_---
SigB:             -----_

(Best viewed using Courier font)

It is for a design that consists of a Xilinx XC5204 using VHDL with
Foundation 3.1 FPGA Express.

Thanks in advance

    Dirk Dörr




Article: 53003
Subject: Re: 10 MHz Clock out of 30 MHz
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Fri, 28 Feb 2003 12:30:17 +0000 (UTC)
Links: << >>  << T >>  << A >>
"Dirk Dörr" <dirk.doerr@delsy.de> wrote:
: Hello!

: Does anyone know how to generate a 10 MHz Clock (and 2 other signals)
: derived from 30 MHz?

: What I need would look like:

: 30 MHz:        _-_-_-
: 10 MHz:        ___---

: SigA:             --_---
: SigB:             -----_

: (Best viewed using Courier font)

: It is for a design that consists of a Xilinx XC5204 using VHDL with
: Foundation 3.1 FPGA Express.

If you only need about 50 % duty cycle, but no alignment to the 30 MHz
clock, build a cyclic counter to 3 with the  30 MHz clock, and set a
Flipflop on the posedge of the 30 MHZ when the counter is 3 and reset that
flipflop asynchrounous with a signal generates from negedge clock when the
countet is two.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 53004
Subject: Virtex II - Driving more than one global clock net from one incoming clock pin
From: "Sam Duncan" <damn_spam2001@yahoo.co.uk>
Date: Fri, 28 Feb 2003 14:58:13 +0200
Links: << >>  << T >>  << A >>
Hi

I'm using an XC2V1000 and trying to drive two global clock nets at different
speeds (using DCMs), using only one clock input pin.  I get errors from
ngdbuild if I try to drive two IBUFG's from the same pad.  If I drive one
IBUFG and split the output to two DCM's, the levels of logic reported on my
clock net (post place and route) increase from 2 to 19.  Is it possible to
drive two DCM's and two clock nets from one input pin, or should there be a
separate input for every DCM/clock net?

Many thanks

Sam

--




Article: 53005
Subject: SDA FIR Filter...
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Fri, 28 Feb 2003 15:42:21 +0200
Links: << >>  << T >>  << A >>
I have implemented a polyphase serial DA fir filter. A new sample is given
as input every 8 clock cycles, while the filter takes 5 clock cycles to
generate an output. Everything works perfectly in simulation, however I only
obtain a constant output when I program the FPGA (Spartan 2e) and test with
logic analyser. I have tested the output interface, aswell as checked the
inputs to the filter, and all are fine. Can anyone possibly offer an idea as
to why this is happening?

Thanks

Adrian



Article: 53006
Subject: error in the design
From: cvmnk@yahoo.com (naveen)
Date: 28 Feb 2003 07:56:14 -0800
Links: << >>  << T >>  << A >>
hi,
 i have designed a lfsr usign macros of the heirarchy elements. my
circuit is not synthesiszing. it s givin me an error.
    like 
     error:pack:679:   unable to obey constraints
  in the web source
     and the soluiton in the xilinx answers sheet is to convert
"u_set" to "h_set"
.
   i dint understand this message.
     iam workin with xilinx vertex 2 fpga
 thanx
 cvm

Article: 53007
Subject: Re: How to maintain pipeline delays
From: "Jonathan Bromley" <jonathan@oxfordbromley.u-net.com>
Date: Fri, 28 Feb 2003 16:45:45 -0000
Links: << >>  << T >>  << A >>
"jonno" <jjacox@NULLpmdi.com> wrote ...
> I have some pipelined megafunctions that need to be synchronized with
other
> data signals for output. Currently I just put the other signals through
> flip-flops to maintan their sequence while the rest of the data goes
through
> their pipeline functions. I am fairly new at this and am thinking there
must
> be a better way to keep the data together other than wasting flip flops to
> hold the non-pipelined data.... Is there?

Not really.

If you are in Xilinx you could look at using SRL16s as a compact
way to implement the "dumb" pipe-matching delay.

Sometimes you find that you can allow the data to get out of
step, and bring it back together again later thanks to some
other pipelined operations.  But you need a clear head and
lots of coffee to deal with that kind of thing.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Article: 53008
Subject: Re: Extend PCI slot to outside PC
From: gs@alpha-data.com (Graham Smart)
Date: 28 Feb 2003 09:00:08 -0800
Links: << >>  << T >>  << A >>
You could try http://www.magma.com/ they have full and half sized PCI
adapters for PCMCIA. We use them sucessfully with our Virtex PCI
cards.

Regards

Graham
=============================
Graham Smart
Alpha Data
e: mailto:gs@alpha-data.com
w: http://www.alpha-data.com
=============================


"Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message news:<9fmSmWm3CHA.2508@exchnews1.main.ntu.edu.sg>...
> Anyway, my PC has PCI to PCMCIA card. is there any PCMCIA to PCI ? 
> Especially for laptop users ?
> :)
> 
> cheers,
> 
> Basuki
> 
> -----Original Message-----
> From: Thomas Rudloff [mailto:thomas rudloff@gmx.net]
> Posted At: Thursday, February 27, 2003 4:31 PM
> Posted To: fpga
> Conversation: Extend PCI slot to outside PC
> Subject: Re: Extend PCI slot to outside PC
> 
> 
> Oh no, the stubs on a PCI bus must not be longer than 2 inch.
> You might have success if you make sure that it is in the last slot. 
> Thus
> just increasing the length of the bus.
> 
> AFAIK there are cards available that add a sub bus to the PCI bus.
> This should be the more reliable solution.
> 
> Thomas
> 
> fizz wrote:
> 
> > you are crazy!  :)
> >
> > but i think u can try it ..  use a cables  , like an ATAPI ( IDE ) 
>  cable .
> > When the cable is about 50cm long ,the delay is no more than 1ns . on 
>  the
> > 66Mhz PCI bus .
> > it's not matter.
> >
> > --
> >                             sincerely yours
> >                                wufengzhi
> > ------------------------------------------
> > email:wufz@magima.com.cn
> > ------------------------------------------
> >
> > "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message
> > news:NixKKci3CHA.2508@exchnews1.main.ntu.edu.sg...
> > Hi all,
> >
> > I have just bought an FPGA development board and it must be attached 
>  to the
> > PC's PCI slot. As it is attached inside the PC, so it's hard to tap 
>  the
> > jumper or FPGA pin and moreover it is not flexible. I am willing to 
>  extend
> > this PCI slot to outside of the PC, using cables and so on.
> >
> > Anybody has done this before ?  any advice ? is it safe ?
> >
> > or .. is there any company who made this, so i can just buy :)
> >
> > Thanks.
> >
> > Basuki Keren

Article: 53009
(removed)


Article: 53010
Subject: guided par question
From: agunos@cox.net (ed)
Date: 28 Feb 2003 09:02:22 -0800
Links: << >>  << T >>  << A >>
I have a design in a virtex2 which connects to a PCI interface chip
(plx9080). With all other things begin equal (same edf file, same ucf
file, same effort level or higher), the latest revision to my design
only works (talks to the PCI bus) if I perform a guided place and
route with a guide file from the previous working implementaion. I've
ran the design without the par guide file AND with higher timing
constraints succesfully and it still does not work. Without probing
the bus signals, can I infer anything from this? Basically, can I
reasonably say that this is not a timing issue? And if not, what else
would a guided par affect?

Thanks,
Ed

Article: 53011
Subject: Re: 10 MHz Clock out of 30 MHz
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 28 Feb 2003 09:06:46 -0800
Links: << >>  << T >>  << A >>
Just take two LUTs+flip-flops with a common clock, and feed the two Q
outputs back to the LUT inputs. You might call this a state machine. The
versatility of the look-up table allows you to generate any divide by 3
or divide by 4 that you can possibly imagine.
Even with paper and pencil, this should take only minutes to design.

Peter Alfke, Xilinx Applications.
==========================
"Dirk Dörr" wrote:
> 
> Hello!
> 
> Does anyone know how to generate a 10 MHz Clock (and 2 other signals)
> derived from 30 MHz?
> 
> What I need would look like:
> 
> 30 MHz:        _-_-_-
> 10 MHz:        ___---
> 
> SigA:             --_---
> SigB:             -----_
> 
> (Best viewed using Courier font)
> 
> It is for a design that consists of a Xilinx XC5204 using VHDL with
> Foundation 3.1 FPGA Express.
> 
> Thanks in advance
> 
>     Dirk Dörr

Article: 53012
Subject: Avnet Cilicon Xilinx Virtex-E development kit
From: "Michael Nicklas" <michaeln@nospam.slayer.com>
Date: Fri, 28 Feb 2003 17:07:11 -0000
Links: << >>  << T >>  << A >>
Hi

I'm thinking of investing in the Avnet Xilinx Virtex-E development kit and
wondered if anybody had any previous experience with them and any opinions
of them as a company, in terms of product quality, tech support etc.

Much appreciated.

--
Cheers!

Mike



Article: 53013
Subject: Re: How to maintain pipeline delays
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 28 Feb 2003 09:16:04 -0800
Links: << >>  << T >>  << A >>
Xilinx invented the SRL16 for this very purpose.
Any 4-input LUT can not only be either a ROM or a RAM, but can also be
used as a shift register, with the 4 inputs defining the shift register
length, 1...16.
The SRL16 has also spawned many other ideas, as described in three
articles on the Xilinx website:

http://support.xilinx.com/support/techxclusives/SRL16-techxclusive2.htm

Peter Alfke
===========================
jonno wrote:
> 
> Hi,
> 
> I have some pipelined megafunctions that need to be synchronized with other
> data signals for output. Currently I just put the other signals through
> flip-flops to maintan their sequence while the rest of the data goes through
> their pipeline functions. I am fairly new at this and am thinking there must
> be a better way to keep the data together other than wasting flip flops to
> hold the non-pipelined data.... Is there?
> 
>   jon

Article: 53014
Subject: IBUF : Pullup Resistors
From: "S Embree" <embree@avionicinstruments.com>
Date: Fri, 28 Feb 2003 09:22:23 -0800
Links: << >>  << T >>  << A >>
Hi, 
Does anyone know how to configure a pullup resistor at an input?  
I am trying to use the library component pullup resistor to 
pullup an input.  I first attempted to route the input directly 
to the pullup resistor, but it wouldn't synthesize, so I inserted 
an IBUF between the input and the pullup resistor.  My problem 
is that the input is not pulled up high enough.  I measured, 
and it is only pulled up to 2.4V and sometimes does not 
register as a logic 1.  Does anyone know how to configure 
a pullup resistor at an input? 

Thanks!

Article: 53015
Subject: Re: How to maintain pipeline delays
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Fri, 28 Feb 2003 17:30:50 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <b3o3nq$drg$1$8302bc10@news.demon.co.uk>,
Jonathan Bromley <jonathan@oxfordbromley.u-net.com> wrote:
>Sometimes you find that you can allow the data to get out of
>step, and bring it back together again later thanks to some
>other pipelined operations.  But you need a clear head and
>lots of coffee to deal with that kind of thing.

OR a good retiming tool to balance everything for you.

One thing nice about retiming is you can create blocks which MUST have
registers but don't have them in the initial design (eg, a BlockRAM
with a negative edge clock instead of a normal clock) and have
retiming force delays onto those locations.

Unfortunatly, only now is retiming starting to really work its way
into the CAD flow.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 53016
Subject: Re: IBUF : Pullup Resistors
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 28 Feb 2003 10:17:32 -0800
Links: << >>  << T >>  << A >>
What device family?
Have you ever tried to configure the same pin also as a tristated output
with a pull-up resistor?
Peter Alfke

S Embree wrote:
> 
> Hi,
> 
> Does anyone know how to configure a pullup resistor at an input?
> 
> I am trying to use the library component pullup resistor to pullup an
> input. I first attempted to route the input directly to the pullup
> resistor, but it wouldn't synthesize, so I inserted an IBUF between
> the input and the pullup resistor. My problem is that the input is not
> pulled up high enough. I measured, and it is only pulled up to 2.4V
> and sometimes does not register as a logic 1. Does anyone know how to
> configure a pullup resistor at an input?
> 
> Thanks!

Article: 53017
Subject: PCB board design software vs outsourcing?
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Fri, 28 Feb 2003 18:55:54 +0000 (UTC)
Links: << >>  << T >>  << A >>
I'm in the very VERY preliminary planning stages, and looking to do
one or more FPGA board designs with multiple Gb (1000-baseSX) ports &
tranceivers.  Thus there will be multiple 1.25 gigabaud differential
pair traces running around, between the FPGA and the transcievers.

Whats the general (rough order ballpark) figure for an ousourced
design consisting of an FPGA, 8 transceivers, a DDR SO-DIMM slot, and
a compact flash/bootup?

Similarly, if doing it in-house, what are the prefered tool-suites?
Is it the cadence branded tools?  The cadence buyout ORCAD flow?
Mentor Graphics flow?

Thanks.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 53018
Subject: Re: PCB board design software vs outsourcing?
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Fri, 28 Feb 2003 19:10:45 GMT
Links: << >>  << T >>  << A >>
Nicholas C. Weaver wrote:
> I'm in the very VERY preliminary planning stages, and looking to do
> one or more FPGA board designs with multiple Gb (1000-baseSX) ports &
> tranceivers.  Thus there will be multiple 1.25 gigabaud differential
> pair traces running around, between the FPGA and the transcievers.
> 
> Whats the general (rough order ballpark) figure for an ousourced
> design consisting of an FPGA, 8 transceivers, a DDR SO-DIMM slot, and
> a compact flash/bootup?
> 
> Similarly, if doing it in-house, what are the prefered tool-suites?
> Is it the cadence branded tools?  The cadence buyout ORCAD flow?
> Mentor Graphics flow?

As immediate question : What is the timeframe you're thinking of ?
A few points :
You cannot decide to do an inhouse board design without previous
knowledge. Whatever tool you choose, it takes some time to figure
out and become comfortable with. It takes at least 6 month to become
productive and another for the bells and whistles. And as I see it,
you'll be using 2 tools, one the the pcb and another one for the FPGA.
And each tool is the mentioned complexity.
A design working with subnanoseconds is far from trivial, without
some knowledge hardly doable. There is more to it than 'just do a
multilayer'.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net


Article: 53019
Subject: Re: PCB board design software vs outsourcing?
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Fri, 28 Feb 2003 19:20:49 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <c148d133f3627dcc857a52d54fcea3fc@news.teranews.com>,
Rene Tschaggelar  <tschaggelar@dplanet.ch> wrote:
>As immediate question : What is the timeframe you're thinking of ?

Probably 9 month out, or a year.  So there is the time to get up to
speed on the tools involved, probably by doing a much simpler, slow
speed demoboard first.

And the other tradeoff is that I don't know yet, but I may need to do
2-3 separate designs over a 3 year period, which lends itself to
in-house design.

>A few points :
>You cannot decide to do an inhouse board design without previous
>knowledge. Whatever tool you choose, it takes some time to figure
>out and become comfortable with. It takes at least 6 month to become
>productive and another for the bells and whistles. And as I see it,
>you'll be using 2 tools, one the the pcb and another one for the FPGA.
>And each tool is the mentioned complexity.
>A design working with subnanoseconds is far from trivial, without
>some knowledge hardly doable. There is more to it than 'just do a
>multilayer'.

Thats the concern: between the high speed differential pairs (you have
to get the V2Pro/Stratix GX transceivers interfaced with the optical
components, giving 1.25 GHz board traces) and a DDR-DRAM bus, its
non-trivial even when the "It's a prototype, throw more layers at the
problem" response is invoked.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 53020
Subject: Re: PCB board design software vs outsourcing?
From: Mike Treseler <tres@fluke.com>
Date: Fri, 28 Feb 2003 11:35:16 -0800
Links: << >>  << T >>  << A >>


Nicholas C. Weaver wrote:
> I'm in the very VERY preliminary planning stages, and looking to do
> one or more FPGA board designs with multiple Gb (1000-baseSX) ports &
> tranceivers.  Thus there will be multiple 1.25 gigabaud differential
> pair traces running around, between the FPGA and the transcievers.
> 
> Whats the general (rough order ballpark) figure for an ousourced
> design consisting of an FPGA, 8 transceivers, a DDR SO-DIMM slot, and
> a compact flash/bootup?

If you mean a pwb layout from an existing schematic netlist, I would
guess about $10K.

> Similarly, if doing it in-house, what are the prefered tool-suites?
> Is it the cadence branded tools?  The cadence buyout ORCAD flow?
> Mentor Graphics flow?

The preferred tools are the ones you have already used successfully.

Consider taking a preliminary schematic to a layout contractor.


        -- Mike Treseler


Article: 53021
Subject: Re: 10 MHz Clock out of 30 MHz
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Fri, 28 Feb 2003 14:42:43 -0500
Links: << >>  << T >>  << A >>
Peter,
    I wonder if the problem is that he wants a 50% duty cycle from the
divide by 3.  Doesn't that complicate things substatially?  Otherwise you
are absolutely correct.

Theron


"Peter Alfke" <peter@xilinx.com> wrote in message
news:3E5F9726.ECF7E6CE@xilinx.com...
> Just take two LUTs+flip-flops with a common clock, and feed the two Q
> outputs back to the LUT inputs. You might call this a state machine. The
> versatility of the look-up table allows you to generate any divide by 3
> or divide by 4 that you can possibly imagine.
> Even with paper and pencil, this should take only minutes to design.
>
> Peter Alfke, Xilinx Applications.
> ==========================
> "Dirk Dörr" wrote:
> >
> > Hello!
> >
> > Does anyone know how to generate a 10 MHz Clock (and 2 other signals)
> > derived from 30 MHz?
> >
> > What I need would look like:
> >
> > 30 MHz:        _-_-_-
> > 10 MHz:        ___---
> >
> > SigA:             --_---
> > SigB:             -----_
> >
> > (Best viewed using Courier font)
> >
> > It is for a design that consists of a Xilinx XC5204 using VHDL with
> > Foundation 3.1 FPGA Express.
> >
> > Thanks in advance
> >
> >     Dirk Dörr



Article: 53022
Subject: Re: 10 MHz Clock out of 30 MHz
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 28 Feb 2003 12:29:10 -0800
Links: << >>  << T >>  << A >>
I don't think he wants 50% duty cycle. If he wants, I published a design
in XCell a few years ago. Without a PLL, it has to rely on a 50% duty
cycle of the incoming clock. There is no other way...

Peter Alfke
===========================
Theron Hicks wrote:
> 
> Peter,
>     I wonder if the problem is that he wants a 50% duty cycle from the
> divide by 3.  Doesn't that complicate things substatially?  Otherwise you
> are absolutely correct.
> 
> Theron
> 
> "Peter Alfke" <peter@xilinx.com> wrote in message
> news:3E5F9726.ECF7E6CE@xilinx.com...
> > Just take two LUTs+flip-flops with a common clock, and feed the two Q
> > outputs back to the LUT inputs. You might call this a state machine. The
> > versatility of the look-up table allows you to generate any divide by 3
> > or divide by 4 that you can possibly imagine.
> > Even with paper and pencil, this should take only minutes to design.
> >
> > Peter Alfke, Xilinx Applications.
> > ==========================
> > "Dirk Dörr" wrote:
> > >
> > > Hello!
> > >
> > > Does anyone know how to generate a 10 MHz Clock (and 2 other signals)
> > > derived from 30 MHz?
> > >
> > > What I need would look like:
> > >
> > > 30 MHz:        _-_-_-
> > > 10 MHz:        ___---
> > >
> > > SigA:             --_---
> > > SigB:             -----_
> > >
> > > (Best viewed using Courier font)
> > >
> > > It is for a design that consists of a Xilinx XC5204 using VHDL with
> > > Foundation 3.1 FPGA Express.
> > >
> > > Thanks in advance
> > >
> > >     Dirk Dörr

Article: 53023
Subject: Re: IBUF : Pullup Resistors
From: "S Embree" <embree@avionicinstruments.com>
Date: Fri, 28 Feb 2003 12:41:42 -0800
Links: << >>  << T >>  << A >>
It's a Spartan II, and I'm using Xilinx ISE 5.1. 
I tried to configure the pin as an output, but ISE 
refuses to connect the pullup node to the rest of 
the circuit (because it thinks that I am want to 
drive an output, when what I really want to do is 
drive an input).  How could I use a tristate buffer 
to pull-up the resistor?



Article: 53024
Subject: Re: IBUF : Pullup Resistors
From: Ad Verschueren <ad.verschueren@NOxs4all.SPAMnl>
Date: Fri, 28 Feb 2003 22:31:56 +0100
Links: << >>  << T >>  << A >>
S Embree wrote:

> It's a Spartan II, and I'm using Xilinx ISE 5.1.
> 
> I tried to configure the pin as an output, but ISE refuses to connect 
> the pullup node to the rest of the circuit (because it thinks that I am 
> want to drive an output, when what I really want to do is drive an 
> input). How could I use a tristate buffer to pull-up the resistor?


Found out a few weeks ago that ISE 5.1 does not 'like' the PULLUP and
PULLDOWN components - had to change the IDaSS-to-Xilinx Verilog rulebase
to place the PULLUP and PULLDOWN I/O properties in the .ucf file (KEEPER
was already there after earlier experiments ;-)). Works for inputs, TS
outputs and bidir connectors (KEEPER not for pure inputs, though).

Ad Verschueren






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