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Messages from 53050

Article: 53050
Subject: Re: several fpga high bandwidth questions
From: nahum_barnea@yahoo.com (Nahum Barnea)
Date: 1 Mar 2003 13:40:05 -0800
Links: << >>  << T >>  << A >>
Austin,
I think that IBIS model will answer the electrical point of view - rise time,
fall time etc - but will not answer the question: can Xilinx IO register
capture the RLDRAM data rates 640 Mbps (RLDRAM-I) or 800 Mbps (RLDRAM-II).
I expect this answer from xilinx experts such as you ...

Bye,
NAHUM. 

Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3E5E3835.620D8772@xilinx.com>...
> Nahum,
> 
> Go the the supplier websites, download their IBIS models, and simulate the
> IOs you wnat to use at the frequencies you desire.
> 
> This will answer your questions.
> 
> Austin
> 
> Nahum Barnea wrote:
> 
> > Hi.
> > Several questions.
> >
> > 1. What Altera fpga family is an alternative to Spartan-IIE family ?
> > 2. I want to design an interface to Micron's RLDRAM device - that is
> >    I/O bandwidth of 640 Mbps (HSTL). what fpga can I use ?
> > 3. Next generation of Micron's RLDRAM device will have a bandwidth of
> >    800 Mbps (HSTL). Do I have an fpga today that will be able to support
> >    this bandwidth ?
> >
> > Bye,
> > NAHUM

Article: 53051
Subject: Re: Atmel and Hotworks boards for sale
From: Ray Andraka <ray@andraka.com>
Date: Sat, 01 Mar 2003 21:40:19 GMT
Links: << >>  << T >>  << A >>


I also have three National Semiconductor ClayFun  boards, each
with 2 CLAY 10's and 1 CLAY 31 on them, and two National
semsiconductor FCMFUN boards.  If anyone is interested, let me
know on those.

Ray Andraka wrote:

> I'm cleaning out my office, and came across two boards I
> wish to get rid of.  I've posted both on ebay:
>
> An Atmel AT6005 prototyping board
> http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=3404172147
>
> and a VCC XC6216DS Hotworks board:
> http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=3404173840
>
> I'm posting here since you all would be the most likely to
> be interested in such boards.
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin
> Franklin, 1759

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin,
1759






Article: 53052
Subject: Re: several fpga high bandwidth questions
From: nahum_barnea@yahoo.com (Nahum Barnea)
Date: 1 Mar 2003 13:43:29 -0800
Links: << >>  << T >>  << A >>
Hi.
ThankX for the response.
The LVDS stuff is not relevant.
I need to interface with Micron's RLDRAM device.
This means HSTL 640 Mbps.

Bye,
NAHUM.


mrand@my-deja.com (Marc Randolph) wrote in message news:<15881dde.0302271053.31523488@posting.google.com>...
> nahum_barnea@yahoo.com (Nahum Barnea) wrote in message news:<fc23bdfc.0302270727.918478c@posting.google.com>...
> > Hi.
> > Several questions.
> > 
> > 1. What Altera fpga family is an alternative to Spartan-IIE family ?
> 
> This sounds just far enough away from homework that I'll answer it. 
> The way the questions are posed though, that was the first thing that
> crossed my mind.
> 
> It is difficult to compare across vendors because of the unique
> features of each.  Spartan-IIE is a cost optimized Virtex-E, so
> everywhere you see me mention Virtex-E, it should also apply to
> Spartan-IIE.
> 
> My personal opinion is that the Virtex-E falls between the Apex 20KE
> and the Apex II families, although that depends on your exact needs
> and the exact design.  The Apex 20KE has different I/O support than
> the Virtex-E.  Unfortunately Altera doesn't have a low cost version of
> those, although they offer hardwire for higher volume cost reduction. 
> Also, last time I checked, the Apex 20KE was priced VERY competitively
> - so for all I know, now-a-days it might be compariable in price to
> the Spartan-IIE.
> 
> > 2. I want to design an interface to Micron's RLDRAM device - that is
> >    I/O bandwidth of 640 Mbps (HSTL). what fpga can I use ?
> 
> I don't know about the HSTL part of it, but for high speed LVDS I/O:
> 
> Xilinx: Virtex-II and above (add Virtex-E if you lower the frequency
> slightly)
> Altera: Apex 20KE and above
> 
> > 3. Next generation of Micron's RLDRAM device will have a bandwidth of
> >    800 Mbps (HSTL). Do I have an fpga today that will be able to support
> >    this bandwidth ?
> 
> Same answer as #2, except the Virtex-E.
> 
>    Marc

Article: 53053
Subject: FIR Filter from Xilinx
From: "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg>
Date: Sun, 2 Mar 2003 06:25:45 +0800
Links: << >>  << T >>  << A >>
Hi,
=20
I'm newbie in implementation filter in FPGA. I've just create a =
distributed arithmetic FIR filter from Xilinx Coregen. The input signal =
is 12 bit and the filter coef bit resolution is 12 bit. Thus, it makes =
the output signal resolution is about 24 bit. My The bit resolution of =
my DAC is 12 bit. How to reduce from 24 to 12 bit ?
=20
pls, gimme advice as i'm newbie in this area.
=20
Thanks.
=20
Basuki


Article: 53054
Subject: Re: FIR Filter from Xilinx
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Sat, 01 Mar 2003 23:28:02 GMT
Links: << >>  << T >>  << A >>


Basuki Endah Priyanto wrote:
> Hi,
>  
> I'm newbie in implementation filter in FPGA. I've just create a 
 > distributed arithmetic FIR filter from Xilinx Coregen. The input
 > signal is 12 bit and the filter coef bit resolution is 12 bit.
 > Thus, it makes the output signal resolution is about 24 bit. My
 > The bit resolution of my DAC is 12 bit. How to reduce from 24
 > to 12 bit ?

Shift right ?
Truncate ?

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net


Article: 53055
Subject: How to select the chip before using FPGA?
From: wangmanxi@yahoo.com (siriuswmx)
Date: 2 Mar 2003 00:33:49 -0800
Links: << >>  << T >>  << A >>
Hi, 
  I am first time to use FPGA,  i want to realize demodulation in
FPGA, but  you know, there are so mang chips with all kinds capacity
and speed from several companies.
 Someone told me that i must calculate sum of the total arrays i shall
use before selecting the best chip.  Could you tell me How to
calculate it?
  thank you very much !
  Best reguards,
 
wangmanxi    3*

Article: 53056
Subject: Re: 10 MHz Clock out of 30 MHz
From: "Dirk Dörr" <dirk.doerr@delsy.de>
Date: 2 Mar 2003 10:40:16 GMT
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote in news:3E5FE201.704E22FE@xilinx.com:

> This makes it a bit more complicated, since the outputs need to change
> on either edge of the incoming clock.


> It can still be done fairly simply assuming the incoming 30 MHz has a
> reasonable duty cycle. Otherwise you need a PLL or DLL

> Here is my old article that talks about the subject.

> http://www.xilinx.com/xcell/xl33/xl33_30.pdf


First of all thanks for the help.

Yes 50 % duty cycle is needed. In our first aproch we got the clock but 
with some glichtes appearing. 

Meanwhile we found a solution that is similiar to your approch.

There have been some problems in synthesise a design using raising and 
falling edge (Simulation works but fpga express complains). 


Thanks 


    	Dirk Dörr 

 


Article: 53057
Subject: Re: Design Manager in ISE 5.x
From: "Markus Meng" <meng.engineering@bluewin.ch>
Date: Sun, 2 Mar 2003 12:14:04 +0100
Links: << >>  << T >>  << A >>
No advise,

it doesn't exist anymore. You have to use the Project Navigator ...

markus

"Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> schrieb im Newsbeitrag
news:xmDMUVD4CHA.352@exchnews1.main.ntu.edu.sg...
Hi,

I am quite surprise coz i can not find Xilinx Design Manager in ISE 5.1i

Previously, I am using ISE 4.2i and Design Manager was still there for my
FPGA implementation.

Any advice ?


Thanks.

Cheers,

Basuki




Article: 53058
Subject: Re: How to select the chip before using FPGA?
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Sun, 02 Mar 2003 11:40:10 GMT
Links: << >>  << T >>  << A >>
siriuswmx wrote:
> Hi, 
>   I am first time to use FPGA,  i want to realize demodulation in
> FPGA, but  you know, there are so mang chips with all kinds capacity
> and speed from several companies.
>  Someone told me that i must calculate sum of the total arrays i shall
> use before selecting the best chip.  Could you tell me How to
> calculate it?


You first have to select a manufacturer.
Choose the one where you have better support, eg a
colleague familiar with the technolgy with sufficient
time to introduce you.
Then download their free tool. It might take you 2 weeks
to become familiar. In case you don't have a manufacturer
preference try another one too.

The FPGA is selected as follows :

-Estimate the number of Flipflops.
  A 16bit counter takes 16 flipflops, when autoloading it
  takes 32 flipflops
-Compare the number of logic inputs to the matrix.
  A macrocell has a certain number of inputs, and when they
  are exceeded another macrocell is taken, its flipflop
  unused.
-Any development uncertainities, unknown functions ?

-Do a simulation first
  Those packages I know let you design without specifying
  the chip. At compile time, the chip is suggested.

-Take the next bigger for the prototype, as the
  compiletime increases when space becomes thight and/or
  a lot of optimizing options are required


Depending on the number of chips used it might make sense
to settle for just a few types, to keep storage cost low.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net


Article: 53059
Subject: Re: SDA FIR Filter...
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Sun, 2 Mar 2003 14:52:23 +0200
Links: << >>  << T >>  << A >>
>
> >I have implemented a polyphase serial DA fir filter. A new sample is
given
> >as input every 8 clock cycles, while the filter takes 5 clock cycles to
> >generate an output. Everything works perfectly in simulation, however I
only
> >obtain a constant output when I program the FPGA (Spartan 2e) and test
with
> >logic analyser. I have tested the output interface, aswell as checked the
> >inputs to the filter, and all are fine. Can anyone possibly offer an idea
as
> >to why this is happening?
> >
> >Thanks
> >
> >Adrian
> >
>
> You should run delay back-annotated simulations after P&R to see if
> this is a timing problem. You might be having really bad setup
> problems to see constant output. Also how are you resetting the
> design? Do you expect any internal state to be at a certain value
> during your RTL simulations ? If you have external reset, are you
> taking your chip off reset ?
>

The design is meant to run constantly, and so I do not expect any prior
values or initial states. Any spurious values in FF's and latches at startup
have no effect on the transient operation of the design. There is no reset
except right at the output where I have an accumulator. This is controlled
by a microcontroller. Should I have a reset on the filters at startup? I
can't see how I am getting any setup problems, as the design runs at a
maximum of 32 MHz, while the slowest net limits me to a maximum speed of
about 110MHz.

thanks

adrian



Article: 53060
Subject: University Research Scholarships
From: abb_ami2002@yahoo.com (Dr. Abbes Amira)
Date: 2 Mar 2003 07:04:12 -0800
Links: << >>  << T >>  << A >>
University Research Scholarships
The Queen's University of Belfast is offering a number of Research
Scholarships for take-up in October 2003 for full-time doctoral study
in the School of Computer Science.
Closing date for receipt of applications: 15 May 2003. 
Please see below for Further information about the proposed projects. 
Application forms can be downloaded from the web site:
http://www.qub.ac.uk/ado/postgrad/download.html
and should be sent to: 
 Admissions Office
Queen's University Belfast
Belfast
Northern Ireland
BT7 1NN

Proposed Projects:
Image and Signal Processing Applications: 
Design and Implementation 
(3 projects)

Supervisors:
Dr  Abbes Amira (Room G23)
Dr Ahmed Bouridane (Room 2.15) 

Project1: An FPGA based Coprocessor for Processing Medical Images 
Supervisors: A.Bouridane, A.Amira
Project2:  A Heterogenous System for Reconfigurable Hardware Design 
Supervisors: A.Amira, A.Bouridane
Project3: Computer Graphics based Wavelets Transforms: 
Compression, Multiresolution Curves and Surfaces 
Supervisors: A.Amira, A.Bouridane





1. Introduction
     
        The "Field Programmable Gate Array" FPGA is an integrated
circuit that contains many identical logic cells that can be viewed as
standard components.  Each logic cell can independently take on any
one of a limited set of functionalities.  The individual cells are
interconnected by a matrix of wires and programmable switches.
      Areas such as signal processing and medical imaging require
enormous computing power. It is the aim of these PhD proposals to use
FPGA as a low cost accelerator for particular algorithms used in such
applications.
      The systems, known as Custom Computing Machines (CCMs), use an
FPGA to provide hardware for the efficient computation of the
intensive, parallel, portions of an algorithm while leaving the
remaining code to be executed on the host processor. Researchers have
shown that CCMs can provide more than ten times better performance
than standard microprocessors when addressing specific problems. As
integration levels grow, the potential for providing parallelism with
the programmable fabric of the FPGA, will realise performance levels
several orders of magnitude higher than those possible with
microprocessors. Another key feature of FPGAs is their flexibility or
reconfigurability, which makes them attractive in many real system
implementations.
       Reconfigurable computing involves manipulation of the logic
within an FPGA at run-time. In other words, the design of the hardware
may change in response to the demands placed upon the system while it
is running. Here, the FPGA acts as an execution engine for a variety
of different hardware functions — some executing in parallel, others
in serial — much as a CPU acts as an execution engine for a variety of
software threads.
       Image enhancement is very important as a preprocessing task to
process medical images, especially when the noise has to be removed
for a good quality of treatment.
       Image Segmentation on the other hand, plays a crucial role in
many medical imaging applications by automating or facilitating the
delineation of anatomical structures. In the human brain imaging and
diagnosis for example, Magnetic Resonance Imaging (MRI) can provide
volumetric images of the brain with good soft tissue contrast –
segmentation is then a post-processing operation, which abstracts
quantitative description of anatomically relevant structures. The
objective of segmenting different types of soft-tissue in MRI brain
images is to label complex structures with complicated shapes, as
white matter, grey matter, CSF and other types of tissues in
neurological conditions. This leads to the development of quantitative
algorithms to analyze the neuroanatomical structures. Furthermore, the
correspondence between disease status and degree of shape deformations
in clinical neurology necessitates the use of computational methods to
improve the techniques. Multi-resolution and statistical approaches
are a useful tool for medical image segmentation.
Classification and segmentation have closely related objectives.
Classification can lead to segmentation and
vice-versa. The classification process can identify the different
classes of objects in an image using template or pattern matching.
     In recent years there has been a considerable increase in the
volume of medical image data generated in hospitals.  As most of these
images have to be kept and archived, hospitals must deal with high
storage requirements.  Another important issue is the transmission of
the image data, through both high-bandwidth channels (e.g. LANs) and
low-bandwidth channels (e.g. modem links).  Data compression is
required to alleviate these problems. Medical applications require
high quality and in most cases only lossless compression is accepted. 
Higher compression ratios can be achieved using lossy compressors
(JPEG, Wavelet techniques, etc.) although radiologists are very
reluctant to use them as they might introduce compression artifacts,
which could complicate diagnosis.
      3D compression is a new branch of data compression aimed at the
3D models and other geometric datasets used in computer graphics,
virtual reality, video games, CAD/CAM, and many scientific,
engineering, and medical applications.
      Almost everyone on the Internet has used data compression to get
interesting data faster: ZIP for text and software, MP3 for music,
JPEG and GIF for images, and MPEG4, Quicktime, and DVD for movies. In
some cases, new compression formats have even created new forms of
entertainment and new business models -- like mp3.com, napster,
Internet-based radio stations, and Internet short films.
      The field of 3D compression is attempting to achieve similar
gains for 3D models, animation, and other much more complex types of
data. Currently, its main use is to allow existing applications like
e-commerce, collaborative CAD/CAM, video games, and medical
visualization to use larger and more complex models over the Internet
than they can use without compression. Existing 3D compression
algorithms use both techniques adapted from the 1D and 2D cases (like
wavelets, entropy coding, and predictive coding), and completely
different approaches that take advantage of the properties of 3D
surfaces (like Edgebreaker, Subdivision Surfaces, and triangle
strips).
       Several 3D compression tools are already commercially
available, including Sun's Java 3D compression standard, IBM's
MPEG4/Topological Surgery method, Virtue, Ltd.'s software, and some
methods included in Intel's 3D software and Microsoft's DirectX.
However, 3D compression remains an active area of research, in part
because many 3D models are still too large to be used efficiently with
currently available methods, and because no one knows how much further
3D compression may be improved.

2. An Overview of Research
      The main objective of project 1 is to use FPGAs as a low cost
accelerator for medical imaging applications. Wavelet based approaches
will be used for the enhancement and compression processes while a
statistical approach will be explored for segmentation and
classification algorithms. The project aims to develop a core
generator based system for medical image processing. The
implementation targets the RC1000-PP Celoxica board using Handel-C for
a rapid prototyping. The RC1000-PP co-processor board used is a
standard PCI bus card equipped with a large Xilinx FPGA chip (Virtex-E
2000).
Handel-C is a high level language that is at the heart of a hardware
compilation system known as Celoxica DK1 which is designed to compile
programs written in a C-like high level language into synchronous
hardware. The output from Handel-C is a file that is used to create
the configuration data for the FPGA.
      The main objective of project 2 is to develop a heterogenous
system towards a general framework for image processing algorithms
implementation. The system will combine a number of environments
including  DK1, MATLAB, Xilinx foundation, CoreGen (from Xilinx) and
the product from project 1 in order to maximize the efficiency of our
implementations on FPGAs in terms of speed, area, throughput,
latency…etc.
      The research programme in project 3 aims to develop a system
based Wavelets transforms for 3D image compression with emphasis on
multiresolution curves and surfaces.
www.celoxica.com
www.xilinx.com

Data Hiding for Multimedia Security 

(2 projects)

Supervisors:
Dr A Bouridane (Room 2.15) 
Dr A. Amira (Room G23)


The advent of digital information revolution together with the growing
reliance of Internet (including wireless communication technology) for
commercial exchange of multimedia information has brought about
profound changes in our society and our lives. This has brought about
new challenges and new opportunities for innovation. Currently,
consumers can access, manipulate and enjoy high quality multimedia
data worldwide, thanks to the availability of powerful software, new
multimedia devices such as digital camera, high quality scanners and
printers, digital voice recorder, MP3 players and PDAs. However, the
security and fair use of the multimedia data, as well as the fast
delivery of multimedia content to a variety of end users/devices with
guaranteed Quality of Service (QoS) are important yet challenging
topics. The solutions to these problems will not only contribute to
our understanding of this fast moving complex technology, but also
offer new economic opportunities to be explored.

Currently, the ease of editing and perfect reproduction in digital
domain is becoming a major concern for the protection of ownership and
the prevention of unauthorized tampering of multimedia data. In recent
years, digital watermarking and data hiding techniques, which are
based on embedding secondary data in digital multimedia data, have
made a considerable progress and have attracted an increasing
attention from both academia and industry. The embedded data, usually
called watermark(s), can be used for various purposes, each of which
is associated with different robustness, security, and embedding
capacity requirements. The principal advantage of data hiding versus
other solutions (such as cryptography) is its ability to associate
secondary data with the primary media in a seamless way. The seamless
association is desirable in many applications. For example, compared
with cryptographic encryptions, the embedded watermarks can travel
with the host media and assume their protection functions even after
decryption.

In recent years, a number of techniques have been proposed for a
variety of applications, including ownership protection,
authentication and access control. However, the key features required
by these techniques such imperceptibility, robustness against moderate
processing such as compression, and the ability to hide many bits are
the basic but rather conflicting requirements for many data hiding
applications. In addition, a few other important problems encountered
in practice, such as the uneven embedding capacity for image/video and
the perceptual models for binary, greyscale and colour images, have
received little attention in literature.

These 2 projects are intended to contribute toward the understanding
of the above-mentioned problems. It is intended that prototype systems
will be developed and evaluated using real multimedia data (only
images and video data will be considered in this work).
Project W-1: Watermarking Embedding Capacity: towards a variable
embedding rate

Generally, data hiding is a tool that is used to convey side
information while retaining the original appearance. This property is
useful in some multimedia communication scenarios to achieve
additional functionalities or better performance. From a theoretical
point of view, data hiding can be considered as a communication
problem where the watermark is the signal to be transmitted.
Consequently, communication theories and techniques are very useful in
studying data hiding. A fundamental problem along this direction is
the total embedding capacity. Generally, the number of bits, which can
be embedded, depends on the robustness required. This is not hard to
understand from the aspects of information theory, where the capacity
is tied with a specific channel model and is a function of the channel
parameters.
In addition to the total embedding capacity, there is another
fundamental problem associated with data hiding. In the case of image
and video data and due to the non-stationary nature of perceptual
sources, the amount of data that can be embedded varies significantly
from region to region (or object to object). This uneven embedding
capacity adds great difficulty to high-rate embedding (this problem
does not receive much attention in literature because a highly
sub-optimal approach is generally used in practice by embedding a
predetermined small number of bits to each region). Although the low
constant rate embedding seems work well in experiments involving only
a few test sources, where the embedding rate can be tuned toward this
small test set, it hardly works in practical systems that need to
accommodate much more diverse sources with diverse constraints.
Therefore, the simple constant rate embedding not only wastes much
embedding capacity in regions/objects that are capable of hiding many
bits, but also create dilemma in regions/objects that can hardly embed
any bits without in-introducing noticeable artifacts. Therefore,
solutions to this problem would substantially improve the performance
of many practical systems.

It is the aim of this project to investigate new techniques that
address this problem. We intend to investigate the use of information
theory principles by modeling the media data as regions/objects. Each
region/object will be considered separately. We will use JPEG2000
(which is in fact based on region/tile based compression). We will
also concentrate of investigating the use of multiwavelets for model
the image data.

It is well known that for better performances in image processing, a
good design of wavelet transforms requires that the filters must
combine a number of desirable properties, such as orthogonality and
symmetry. However, the currently available scalar wavelets do not
simultaneously possess all of these properties. To overcome such
limitations, we propose the use of multiwavelets for image
watermarking since they offer simultaneous orthogonality, symmetry,
and short support. Multiwavelets are very similar to scalar wavelets
but have some important differences. In contrast to scalar wavelets,
which are described in the context of multiresolution analysis with a
unique scaling function and a wavelet function, multiwavelets may have
two or more scaling (and wavelets) functions.





Project W-2: Shift Invariant Watermarking: A Complex Wavelet
Multiresolution Approach

Typically, most existing watermarking algorithms transform the host
image into a critically sampled domain, add a suitably scaled
pseudorandom sequence to the transformed image coefficients and
inverse transform the modified coefficients back to obtain the
watermarked image. As previously stated out (Project 1) the amount of
data that can be embedded varies significantly from region to region.
The Discrete Wavelet Transform (DWT) and the Discrete Cosine Transform
(DCT) are among the most popular transform domains. In general, the
DWT produces watermark images with the best visual quality due to the
absence of blocking artifacts. However, it has two drawbacks. The DWT
lacks shift invariance, which means small shifts in input signal can
cause big changes in the energy distribution of the wavelet
coefficients thus affecting the capacity of watermark embedding
process. Secondly, the DWT has poor directional selectivity for
diagonal features, which leads to a blurring of the impulse responses
of the filters of individual subbands thus affecting negatively the
watermark embedding robustness (this is because there is only one
filter for diagonal features).

There exist a number of methods to provide shift invariance one may
use the undecimated (redundant using the "a trous" algorithm for
example) wavelet transform. However, this is computationally intensive
and still has poor selectivity for diagonal features. The Complex
Wavelet Transform (CWT), on the other hand, is more computationally
efficient and has only a modest amount of redundancy; yet it provides
approximate shift invariance and good directional selectivity.

Taking into account the desirable features provided by multiwavelets
(as stated in Project 1), we will investigate the use of Complex
MultiWavelet Transforms (CMWT) for robust watermark embedding. We will
also consider JPEG2000 standard and consider the Wavelets used in the
standard for both lossless and lossy compression. Initially we will
consider both Multiwavelet decomposition of multiplicity order 2 (r
=2) with emphasis on developing balanced wavelet decomposition in
order to allow efficient implementations. We will then generalize the
concepts for decompositions for multiplicity orders r = 3 and possibly
r=4 and we will investigate the effectiveness of watermark embedding,
simplicity of implementation and the preprocessing required.

Article: 53061
Subject: Re: Virtex II - Driving more than one global clock net from one incoming clock pin
From: chris.rosewarne@calyptech.com (Chris Rosewarne)
Date: 2 Mar 2003 15:35:01 -0800
Links: << >>  << T >>  << A >>
Sam,

The way to do it is to drive the DCM #2 with the output from DCM #1. 
DCM #1 is driven by the IBUFG in this case.

regards,
Chris

"Sam Duncan" <damn_spam2001@yahoo.co.uk> wrote in message news:<b3nmd8$1osp5j$1@ID-167554.news.dfncis.de>...
> Hi
> 
> I'm using an XC2V1000 and trying to drive two global clock nets at different
> speeds (using DCMs), using only one clock input pin.  I get errors from
> ngdbuild if I try to drive two IBUFG's from the same pad.  If I drive one
> IBUFG and split the output to two DCM's, the levels of logic reported on my
> clock net (post place and route) increase from 2 to 19.  Is it possible to
> drive two DCM's and two clock nets from one input pin, or should there be a
> separate input for every DCM/clock net?
> 
> Many thanks
> 
> Sam
> 
> --

Article: 53062
Subject: Re: guided par question
From: chris.rosewarne@calyptech.com (Chris Rosewarne)
Date: 2 Mar 2003 15:46:38 -0800
Links: << >>  << T >>  << A >>
Ed,

This would be a timing issue as the guided P&R is reusing the old
placement and routing information where it can, which sets the timing
characteristics of the design.  Try running an unconstrained path
report (trce -u) to check that the timing constraints are cover all
relevant paths.

regards,
Chris

agunos@cox.net (ed) wrote in message news:<c23bf65e.0302280902.4bdcdf3a@posting.google.com>...
> I have a design in a virtex2 which connects to a PCI interface chip
> (plx9080). With all other things begin equal (same edf file, same ucf
> file, same effort level or higher), the latest revision to my design
> only works (talks to the PCI bus) if I perform a guided place and
> route with a guide file from the previous working implementaion. I've
> ran the design without the par guide file AND with higher timing
> constraints succesfully and it still does not work. Without probing
> the bus signals, can I infer anything from this? Basically, can I
> reasonably say that this is not a timing issue? And if not, what else
> would a guided par affect?
> 
> Thanks,
> Ed

Article: 53063
Subject: Re: FIR Filter from Xilinx
From: "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg>
Date: Mon, 3 Mar 2003 10:16:43 +0800
Links: << >>  << T >>  << A >>
Additional info :

My input and the filter coefficients have the following bit assignments
:
MSB
1 bit : signed bit
2 bit : integer
9 bit : decimal
LSB

Once the output becomes 24 bits, How do I arrange the bit assignment in
the output of my filter?

-----Original Message-----
From: Basuki Endah Priyanto
Posted At: Sunday, March 02, 2003 6:26 AM
Posted To: fpga
Conversation: FIR Filter from Xilinx
Subject: FIR Filter from Xilinx


Hi,

I'm newbie in implementation filter in FPGA. I've just create a
distributed arithmetic FIR filter from Xilinx Coregen. The input signal
is 12 bit and the filter coef bit resolution is 12 bit. Thus, it makes
the output signal resolution is about 24 bit. My The bit resolution of
my DAC is 12 bit. How to reduce from 24 to 12 bit ?

pls, gimme advice as i'm newbie in this area.

Thanks.

Basuki



Article: 53064
Subject: Re: PCB board design software vs outsourcing?
From: hmurray@suespammers.org (Hal Murray)
Date: Mon, 03 Mar 2003 05:13:37 -0000
Links: << >>  << T >>  << A >>
If you had asked me a couple of years ago, I would have assumed
the right answer was to do it inhouse.  The current trend seems
to be to outsource things, but that's just my view.

Aside from asking here, I'd suggest asking around at work.
I think things like this are much easier to learn if you have
somebody nearby who is willing to answer questions and/or
give you some hints and checking.

My batting average for outsourcing is mixed.  We had two
big boards outsourced (both design and layout) and I wasn't
happy with the layout.  I think that reflects more on the
overall project rather than the idea of outsourcing the layout.
(The guy who did the layout wasn't that sharp and the guys
who should have been checking/helping him didn't do a good
job.  And somebody wanted it yesterday...)


I've outsourced the layout of two boards localy with good
results.  One was via phone and the other was face to face.
They probably did as good a job as I could have done.
I'd happily do it again.

Here is my checklist for outsourcing a PCB:

  Make a packet of the mechanical pages from the data sheets.
    Scribble on the top the name you used in the libraries.
    Be prepared to make a pass through your libaries tweaking
    the names you used for the footprints.  They might
    want "R0603" where you used "0603".

  Make a mechanical drawing/sketch of the board outline and
    mounting holes.
  Add to that a rough placement of the big parts, especially
    connectors.  (Maybe their location is firm rather than rough.)
  Make a list of the layers (stackup) and sketch of the plane cuts.
    It's OK if the above are rough.  Tell them what is firm.
    Should they add layers or make the board bigger to get
    the job done sooner and cleaner?

  Make a list of all the routing constraints by signal name:
    differential pairs
    controlled impedance
    fat traces (for power)
    ...

  Take a set of schematics and expect to sit with the layout
    guy while he does the initial placement.  (He will dump
    all the parts next to the board and then move them onto
    the board.)  This is obviously easier if he is located
    near enough so you can go there.
  Show him where the differential pairs go.

  In a day or so, you will get back a trial layout.
  If that's OK, you soon get a routed board.
    I think all the board design packages include a free
    viewer.  You get to stare at it for a while and make
    change requests/suggestions.
  Expect to iterate a few times making minor tweaks.
    A face to face session may be appropriate.


-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 53065
Subject: Re: How to select the chip before using FPGA?
From: wangmanxi@yahoo.com (siriuswmx)
Date: 2 Mar 2003 23:11:18 -0800
Links: << >>  << T >>  << A >>
Thank you,rene :)
as you say, i ask my colleagues for help, but i still have some
puzzles:
1. What are the differences between the chips of altera and xilinix ?
at the aspects of  power dissipation, speed and price.
2. i feel that QUARTUSII is easier to use than ISE, but i also found
that many engineers preferred ISE, why?
>   A 16bit counter takes 16 flipflops, when autoloading it
>   takes 32 flipflops
3. what is meaning of autoloading here? does it mean useing language
like VHDL or verilog? and  that is to say, symbol input is better than
Language input?


Best reguards,

siriuswmx  

Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<c7380f4bfc3d8b852d279a37c4edffb5@news.teranews.com>...
> siriuswmx wrote:
> > Hi, 
> >   I am first time to use FPGA,  i want to realize demodulation in
> > FPGA, but  you know, there are so mang chips with all kinds capacity
> > and speed from several companies.
> >  Someone told me that i must calculate sum of the total arrays i shall
> > use before selecting the best chip.  Could you tell me How to
> > calculate it?
> 
> 
> You first have to select a manufacturer.
> Choose the one where you have better support, eg a
> colleague familiar with the technolgy with sufficient
> time to introduce you.
> Then download their free tool. It might take you 2 weeks
> to become familiar. In case you don't have a manufacturer
> preference try another one too.
> 
> The FPGA is selected as follows :
> 
> -Estimate the number of Flipflops.
>   A 16bit counter takes 16 flipflops, when autoloading it
>   takes 32 flipflops
> -Compare the number of logic inputs to the matrix.
>   A macrocell has a certain number of inputs, and when they
>   are exceeded another macrocell is taken, its flipflop
>   unused.
> -Any development uncertainities, unknown functions ?
> 
> -Do a simulation first
>   Those packages I know let you design without specifying
>   the chip. At compile time, the chip is suggested.
> 
> -Take the next bigger for the prototype, as the
>   compiletime increases when space becomes thight and/or
>   a lot of optimizing options are required
> 
> 
> Depending on the number of chips used it might make sense
> to settle for just a few types, to keep storage cost low.
> 
> Rene

Article: 53066
Subject: FPGA demo board schematic
From: rathanon99@yahoo.com (ron)
Date: 2 Mar 2003 23:11:21 -0800
Links: << >>  << T >>  << A >>
I am looking for demo board schematic for small gate count (cheaper)
CPLDs and Spartan FPGAs. I was able to see some at www.opencores.org
but the FPGAs were quite expensive. Do you know where I can get this?
I'm planning to make my own board since I cannot afford to buy demo
board. THank you

Article: 53067
Subject: Re: FPGA demo board schematic
From: hmurray@suespammers.org (Hal Murray)
Date: Mon, 03 Mar 2003 07:43:02 -0000
Links: << >>  << T >>  << A >>
>I am looking for demo board schematic for small gate count (cheaper)
>CPLDs and Spartan FPGAs. I was able to see some at www.opencores.org
>but the FPGAs were quite expensive. Do you know where I can get this?
>I'm planning to make my own board since I cannot afford to buy demo
>board. THank you

If you are going to make your own board, you might just as well
make it do what you want.  What do you want it to do?  LEDs?
Switches?  BNC connectors?

If you found schematics on opencores, look at them for hints.

Things to look for:
  The clock(s) generally go in on special pins.
  FPGAs need some way to load the bit pattern:  Either JTAG
    or one of the non JTAG ways: master serial, slave serial...
    (You will have to understand that anyway, so might as well
    do it when you are working on the schematics.)

If you are building your own board, you should probably check
the recent (2 weeks?) discussions on bypassing.  It's tricky
to do in two layers since you probably have (at least) 2
voltages as well as ground.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 53068
Subject: Startup latency...
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Mon, 3 Mar 2003 10:00:30 +0200
Links: << >>  << T >>  << A >>
I posted a question (Ref: SDA FIR Filter) regarding the refusal of my SDA
FIR filter to work in hardware, although it works perfectly in simulation. I
noticed that in the CORE generator GUI, the latency (startup latency I
presume) was 9 clock cycles. I am feeding the filter 4 bit input samples
every 8 clock cycles, so should get an output every 4 clock cycles. However,
my complaint was that I am only getting a DC output in hardware, and am now
wondering whether the fact that I am giving samples every 8 clock cycles
from startup might have an effect on the filter, since the latency is 9
clock cycles... to me this is not possible, but I am getting desperate!!!

adrian



Article: 53069
Subject: Re: FPGA demo board schematic
From: "Jan Pech" <j.pech@NOSPAMieee.org>
Date: Mon, 3 Mar 2003 10:10:53 +0100
Links: << >>  << T >>  << A >>
One more low cost open-source design: http://fpga.f2g.net/
You can find .GWK file of this board for use with PCB pool at
http://fpga.wavesynth.com/
Jan

"ron" <rathanon99@yahoo.com> wrote in message
news:c661162.0303022311.3d87a075@posting.google.com...
> I am looking for demo board schematic for small gate count (cheaper)
> CPLDs and Spartan FPGAs. I was able to see some at www.opencores.org
> but the FPGAs were quite expensive. Do you know where I can get this?
> I'm planning to make my own board since I cannot afford to buy demo
> board. THank you



Article: 53070
Subject: Re: Spartan II PCB, bypass Capacitors
From: "Stamatis Sotiropoulos" <ssothro@hotmail.com>
Date: Mon, 3 Mar 2003 11:32:25 +0200
Links: << >>  << T >>  << A >>

Regarding bypass Capacitors, is it important to use SMD Capacitors
(like Y5V)?  I intended to use classic MKT-370 capacitors...



Article: 53071
Subject: Re: How to select the chip before using FPGA?
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Mon, 03 Mar 2003 10:20:48 GMT
Links: << >>  << T >>  << A >>
siriuswmx wrote:
> Thank you,rene :)
> as you say, i ask my colleagues for help, but i still have some
> puzzles:
> 1. What are the differences between the chips of altera and xilinix ?
> at the aspects of  power dissipation, speed and price.

I assume all manufacturer try to deliver good stuff.
Don't ask me about specifics. I happend the come across this technology
many years ago, when a colleague showed me a MAX7016 or a 7032, with
16 or 32 flipflops. The software is not simple and since I lack time to
explore the software of competitiors, I stick with Altera. Pure chance.
Could have been any else.


> 2. i feel that QUARTUSII is easier to use than ISE, but i also found
> that many engineers preferred ISE, why?

No idea. I don't even know ISE.

> 
>>  A 16bit counter takes 16 flipflops, when autoloading it
>>  takes 32 flipflops
> 
> 3. what is meaning of autoloading here? does it mean useing language
> like VHDL or verilog? and  that is to say, symbol input is better than
> Language input?

In order to make a sub-clock, eg 1kHz, you usually reload the counter
with a constant(or variable) from the carry. And that constant or variable
takes another set of flipflops.
I do Schematic editing of the content, I never came across any HDL,
and never saw any advantage (beside lacking the time) in using them.
I guess becoming familiar with VHDL is another 4 weeks.

Rene

> 
> 
> Best reguards,
> 
> siriuswmx  
> 
> Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<c7380f4bfc3d8b852d279a37c4edffb5@news.teranews.com>...
> 
>>siriuswmx wrote:
>>
>>>Hi, 
>>>  I am first time to use FPGA,  i want to realize demodulation in
>>>FPGA, but  you know, there are so mang chips with all kinds capacity
>>>and speed from several companies.
>>> Someone told me that i must calculate sum of the total arrays i shall
>>>use before selecting the best chip.  Could you tell me How to
>>>calculate it?
>>
>>
>>You first have to select a manufacturer.
>>Choose the one where you have better support, eg a
>>colleague familiar with the technolgy with sufficient
>>time to introduce you.
>>Then download their free tool. It might take you 2 weeks
>>to become familiar. In case you don't have a manufacturer
>>preference try another one too.
>>
>>The FPGA is selected as follows :
>>
>>-Estimate the number of Flipflops.
>>  A 16bit counter takes 16 flipflops, when autoloading it
>>  takes 32 flipflops
>>-Compare the number of logic inputs to the matrix.
>>  A macrocell has a certain number of inputs, and when they
>>  are exceeded another macrocell is taken, its flipflop
>>  unused.
>>-Any development uncertainities, unknown functions ?
>>
>>-Do a simulation first
>>  Those packages I know let you design without specifying
>>  the chip. At compile time, the chip is suggested.
>>
>>-Take the next bigger for the prototype, as the
>>  compiletime increases when space becomes thight and/or
>>  a lot of optimizing options are required
>>
>>
>>Depending on the number of chips used it might make sense
>>to settle for just a few types, to keep storage cost low.


Article: 53072
Subject: PCI specification doubt
From: praveenkumar1979@rediffmail.com (praveen)
Date: 3 Mar 2003 03:10:07 -0800
Links: << >>  << T >>  << A >>
Hello Sir/Friends.

 I am designing a PCI target. I am presently reading specification and
 i didnot understand certain things which i have listed it.


1. I didnot understand why cacheline register required. I have read
that its length is same as processor cacheline length. what is the
exact function of this cacheline register. If you can give me an
example it will be wonderful.


2. How can understand how can PCI have multiple function? please can
you give me multiple function PCI?


3.what is use cardbus line register in configuration header?Is this
used only for PCMCIA cards? i have read that this is used for hot plug
devices where the initialisation code is on expansion ROM is this
true?Please give me more information about it?


4. why is cache wrap mode of addressing required ?where is mode used?


5. In PCI cache support protocol how is the next address information
given to cache controller because cache latches only the starting
address and snoops it. Thereafter its the function of target PCI to
give the next address addressed (in burst mode as target PCI latches
the starting address and thenafter it increments it withinself). How
this incremented address given to cachecontroller?


6.what is the value to be written for header type zero(ie bit[6:0]),
header type one , and header type two in the header type register in
configuration register ?I mean what value to be written in bit[6:0]
for header type zero/one/two?



7. Where is built in self test code located whether in expansion ROM
or where?how can you conduct a built in self test whether by doing a
configuration write on the BIST register or how?


8. what is the use Cardbus CIS pointer in configuration register? It
is said it is implemented by devices that share silicon between
cardbus and PCI.I didnot understand what that share silicon means? can
please give me more information about it?



9. What is use of max_lat register in configuration register?what i
have read is that value written in MIN_gnt register is read by BIOS
and load the latency timer with value in terms of PCI clock to it?
what is the use Max_lat register?Is it the priority?If so what is the
weightage of the bit?



10. what is this user defined features(UDF)?Can you please give me
example for this?



waiting for Your reply   
thank in advance
praveen

Article: 53073
Subject: Re: Spartan II PCB, bypass Capacitors
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Mon, 3 Mar 2003 11:26:05 +0000 (UTC)
Links: << >>  << T >>  << A >>
Stamatis Sotiropoulos <ssothro@hotmail.com> wrote:
: Regarding bypass Capacitors, is it important to use SMD Capacitors (like
: Y5V)?  I intended to use classic MKT-370 capacitors...  
:   

Longer leads result in higher inductance results in higher noise.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 53074
Subject: Re: FPGA demo board schematic
From: "geeko" <jibin@ushustech.com>
Date: Mon, 3 Mar 2003 17:01:33 +0530
Links: << >>  << T >>  << A >>
Another good influx board can be found @
http://kamsky.eecs.berkeley.edu/calinx/pdf/Manual.pdf

regards
geeko


"ron" <rathanon99@yahoo.com> wrote in message
news:c661162.0303022311.3d87a075@posting.google.com...
> I am looking for demo board schematic for small gate count (cheaper)
> CPLDs and Spartan FPGAs. I was able to see some at www.opencores.org
> but the FPGAs were quite expensive. Do you know where I can get this?
> I'm planning to make my own board since I cannot afford to buy demo
> board. THank you





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