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Messages from 53125

Article: 53125
Subject: EP310
From: Steven John Buckley <buckley@zetnet.co.uk>
Date: Tue, 4 Mar 2003 13:56:30 GMT
Links: << >>  << T >>  << A >>
Not sure if this is the right place but here goes!
I have the task of replacing a bunch of ALTERA
EP310 PLDs for a new design but only have the
JED files for them. I need the equation for them.
I have scanned the NET but can only find
JED2EQN.EXE which does not have the EP310 in the library.
I don't care about the format of the equations EQN,CUPL etc.
Does anyone know of a simple utility around that will take
the EP310 JED files and output something that tells me what
the damn things do.
Any help will be gratefullt received.

       Regards
                    Steve


Article: 53126
Subject: Re: VHDL & FPGA Design tools
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Tue, 4 Mar 2003 09:08:29 -0500
Links: << >>  << T >>  << A >>
Goran,
    How about using the web-pack.  It is free and does support the
Spartan2E.  Alternatively, ISE is only about $700 if I recall correctly.
Theron


"Goran" <goran@net.yu> wrote in message
news:3c0f6336.0303040501.3ebd09f8@posting.google.com...
> Thanks, Ray.
>  But how can I update libraries? I contacted people in Aldec support,
> and they didn't give me any clear answer. They just told me it would
> be if I buy new edition ( $4K for Xilinx edition).
>  My idea is to start developing some serious stuff in FPGAs for
> company I work in, but I first have to show "some" results with what
> we already got, before I start pursuading my chief to buy some real
> stuff.
>  Thanks,
>  Goran
>
>
> Ray Andraka <ray@andraka.com> wrote in message
news:<3E640E13.EB3569B6@andraka.com>...
> > XST does a fine job, much better than foundation did.  You will be happy
with it.  You can use your Aldec for both
> > pre-PAR and post route simulations.  Aldec 3.2 is getting a bit long in
the tooth now, the current version is 5.2.  Just
> > make sure your unisim and simprim libraries have been updated and you
should be fine though.  For what it is worth, the
> > later editions of Aldec fixed a few annoying bugs in 3.2, increased the
simulation speed considerably, and added
> > features.  You'd probably find the update to be well worth the money
when you can afford it.
> >
> > Goran wrote:
> >
> > > kevinbraceusenet@hotmail.com (Kevin Brace) wrote in message
news:<cc7b0b5f.0302231456.ce5e3f9@posting.google.com>...
> > >
> > > Kevin,
> > > Thanks for answer.
> > >
> > > > Goran,
> > > >
> > > > Which Xilinx part are you planning to target?
> > >
> > > Spartan IIe, smaler Virtex (mainly because multipliers).Below 300K
> > > gates.
> > >
> > > > As long as you are targeting Xilinx devices below 300K system gates
or
> > > > you don't have to target a 2.5V Virtex device, you may want to try
the
> > > > free ISE WebPACK first before paying for ISE BASE-X.
> > > > Unlike ISE BASE-X users, ISE WebPACK users won't have access to FPGA
> > > > Editor or CORE Generator, but if those tools aren't important to
you,
> > > > you should be fine with ISE WebPACK.
> > >
> > > I would like to use CORE Generator. I think it's a nice thing and ISE
> > > baseX doesn't seem to expencive. I don't like paying every year,
> > > but...
> > >
> > > >         Regarding ModelSim XE, you may want to try ModelSim
XE-Starter
> > > > first before paying for ModelSim XE.
> > > > Yes, ModelSim XE-Starter has a 500 statements limit, but what that
> > > > really means is that the simulation speed will drop after that
limit,
> > > > and the simulator will still continue to run past that limit.
> > > > In the past, I have simulated a design that exceeded the 500
> > > > statements limitation by 40,000 lines, but ModelSim XE-Starter
> > > > completed the simulation fine.
> > > > However, it took quite a time to complete because I was doing a Post
> > > > P&R simulation of a design, and a Post P&R simulation is inherently
> > > > very slow compared to an RTL simulation.
> > >
> > > The problem is we have some older version of Aldecs ActiveVHDL, I
> > > think 3.2. I did lot of behavioral simulations on this one, and I like
> > > it. My question is can I import post place & route design from ISE and
> > > perform simulation in ActiveVHDL 3.2? I'm beginer in this, so really
> > > need help!
> > >
> > > >         I also agree with Spam Hater that XST's synthesis quality is
> > > > good, so unless you don't mind paying $8,000 for a third party
> > > > synthesis tool, I will just use XST.
> > >
> > > Lot of people are saying XST is OK. Since I mind paying that much I'll
> > > go with XST.
> > >
> > > Regards,
> > > Goran
> > >
> > > >
> > > >
> > > > Kevin Brace (If someone wants to respond to what I wrote, I prefer
if
> > > > you will do so within the newsgroup.)
> > > >
> > > >
> > > >
> > > > goran@net.yu (Goran) wrote in message
news:<3c0f6336.0302221215.1ab0ed0d@posting.google.com>...
> > > > > Hi all,
> > > > > I work in small, development company, and we would like to start
some
> > > > > more advanced FPGA designs (we are now using Xilinx FPGAs for
simple
> > > > > glue logic only). My question is what tools we need to complete
medium
> > > > > sized projects on Spartan IIe & smaller Virtex members.
> > > > > I learned (on Xilinx web site) that ISEbaseX would be OK?
> > > > > Does "one year license" that you buy from Xilinx mean your
software
> > > > > stops working after one year, or you just don't have access to
> > > > > updates?
> > > > > If we purchase ModelSim XE does the same license apply?
> > > > > Can we use another VHDL simulator for post place & route
simulation?
> > > > > We have, for example, Active VHDL, can we use it?
> > > > > How does XST behave, do we have to buy other synthezis tool to
compile
> > > > > anything more advanced?
> > > > > Thanks in advance,
> > > > > Goran.
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759



Article: 53127
Subject: Re: Spartan II PCB, bypass Capacitors
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Tue, 04 Mar 2003 09:16:00 -0500
Links: << >>  << T >>  << A >>

Stamatis Sotiropoulos wrote:

> Regarding bypass Capacitors, is it important to use SMD Capacitors
> (like Y5V)?  I intended to use classic MKT-370 capacitors...

As someone else has said, long leads mean high inductance and poor
bypass behavior.  Short leads (or no leads) mean low inductance and best
bypass behavior.  Use the surface mount parts.  They are very easy to
use.  Ideally use a 0605 or smaller size.  Certainly not any bigger than
0805 size.

Theron




Article: 53128
Subject: Re: Avnet Cilicon Xilinx Virtex-E development kit
From: "Michael Nicklas" <michaeln@nospam.slayer.com>
Date: Tue, 4 Mar 2003 14:18:14 -0000
Links: << >>  << T >>  << A >>
This is a fair point, I am partly affiliated with a university here in
Scotland and I have noticed a significant difference in support from
educational and commercial points of view, it was part of the reason that we
(at the company) went with the commercial version of ISE and ModelSIM.

I have had no problem getting in contact with the people at the company and
their technical advice to a potential customer was very good considering it
was only an enquiry.

Robert, I hope you have more luck.

Austin, thanks.

I would still like an opinion from someone who has one if possible though!

Thanks again, and in advance!

Mike

"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3E63E0EA.B099E0B7@xilinx.com...
> Robert,
>
> Why would you call Avnet when the Xilinx University program supports
Berkeley
> directly?
>
> Remember that Avnet is a "for profit" business, and they will concentrate
on
> customers (because that is how we all make money and stay in business).
>
> For University support, there is a whole other organization set up just
for that
> reason (so we can support reseach, and student learning, without impacting
our
> sales partners and our day to day business).
>
> In fact, universities and schools are encouraged to use the newsgroup that
is
> set up just for them....to obtain support on any technical questions.
>
> http://www.xilinx.com/univ/
>
> Austin
>
> Robert Abiad wrote:
>
> > Hi Mike,
> >
> > After many calls, I was never able to actually talk to anyone at the
> > company or get anyone to return my calls.  That's a bad sign as far as
> > I'm concerned, so I'd try someone else.
> >
> > -robert
> >
> > Michael Nicklas wrote:
> >
> > > Hi
> > >
> > > I'm thinking of investing in the Avnet Xilinx Virtex-E development kit
and
> > > wondered if anybody had any previous experience with them and any
opinions
> > > of them as a company, in terms of product quality, tech support etc.
> > >
> > > Much appreciated.
> > >
> > > --
> > > Cheers!
> > >
> > > Mike
> > >
> > >
> > >
>



Article: 53129
Subject: Re: Decoupling Capacitor for CPLD
From: "David Kinsell" <kinsell@poboxyz.com>
Date: Tue, 04 Mar 2003 14:19:16 GMT
Links: << >>  << T >>  << A >>
There's no real standard guidelines.  Conventional, conservative practice
these days is to have gnd and vdd on two adjacent planes, have several bulk
caps of 33-47 uF tantalum somewhere on the board, and have high-frequency
ceramic bypass caps of .1 or .01 (maybe both) as close as possible to pairs of
power pins.  The actual requirements depend on slew rates, how many lines
can switch at the same time, loads on the outputs, clock frequencies, etc.

Xilinx or one of their distributors sponsored a talk claiming that the high-frequency
caps should be of varying capacities, because each package will have its
own resonant frequency where noise is not effectively squashed.  Might
be needed in the most demanding of applications.

Dave Kinsell

kill the yz in address for email reply




"sanjay" <sanjay@cg-coreel.com> wrote in message news:b3fdt2$1klqf9$1@ID-164436.news.dfncis.de...
> Hi group,
> Can anybody tell me which kind of Decoupling Capacitor I should us for
> Xilinx Xc98288XL-10FG256.
> Is there any standard Guideline for selecting the Device Decoupling?
>
> Thanks in Advance
> Sanjay
>
>



Article: 53130
Subject: Re: FIR Filter from Xilinx
From: Ken Chapman <chapman@xilinx.com>
Date: Tue, 04 Mar 2003 14:36:09 +0000
Links: << >>  << T >>  << A >>
Dear Basuki,

The safe answer is just to keep the most significant bits. However, you may well be wasting dynamic range by doing this.

The best is to calculate the output saturation level. This is the maximum level the output can reach based on the actual coefficients you have used, many of which will relatively small numbers. In this way you can often discard one or more of the MSBs which are not really used and maintain higher precision by keeping some LSBs.

Needless to say this is covered on the Xilinx DSP Techniques Course which I authored :-)

Yours sincerely,

Ken Chapman





Article: 53131
Subject: xilinx HDL bencher
From: itris@technologist.com (itris)
Date: 4 Mar 2003 07:01:53 -0800
Links: << >>  << T >>  << A >>
hiya guys,

my first post to this group, please don't tear me apart ;)

I'm using the HDL bencher from xilinx to generate a testbench. I'm
using their free ISE 5.2i software. Works fine.
except..

when I go beyond even a very simple stimuli, the memory usage of the
bencher grows beyond belief, slowing the pc down to a halt.
Setting a signal on and off for a about 20 times runs me up to 90MB
memory used. Anyone else getting this? Any solutions? I've searched
the web but didn't find much..

tnx,


itris

Article: 53132
Subject: Xilinx support...
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 4 Mar 2003 17:18:49 +0200
Links: << >>  << T >>  << A >>
Does Xilinx have support via email (ie. individual support)... my problem
has no solution record on the website, I think it may be a bug but I don't
know...I am running ISE 4.2i, and am having a huge problem with the serial
implementation of the DA FIR Filter v7.0

thanks

adrian



Article: 53133
Subject: Re: Xilinx support...
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 04 Mar 2003 08:08:37 -0800
Links: << >>  << T >>  << A >>
Noddy,

http://www.xilinx.com/support/clearexpress/websupport.htm

Gets you to the logins and emails for techincal support.

Note that the University Program has its own technoical support system (do not
use commercial hotline!).

Austin

Noddy wrote:

> Does Xilinx have support via email (ie. individual support)... my problem
> has no solution record on the website, I think it may be a bug but I don't
> know...I am running ISE 4.2i, and am having a huge problem with the serial
> implementation of the DA FIR Filter v7.0
>
> thanks
>
> adrian


Article: 53134
Subject: Using Xilinx DCM's (DLL) with RESET tied to GND is dangerous!!
From: haklis@hotmail.com (Hakon Lislebo)
Date: 4 Mar 2003 08:21:26 -0800
Links: << >>  << T >>  << A >>
Hi all of you!
I have seen a lot of postings related to DCM's unlocking because of
ground bounce and jitter on the input clock to the DCM. I also had a
problem with that on a prototype. Buffering the input clock solved
that because the problem was crosstalk from other signals.

My concern is this... the DLL need a reset when it loses lock and
there seemes to be several problems that leeds to a DCM loosing lock.
If you have a design that shall run for years without restart, there
is a great chance that the DLL will unlock and corrupt the data
transmission or whatever it does. Personally I intend to make an
auto-reset based on the status signals from the DLL. In most
application notes from Xilinx they tie DCM RESET to GND, should't they
at least make a footnote that warn you about this possible situation?
A design may work in the lab for a few days, but what about the noisy
environment of the customers?

What do you think? Do you have the guts to send out hundreds of PBA's
with DLL RESET tied to GND? What does the Xilinx guys says about this?

Regards
Håkon Lislebø

Article: 53135
Subject: Using Xilinx DCMs out of specifications is not recommended!!!!
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 04 Mar 2003 09:02:52 -0800
Links: << >>  << T >>  << A >>
Hakon,

Well, if the noise is less than what we specify (ie 200 mV peak to peak)
there are no problems (at least from the noise)....

If the input jitter or noise is far worse than what we specify, then you
should take that into account, and either fix the jitter/noise, or make a
design that can reset itself when the DCM unlocks due to excessive input
jitter, and tolerate the occasional resets due to operating out of
specifications.

Quite simply, if you exceed the jitter input specification, do not expect
the DCM to remain locked.

As for hundreds, let us say rather that millions of pcbs have been shipped
that use the DCM, and this is not a problem that we see occurring in the
field except in a very few selected cases; which turn out to be due to
excessive noise or bad signal integrity in the initial design and we get
them solved.  Every time we solve a problem, we post it as an answer, so
that our hotline (and the customer) doesn't have to keep guessing at what
might be wrong.

The fact that there are so many 'answers' for the DCM just means they are
a popular and useful feature, that gets used a lot, and people are always
finding new ways to break them and exceed the specifications.

Austin

Hakon Lislebo wrote:

> Hi all of you!
> I have seen a lot of postings related to DCM's unlocking because of
> ground bounce and jitter on the input clock to the DCM. I also had a
> problem with that on a prototype. Buffering the input clock solved
> that because the problem was crosstalk from other signals.
>
> My concern is this... the DLL need a reset when it loses lock and
> there seemes to be several problems that leeds to a DCM loosing lock.
> If you have a design that shall run for years without restart, there
> is a great chance that the DLL will unlock and corrupt the data
> transmission or whatever it does. Personally I intend to make an
> auto-reset based on the status signals from the DLL. In most
> application notes from Xilinx they tie DCM RESET to GND, should't they
> at least make a footnote that warn you about this possible situation?
> A design may work in the lab for a few days, but what about the noisy
> environment of the customers?
>
> What do you think? Do you have the guts to send out hundreds of PBA's
> with DLL RESET tied to GND? What does the Xilinx guys says about this?
>
> Regards
> Håkon Lislebø


Article: 53136
(removed)


Article: 53137
Subject: Re: conditional `include
From: Keith <keith@NOSPAMmyricanetworks.com>
Date: Tue, 04 Mar 2003 09:08:50 -0800
Links: << >>  << T >>  << A >>
On Mon, 03 Mar 2003 20:25:47 -0800, Kevin Neilson wrote:

> Here's a question I was asked by a friend and realized I have no answer
> for. He wants to use `include, to include a text file of comments that
> initializes a blockRAM, but he wants to do it conditionally based on the
> hierarchy of the module.  That is, he wants to reuse the same module in
> many places, but wants to `include a different text file in each one.
> 
> Here's an example of what he would like to do (although this isn't
> possible):
> 
> //  Instantiate RAM 0
> defparam ram0.TEXT_FILE = "file0";
> ram_module ram0 (..);
> //  Instantiate RAM 1
> defparam ram1.TEXT_FILE = "file1";
> ram_module ram1 (..);
> 
> //This is the code for the RAM module module ram_module (..); parameter
> TEXT_FILE = "something_that_will_be_passed_from_above"; `include
> "TEXT_FILE"
> endmodule
> 
> 
> 
> Is there a way to do something like this?
> 
> -Kevin

Kevin:

I remember trying very hard in the past to get the `include
directive to accept something other than a literal file name.  I was
unsuccessful.  It is a pretty inflexible mechanism.  About the only thing
you can do is bracket it with `ifdef's.

What is your friend's motivation here, and which Verilog
simulator/synthesizer is he using?  Perhaps there is an alternate way of
doing what he wants.

--Keith

Article: 53138
Subject: Re: Newbie: Help
From: "John_H" <johnhandwork@mail.com>
Date: Tue, 04 Mar 2003 17:55:33 GMT
Links: << >>  << T >>  << A >>
ISE is the tool that takes your Verilog design and produces your chip.  The
test bench is used for simulation where you provide stimulus - usually in a
non-synthesizeable form - and compare the outputs from the design you're
testing to the expected values.  It's the design you'r testing that needs to
be run through ISE, not the test bench.


"nntp.lucent.com" <wang_huaibo@hotmail.com> wrote in message
news:b427fb$eps@netnews.proxy.lucent.com...
> Hi, everyone,
>
> I finished the verilog code.
> I simulated it by Modelsim.
>
> Now I want to run it on ISE 5.0
>
> ISE complains that my test bench
> module has no port list.
>
> What shall I do now? Shall I prepare
> my test bench driver in another way?
>
> THANKS
>
> Bucther
>
>



Article: 53139
Subject: Re: Mac Os X for FPGA design
From: "Kevin Neilson" <kevin_neilson@removethistextattbi.com>
Date: Tue, 04 Mar 2003 18:10:39 GMT
Links: << >>  << T >>  << A >>
That would be great but I don't see it happening.

"Tomas" <tmlo@networks.nera.no> wrote in message
news:87f5aba4.0303040322.570bb649@posting.google.com...
> Hi all,
>
> I am considering the future hardware platforms for our designs. As our
> groups have a wide experience with unix environments (we have been
> using Solaris for a while, now), we would like to continue in this
> world.
>
> Basically all the EDA tools we need run for either Solaris, HP and
> some of them now, Linux. I am not going to list all the pro's and
> con's of these platforms, we have already heard enough about it.
>
> What I am mostly curious about is the feasibility of Mac based FPGA
> design. Mac Os X is a nice and SUPPORTED Unix OS, and the Xservers
> from Apple are not too expensive compared to equivalent Intel boxes...
> And with the rumored advent of the 970 chips from IBM they might
> become even more interesting.
>
> Of course none of EDA tools we use (Modelsim, Leonardo, Synplify,
> Xilinx Alliance...) have native versions for Mac OS X.
>
> What do you all think about this? Should we press the EDA vendors to
> come up with yet-another-supported-platform?
>
> Regards,
> Tomas



Article: 53140
Subject: Re: Implementation of latch in FPGA
From: Mike Treseler <tres@fluke.com>
Date: Tue, 04 Mar 2003 10:30:57 -0800
Links: << >>  << T >>  << A >>
Jeniffer wrote:
> Hi all,
> I am trying to implement a design in virtex device. My design contains
> quite a few latches (intended). When I implement the design and open 
> the design in the FPGA editor, I see that the latches are implemented 
> using LUTs and not using the registers in the slice. The device contains 
> free resources of registers. Is there a way, I can force the latches to 
> be implemented in registers

To infer a register, you need a synchronous process.

process(rst, clk)
begin
. . .



           -- Mike Treseler


Article: 53141
Subject: Re: xilinx HDL bencher
From: Mike Treseler <tres@fluke.com>
Date: Tue, 04 Mar 2003 10:37:40 -0800
Links: << >>  << T >>  << A >>


itris wrote:

> 
> I'm using the HDL bencher from xilinx to generate a testbench. I'm
> using their free ISE 5.2i software. Works fine.
> except..
> 
> when I go beyond even a very simple stimuli, the memory usage of the
> bencher grows beyond belief, slowing the pc down to a halt.
> Setting a signal on and off for a about 20 times runs me up to 90MB
> memory used. Anyone else getting this? Any solutions? I've searched
> the web but didn't find much..

Consider writing your own testbench in a text editor.
See:
http://www.stefanvhdl.com/

     -- Mike Treseler


Article: 53142
Subject: Re: Avnet Cilicon Xilinx Virtex-E development kit
From: Robert Abiad <abiad@ssl.berkeley.deletethisandaddedu>
Date: Tue, 04 Mar 2003 11:23:07 -0800
Links: << >>  << T >>  << A >>
Austin,

Austin Lesea wrote:

> Robert,
> 
> Why would you call Avnet when the Xilinx University program supports Berkeley
> directly?


Would you believe because I like to pay full price?
Actually, I figured that the XUP was for instruction only.  Then again, 
when I did call Xilinx directly, they sent me off to an outside rep who 
told me that Xilinx doesn't make boards themselves and that I should 
call one of their partners.  Nobody suggested the XUP.

 
> Remember that Avnet is a "for profit" business, and they will concentrate on
> customers (because that is how we all make money and stay in business).
> 
> For University support, there is a whole other organization set up just for that
> reason (so we can support reseach, and student learning, without impacting our
> sales partners and our day to day business).
> 


When I call a company about their products, I am a customer.  We pay 
with real money and if we want to purchase a commercial product instead 
of an educational one, the vendor shouldn't override us.  If Insight 
responds to our questions and sells us their products when Avent won't, 
that means they provide better service.  I wouldn't buy from a company 
that ignores me because I'm not a big enough customer unless I had to.

I'm glad to hear Mike had better luck.

 > In fact, universities and schools are encouraged to use the newsgroup 
   that is
 > set up just for them....to obtain support on any technical questions.
 >
 > http://www.xilinx.com/univ/
 >
 > Austin


Thanks for the reference.  I'll keep it in mind for the future.


-robert



Article: 53143
Subject: Re: Mac Os X for FPGA design
From: johnjakson@yahoo.com (john jakson)
Date: 4 Mar 2003 11:34:40 -0800
Links: << >>  << T >>  << A >>
tmlo@networks.nera.no (Tomas) wrote in message news:<87f5aba4.0303040322.570bb649@posting.google.com>...
> Hi all,
> 
> I am considering the future hardware platforms for our designs. As our
> groups have a wide experience with unix environments (we have been
> using Solaris for a while, now), we would like to continue in this
> world.
> 
> Basically all the EDA tools we need run for either Solaris, HP and
> some of them now, Linux. I am not going to list all the pro's and
> con's of these platforms, we have already heard enough about it.
> 
> What I am mostly curious about is the feasibility of Mac based FPGA
> design. Mac Os X is a nice and SUPPORTED Unix OS, and the Xservers
> from Apple are not too expensive compared to equivalent Intel boxes...
> And with the rumored advent of the 970 chips from IBM they might
> become even more interesting.
> 
> Of course none of EDA tools we use (Modelsim, Leonardo, Synplify,
> Xilinx Alliance...) have native versions for Mac OS X.
> 
> What do you all think about this? Should we press the EDA vendors to
> come up with yet-another-supported-platform?
> 
> Regards,
> Tomas


OSX is a great platform but it won't help, way too expensive, way too
little cpu.

I would say to drop support for Windows and leave it all to Linux, at
least the APIs are more friendly to complex EDA SW dev, and not
endlessly being changed as MS is prone to do.

And Intel/Linux boxes are the cheapest/fastest way to go. Linux is
ready for 64bit cpus IIRC. Anyway the high end FPGA tool chain is more
& more becoming the same as the ASIC flow which has long been almost
totally nix.

Using Windows for ASIC then FPGA design has been a big waste of time
for me, Windows doesn't even have a useable cmd line interface unless
you add in this & that. I wanted all Windows & GUIed apps at one time,
but I changed my mind after using it.

nuff said

Article: 53144
Subject: Re: Mac Os X for FPGA design
From: iluvfpgas@yahoo.ca (Alfredo)
Date: 4 Mar 2003 12:31:05 -0800
Links: << >>  << T >>  << A >>
"john jakson" <johnjakson@yahoo.com> wrote in message 
> OSX is a great platform but it won't help, way too expensive, way too
> little cpu.
> 
> I would say to drop support for Windows and leave it all to Linux, at
> least the APIs are more friendly to complex EDA SW dev, and not
> endlessly being changed as MS is prone to do.
> 
> And Intel/Linux boxes are the cheapest/fastest way to go. Linux is
> ready for 64bit cpus IIRC. Anyway the high end FPGA tool chain is more
> & more becoming the same as the ASIC flow which has long been almost
> totally nix.
> 


Alfredo

Article: 53145
Subject: Partial reconfiguration
From: thetallman63@yahoo.com (Sumanth Donthi)
Date: 4 Mar 2003 12:49:00 -0800
Links: << >>  << T >>  << A >>
Hi!

  Can anyone let me how partial reconfiguration achieved in Atmel
AT40k and lattice ispXPGA FPGAs

regards,
Sumanth

Article: 53146
Subject: Re: How to select the chip before using FPGA?
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 04 Mar 2003 13:54:21 -0800
Links: << >>  << T >>  << A >>
LUT-based programmable chips with their configuration stored in latches
(and thus called "SRAM-based") are generally called FPGA ( as are the
antifuse parts from Actel and Quicklogic)

When Altera added such devices to their  line they had emotional,
political, or legal concerns to call them FPGAs, so they insisted on the
CPLD label. But this hang-up seems to be over, now that the lawsuit with
Xilinx is settled.
Do like the rest of the world, just call all LUT and "SRAM" -based
devices FPGAs. 
Life is too short to be hung up on semantics.

Peter Alfke, Xilinx Applications.
==========================
siriuswmx wrote:
> 
> Thank you .
> I prefer the chip APEX20K , but it is FPGA or CPLD, How to
> differentiate FPGA from CPLD?  and are there mang differences of the
> programming between FPGA and CPLD ?
> :)
> brad@tinyboot.com (Brad Eckert) wrote in message >
> > Both companies claim to have the lowest cost FPGAs. 8-)
> >
> > I haven't used Altera, so I can't make a good comparison. But,
> > installing ISE Webpack was very easy. I got the CD and a product key
> > from Xilinx for free, and it will run forever. The next thing I knew I
> > was pushing buttons and synthesizing and fitting VHDL. Too cool.
> >
> > Altera uses a third party synthesis tool with Quartus, so licensing
> > isn't so simple. AKAIK the Mentor evaluation license lasts for 30
> > days.

Article: 53147
Subject: Re: Implementation of latch in FPGA
From: johnjakson@yahoo.com (john jakson)
Date: 4 Mar 2003 14:23:45 -0800
Links: << >>  << T >>  << A >>
J_Jeniffer@excite.com (Jeniffer) wrote in message news:<ded21c45.0303040224.10dfe510@posting.google.com>...
> Hi all,
> I am trying to implement a design in virtex device. My design contains
> quite a few latches (intended). When I implement the design and open 
> the design in the FPGA editor, I see that the latches are implemented 
> using LUTs and not using the registers in the slice. The device contains 
> free resources of registers. Is there a way, I can force the latches to 
> be implemented in registers (other than using primitives)? I would 
> prefer the code to be portable. 
> 
> My code (VHDL) for latch looks something like this:
> 
> process (enable, din)
> begin
> if (enable = 0) then
> dout <= din;
> else 
> dout <= dout;
> end if;
> end process;
> 
> Thankyou for your time,
> Jeniffer

If you are a newbie, you really^n shouldn't be using latches period,
its bad all round for many reasons, enough to hang yourself by. Stick
to syncronous clocked flops & you will do so much better.

If you are an old pro, then you will already know when latches are ok
to use & how to code them (no else), I can think of some really good
reasons to use them in full custom ASICs, but I am damned if I would
ever use them in FPGA. Even in most ASIC foundries, you often wouldn't
be allowed to insert latches in a design with out detailed case by
case waivers. That means using latches in FPGA means it likely won't
port to an ASIC, so why will it work in FPGA?

Sorry to come on like that, but most of us learnt our lessons on
latches. Same as the GOTO statement. Sign of badly written code. You
can usually get same/better result with DFlops. But IIRC most fast
cpus use latches for pipelines because they can allow faster clocking.

JJ

Article: 53148
Subject: Re: Implementation of latch in FPGA
From: paul <paul@ecoms.fr>
Date: Tue, 04 Mar 2003 22:52:29 +0000
Links: << >>  << T >>  << A >>
Jeniffer wrote:

> Hi all,
> I am trying to implement a design in virtex device. My design contains
> quite a few latches (intended). 
I think you can use RAM elements to synthesise a latch ... This way is 
documented on Xilinx website...

Article: 53149
Subject: Re: Implementation of latch in FPGA
From: David R Brooks <daveb@iinet.net.au>
Date: Wed, 05 Mar 2003 07:19:25 +0800
Links: << >>  << T >>  << A >>
 As others have written, your code doesn't actually infer a latch. 

 Indeed, you should not be using latches unless you are very sure what
you are doing. One of their few uses on a FPGA is in linking
asynchronous clock domains (itself a very specialised business).
 There is a design note on Xilinx TechXclusives that does this.

 Download a copy of the Xilinx Libraries Guide: it includes sample
code to instantiate all the different primitives.
 Xilinx will implement a latch using the asynchronous set/reset inputs
to a flipflop.

J_Jeniffer@excite.com (Jeniffer) wrote:

:Hi all,
:I am trying to implement a design in virtex device. My design contains
:quite a few latches (intended). When I implement the design and open 
:the design in the FPGA editor, I see that the latches are implemented 
:using LUTs and not using the registers in the slice. The device contains 
:free resources of registers. Is there a way, I can force the latches to 
:be implemented in registers (other than using primitives)? I would 
:prefer the code to be portable. 
:
:My code (VHDL) for latch looks something like this:
:
:process (enable, din)
:begin
:if (enable = 0) then
:dout <= din;
:else 
:dout <= dout;
:end if;
:end process;
:
:Thankyou for your time,
:Jeniffer




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