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Messages from 54000

Article: 54000
Subject: Re: microblaze gnu tool info ?
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 31 Mar 2003 10:12:10 +1000
Links: << >>  << T >>  << A >>
John Williams wrote:

I should have added :

> Muzaffer Kal wrote:
> 
 >> When one gets the EDK, do you get the sources on the CD ?

No.  At least not with the current EDK release.

John


Article: 54001
Subject: $4000 FPGAs
From: khimbittle@cliftonREMOVEsystems.com (Khim Bittle)
Date: Mon, 31 Mar 2003 03:45:37 GMT
Links: << >>  << T >>  << A >>
hello folks ...  while tooling around the arrow site this evening
doing some price comparisons ... I noticed that altera has million
gate plus FPGA's that are priced in the $2000-4000 range , holly geeze
!! , yes I know a "good price or volume price " is certainly lower ...
but does anyone outside of perhaps the military actually buy and build
product with FPGA's that cost a couple of grand ??  just curious ...
my designs are always under such cost pressure that part prices much
over 100 bucks is difficult to use ... thanks for the enlightenment ..
KB


Article: 54002
Subject: Re: $4000 FPGAs
From: "Jerry" <nospam@nowhere.com>
Date: Sun, 30 Mar 2003 23:00:29 -0500
Links: << >>  << T >>  << A >>
Well, the short answer is yes they do buy them. They are perfect as a
breadboard ASIC. I take it you got a look at the published prices. If you
are serious get
a quote. I think you'll find that the quoted prices are lower. One more
thing, beat Peter
against Paul for better prices. Let them both know that you are looking at
the other
guy's devices.


"Khim Bittle" <khimbittle@cliftonREMOVEsystems.com> wrote in message
news:3e87b820.8088935@news.compuserve.com...
> hello folks ...  while tooling around the arrow site this evening
> doing some price comparisons ... I noticed that altera has million
> gate plus FPGA's that are priced in the $2000-4000 range , holly geeze
> !! , yes I know a "good price or volume price " is certainly lower ...
> but does anyone outside of perhaps the military actually buy and build
> product with FPGA's that cost a couple of grand ??  just curious ...
> my designs are always under such cost pressure that part prices much
> over 100 bucks is difficult to use ... thanks for the enlightenment ..
> KB
>



Article: 54003
Subject: Re: $4000 FPGAs
From: Phil Hays <SpamPostmaster@attbi.com>
Date: Mon, 31 Mar 2003 04:28:07 GMT
Links: << >>  << T >>  << A >>
Khim Bittle wrote:

> hello folks ...  while tooling around the arrow site this evening
> doing some price comparisons ... I noticed that altera has million
> gate plus FPGA's that are priced in the $2000-4000 range , holly geeze
> !! , yes I know a "good price or volume price " is certainly lower ...
> but does anyone outside of perhaps the military actually buy and build
> product with FPGA's that cost a couple of grand ??  just curious ...
> my designs are always under such cost pressure that part prices much
> over 100 bucks is difficult to use ... thanks for the enlightenment ..

A few reasons why I've seen large expensive FPGAs are used include: 

1) ASIC emulation.  Build a few boards with FPGAs so that the whole
system can be verified BEFORE spending NREs that can exceed $1,000,000. 
FPGAs are cheap if you avoid spending the NRE twice, eh?  And the system
with FPGAs might be a way to start up production.

2) Big and odd types of problems.  Suppose you need to build a machine
that will move and process many gigabytes/second of some type of data. 
This isn't a low cost sort of problem, and it's likely to be a low (one
to hundreds) volume type of problem...  If it was high volume you might
think of designing an ASIC to replace it.

3) Changeable types of problems.  Suppose you need to build a machine
that will move and do FOO to many gigabytes/second.  Sometime next
month, you will need to be doing BAR to the same data stream.  Later
this year you will need to do FOOBAR to the data.  Sometime next year
you will will need to be doing something completely different to the
same data stream.  It will can sense to put lots more FPGA into this
design than is really needed to do FOO, BAR or FOOBAR, as building and
installing new PWB can cost more than just buying more FPGA now.


-- 
Phil Hays

Article: 54004
Subject: Re: $4000 FPGAs
From: hmurray@suespammers.org (Hal Murray)
Date: Mon, 31 Mar 2003 05:51:21 -0000
Links: << >>  << T >>  << A >>
>hello folks ...  while tooling around the arrow site this evening
>doing some price comparisons ... I noticed that altera has million
>gate plus FPGA's that are priced in the $2000-4000 range , holly geeze
>!! , yes I know a "good price or volume price " is certainly lower ...
>but does anyone outside of perhaps the military actually buy and build
>product with FPGA's that cost a couple of grand ??  just curious ...
>my designs are always under such cost pressure that part prices much
>over 100 bucks is difficult to use ... thanks for the enlightenment ..

Consider small volume runs.

What is the NRE for a PCB with lots of layers?

What is the cost of several PCBs and backplane and connectors and
bigger power supply and ... to solve the same problem with less
expensive FPGAs?

What about the design time for those two systems?

If you have a problem that fits well with that size chip,
it's probably cheaper than the alternatives.  (Otherwise
they wouldn't sell (m)any of them.)

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 54005
Subject: Re: $4000 FPGAs
From: johnjakson@yahoo.com (john jakson)
Date: 30 Mar 2003 23:47:33 -0800
Links: << >>  << T >>  << A >>
khimbittle@cliftonREMOVEsystems.com (Khim Bittle) wrote in message news:<3e87b820.8088935@news.compuserve.com>...
> hello folks ...  while tooling around the arrow site this evening
> doing some price comparisons ... I noticed that altera has million
> gate plus FPGA's that are priced in the $2000-4000 range , holly geeze
> !! , yes I know a "good price or volume price " is certainly lower ...
> but does anyone outside of perhaps the military actually buy and build
> product with FPGA's that cost a couple of grand ??  just curious ...
> my designs are always under such cost pressure that part prices much
> over 100 bucks is difficult to use ... thanks for the enlightenment ..
> KB

Yes it is possible. For a prototype $ is almost irrelevant as long as
there is a way out.

For Xilinx I just found out has a program that allows partial working
parts that function with a specific bit file to be sold at a fraction
(20%?) of 100% working FPGA. Don't know if Altera has the same
discount on partials. Once you have a bit file for production, send it
to them & they screen for ones that will work with it. Actually Altera
IIRC still has the route to fixed GAs to replace FPGA for production
so maybe not an issue since its about the same 20% price point.

Think about it, if things you aren't using don't work but don't kill a
device, its still useable to you for production. But if you should
slightly change your design to use more logic, I'd guess you could get
stuck with expensive duds not useful to anyone. Perhaps the tools can
be given a dead list to walk around those areas, so design can be
revised till actually run out of resources. If each device was
slightly different, that could mean a custom PR bitfile for each unit
shipped, nargh.

I always thought $13k was high for xcv10000? when I saw it awhile
back, I just take that to mean, look elsewhere for the moment.

JJ

Article: 54006
Subject: Re: Anyone have difficulty downloading this core?
From: nospammers@n0spam.org (Sam Walton)
Date: Mon, 31 Mar 2003 08:09:29 GMT
Links: << >>  << T >>  << A >>
On Tue, 25 Mar 2003 22:54:11 -0000, ad.rast.7@nwnotlink.NOSPAM.com
(Alex Rast) wrote:

>http://www02.so-net.ne.jp/~morioka/cqpic.htm
>
>Supposedly a PIC16F84 implementation in VHDL. Version 1.00b appears to be 
>downloadable on the site. But when I click the link, I get the following:
>
>"Forbidden
>You don't have permission to access /fb3/morioka/pic100a/cqpic100b.exe on 
>this server."
>
Alex,
I worked at a large ISP for several years.  We would get customer
complaints like this when our DNS was having problems.  Some sites
configure for reverse lookup to valid domain and/or  reverse then
forward to verify domain.  Find out your true IP and use dig or
nslooup to check the reverse and forward values.

I tried the download (as others have) and it worked ok, got
the true zip

HTH

>i.e. the standard no-access message. Are others running into this? If so, 
>is there some other location from which I can download? Or is it somehow 
>something in my environment that I need to change in order to download 
>successfully?
>-- 
>Alex Rast
>ad.rast.7@nwnotlink.NOSPAM.com
>(remove d., .7, not, and .NOSPAM to reply)


Article: 54007
Subject: Re: microblaze gnu tool info ?
From: Muzaffer Kal <kal@dspia.com>
Date: Mon, 31 Mar 2003 08:19:28 GMT
Links: << >>  << T >>  << A >>
On Mon, 31 Mar 2003 07:33:40 +1000, John Williams
<jwilliams@itee.uq.edu.au> wrote:

>Muzaffer Kal wrote:
>> Hi,
>> I guess some people here must be working with Microblaze processors. I
>> understand that Microblaze EDK ships with a port of GNU tools. Are the
>> sources for these tools available (from the GPL I understand that they
>> must be). When one gets the EDK, do you get the sources on the CD ?
>> 
>Hi Muzaffer,
>
>The EDK runs on top of a modified version of Cygwin, called Xygwin[1]. 
>The gnu tools (mb-gcc, mb-ld, etc etc) run within Xygwin.  The source 
>for these tools is publicly available for download from Xilinx.  You 
>don't need to be an EDK customer to obtain it.
>
>I have a copy here, it's several hundred megabytes.  I looked but can't 
>find the place on xilinx's website where I downloaded it.
>
>John
>
>[1] The chances from Cygwin->Xygwin are very small - it's possible to 
>make the microblaze tools run under normal cygwin, which is what I'm 
>doing here.

Thanks for the tip. I found it here:
http://www.xilinx.com/guest_resources/gnu/index.htm

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Article: 54008
Subject: JBits & Tristate
From: Florian-Wolfgang Stock <f.stock@tu-bs.de>
Date: Mon, 31 Mar 2003 11:10:59 +0200
Links: << >>  << T >>  << A >>
Hello,

if I have verilog-lines for a Tristate inout like this:

inout [32:0] DATA;
assign DATA = WRITE ? DATAOUT : 32'hzzzzzzzz;

how would I do this in JBits?  I work with the Board-Class, and
my code looks like this:

int tmp=board.addInput("DATAIN",diBus);
int tmp2=board.addOutput("DATAOUT", doBus);

Both (DATAIN and DATAOUT) have in the ucf-file, which I parse with

board.implement(0,"myucffile.ucf");

the same LOCs. I try to connect the Tristate-Line with this command:

board.setTristate(tmp2, triNet);

and with this command I am not sure, because the javadoc (and the
tutorial too) is at this functions not very helpfull. Are there any
more calls necessary for instantiating the Tristateline? And what
signal enables the z's? Must the triNet be 1 or 0? I am thankful for
any help (or at least a good hint where I can look for it).

Thanks in Advance
Florian
-- 
int m,u,e=0;float l,_,I;main(){for(;1840-e;putchar((++e>907&&942>e?61-m:u)
["\t#*fg-pa.vwCh`lwp-e+#h`lwP##mbjqloE"]^3))for(u=_=l=0;79-(m=e%80)&&
I*l+_*_<6&&26-++u;_=2*l*_+e/80*.09-1,l=I)I=l*l-_*_-2+m/27.;}

Article: 54009
Subject: ModelSIM XE wave files
From: "Michael Nicklas" <michaeln@nospam.slayer.com>
Date: Mon, 31 Mar 2003 10:43:37 +0100
Links: << >>  << T >>  << A >>
Hi

does anybody know if there is a way to export the wave file created during a
simulation to a Word document or other package instead of just taking a
screen capture??

I honestly cant seem to find anything about this in the pdf documentation or
release notes etc.

Thanks in advance.

--
Cheers!

Mike



Article: 54010
Subject: Re: $4000 FPGAs
From: Mike Harrison <mike@whitewing.co.uk>
Date: Mon, 31 Mar 2003 12:29:22 +0100
Links: << >>  << T >>  << A >>
On Mon, 31 Mar 2003 04:28:07 GMT, Phil Hays <SpamPostmaster@attbi.com> wrote:

>Khim Bittle wrote:
>
>> hello folks ...  while tooling around the arrow site this evening
>> doing some price comparisons ... I noticed that altera has million
>> gate plus FPGA's that are priced in the $2000-4000 range , holly geeze
>> !! , yes I know a "good price or volume price " is certainly lower ...
>> but does anyone outside of perhaps the military actually buy and build
>> product with FPGA's that cost a couple of grand ??  just curious ...
>> my designs are always under such cost pressure that part prices much
>> over 100 bucks is difficult to use ... thanks for the enlightenment ..
>
>A few reasons why I've seen large expensive FPGAs are used include: 
>
>1) ASIC emulation.  Build a few boards with FPGAs so that the whole
>system can be verified BEFORE spending NREs that can exceed $1,000,000. 
>FPGAs are cheap if you avoid spending the NRE twice, eh?  And the system
>with FPGAs might be a way to start up production.
>
>2) Big and odd types of problems.  Suppose you need to build a machine
>that will move and process many gigabytes/second of some type of data. 
>This isn't a low cost sort of problem, and it's likely to be a low (one
>to hundreds) volume type of problem...  If it was high volume you might
>think of designing an ASIC to replace it.
>
>3) Changeable types of problems.  Suppose you need to build a machine
>that will move and do FOO to many gigabytes/second.  Sometime next
>month, you will need to be doing BAR to the same data stream.  Later
>this year you will need to do FOOBAR to the data.  Sometime next year
>you will will need to be doing something completely different to the
>same data stream.  It will can sense to put lots more FPGA into this
>design than is really needed to do FOO, BAR or FOOBAR, as building and
>installing new PWB can cost more than just buying more FPGA now.

..and of course the cost of the design man-hours for most things that need such megagates will
probably make the cost of the chips fairly trivial.....


Article: 54011
Subject: Re: ModelSIM XE wave files
From: "Laurent Gauch, Amontec" <laurent.gauch@amontec.com>
Date: Mon, 31 Mar 2003 14:09:49 +0200
Links: << >>  << T >>  << A >>
swave the dataset, or work directly on the list


Michael Nicklas wrote:

> Hi
>
> does anybody know if there is a way to export the wave file created 
> during a
> simulation to a Word document or other package instead of just taking a
> screen capture??
>
> I honestly cant seem to find anything about this in the pdf 
> documentation or
> release notes etc.
>
> Thanks in advance.
>
> --
> Cheers!
>
> Mike
>
>


Article: 54012
Subject: Re: Help reg Target device & synthesis
From: "Laurent Gauch, Amontec" <laurent.gauch@amontec.com>
Date: Mon, 31 Mar 2003 15:42:06 +0200
Links: << >>  << T >>  << A >>
First one, try to use a bigger device (3040 ...).
If you need the same time, yes that's your code.
If it's very faster, your 3020 is certaily a little bit small for you 
specific design

Laurent Gauch
www.amontec.com

Prasanth Anbalagan wrote:

> Hai
>      I have a problem regarding the synthesis part.I'm using Xilinx
> Foundation series 3.1i & I 've set the Taget device family as
> XC3000.Device:3020APC68...Speed -6.But the synthesis takes more than
> an hour to complete.Is that there is a problem with my code or the
> taget device specification ?
>
> Bye
> Prasanth



Article: 54013
Subject: connecting 2 FPGAs
From: "Andreas Wortmann" <wortmann@informatik.hs-bremen.de>
Date: Mon, 31 Mar 2003 16:04:46 +0200
Links: << >>  << T >>  << A >>
Hi,

I need to connect 2 FPGAs (Xilinx SpartanIIe, Virtex) via a parallel data
link.
i.e. 80Bit @ 50Mhz, bidirectional.

Does somebody have any experience what to take care of or does somebody know
some good reference ?

thank, andreas



Article: 54014
Subject: Re: $4000 FPGAs
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Mon, 31 Mar 2003 09:11:53 -0500
Links: << >>  << T >>  << A >>
On Sun, 30 Mar 2003 22:45:37 -0500, Khim Bittle wrote:

> hello folks ...  while tooling around the arrow site this evening doing
> some price comparisons ... I noticed that altera has million gate plus
> FPGA's that are priced in the $2000-4000 range , holly geeze !! , yes I
> know a "good price or volume price " is certainly lower ... but does
> anyone outside of perhaps the military actually buy and build product
> with FPGA's that cost a couple of grand ??  just curious ... my designs
> are always under such cost pressure that part prices much over 100 bucks
> is difficult to use ... thanks for the enlightenment .. KB
 
In any low volume system these make sense. The cost of developing an ASIC
can me millions more that an FPGA for several reasons, 1) mask charges
run from $500K to $1.3M, 2) Tools, $250-500K, 3) Much longer development
times and costs, $500K-$1.5M. If you take the low end of the those costs
then you can see that an ASIC can cost you at least a $1M more to develop
than an FPGA. If you are only going to use 500 chips over the life of the
design you would break even on a $2000 FPGA even if the resulting ASIC
were free. When you factor in the value of getting to market a year
earlier using an FPGA, even a very expensive one, it's a no brainer.

Article: 54015
Subject: Re: Pin failure detection
From: "David Kinsell" <kinsell@poboxyz.com>
Date: Mon, 31 Mar 2003 14:13:34 GMT
Links: << >>  << T >>  << A >>
There's another commercial solution at www.universalscan.com, but it's also
a rather pricey way to just flip a pin up and down.  There's got to be some lower-
cost alternatives out there.


"Joze Dedic" <joze.dedic@fe.uni-lj.si> wrote in message news:b61ubr$dl3$1@planja.arnes.si...
> Thank you for your answer. I have spend several hours searching for
> appropriate solutions in a meantime.
> Now, when I know that it is possible, I would like to address the people who
> know how to do that with non commercial tools, if there are any.
> What I would like is to simply read from and write to pin. Is that too much
> for free?
>
> Or there might be some commercial solution with university price-discount. I
> am a PhD junior research student an we will use it for educational reasons.
>
> Regards, Joze Dedic
>
> "Gordon Hollingworth" <gordon.hollingworth@NOSPAMoptionexist.co.uk> wrote in
> message news:b61ka7$fok$1$8300dec7@news.demon.co.uk...
> > Joze,
> >
> > The XJTAG tool (www.xjtag.com) can be used in the way you suggest, more
> > specifically it will implement the connection test to check that all the
> > pins are down on a device, but it also does a lot more...
> >
> > XJEase is a simple BASIC like programming language that can be used to
> write
> > tests for non-JTAG devices like RAMs or network controllers, using this
> tool
> > you can write code to do loopback tests on ethernet controllers, or even
> > read the time from a RTC, wait a second and read it again!
> >
> > Also the XJLink JTAG hardware can be bought with the XJAPI interface so
> you
> > can write your own JTAG code to access embedded processors etc.
> >
> > If you need any more information you can contact us on support@xjtag.com
> >
> > Cheers
> >
> > Gordon Hollingworth PhD
> >
> >
> > Dr Gordon Hollingworth
> >
> >
> > "Joze Dedic" <joze.dedic@fe.uni-lj.si> wrote in message
> > news:b61gsv$2c1$1@planja.arnes.si...
> > > Hi
> > >
> > > I would like to know if/how it is possible to detect pin failure through
> > > boundary scan - i.e. I would like to know if my CPLD (or FPGA) has all
> > pins
> > > fully working, because I have difficulties measuring all the signals and
> > > also difficulties with devices connected to CPLD. So by now you have
> > > probably figured it out - I  can't find where the problem is.
> > >
> > > Much thanks.
> > >
> > > Joze Dedic
> > >
> > >
> >
> >
>
>



Article: 54016
Subject: Re: ModelSIM XE wave files
From: "Michael Nicklas" <michaeln@nospam.slayer.com>
Date: Mon, 31 Mar 2003 15:23:55 +0100
Links: << >>  << T >>  << A >>
ideally I would like to save it in a format where the waveform can be viewed
as opposed to a list of the signal transitions, is this possible using the
save dataset option and if so, how?

I am (extremely) new to this tool so please excuse my questions if they seem
rather petty!

Thanks

Mike

"Laurent Gauch, Amontec" <laurent.gauch@amontec.com> wrote in message
news:3E88300D.2090503@amontec.com...
> swave the dataset, or work directly on the list
>
>
> Michael Nicklas wrote:
>
> > Hi
> >
> > does anybody know if there is a way to export the wave file created
> > during a
> > simulation to a Word document or other package instead of just taking a
> > screen capture??
> >
> > I honestly cant seem to find anything about this in the pdf
> > documentation or
> > release notes etc.
> >
> > Thanks in advance.
> >
> > --
> > Cheers!
> >
> > Mike
> >
> >
>



Article: 54017
Subject: Re: connecting 2 FPGAs
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Mon, 31 Mar 2003 14:43:17 +0000 (UTC)
Links: << >>  << T >>  << A >>
Andreas Wortmann <wortmann@informatik.hs-bremen.de> wrote:
: Hi,

: I need to connect 2 FPGAs (Xilinx SpartanIIe, Virtex) via a parallel data
: link.
: i.e. 80Bit @ 50Mhz, bidirectional.

: Does somebody have any experience what to take care of or does somebody know
: some good reference ?

What distance, how many bits? Do you consider dedicated unidirectional lines?

Couldn't you use a bigger chip and get all logic into this one, so no more
need for the interconnect! 

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 54018
Subject: Re: ModelSIM XE wave files
From: "Michael Rhotert" <mrhotert@yahoo.com>
Date: Mon, 31 Mar 2003 16:53:25 +0200
Links: << >>  << T >>  << A >>
"Michael Nicklas" <michaeln@nospam.slayer.com> wrote
> Hi
>
> does anybody know if there is a way to export the wave file created during
a
> simulation to a Word document or other package instead of just taking a
> screen capture??
>

Print the waveform to a postscript file, open the file in a postscript
viewer
(GSview, ask Google) and copy/paste the image to your word processor.

/Michael



Article: 54019
Subject: Xilinx announces 90nm sampling today!
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Mon, 31 Mar 2003 07:39:37 -0800
Links: << >>  << T >>  << A >>
Really?

Have just annouced 90nm shipped samples.

http://biz.yahoo.com/prnews/030331/sfm087_1.html

so I would suspect that you might want to get in touch with another
distributor....

Might find 1+ million gates for a whole lot less....

Austin

"B. Joshua Rosen" wrote:

> On Sun, 30 Mar 2003 22:45:37 -0500, Khim Bittle wrote:
>
> > hello folks ...  while tooling around the arrow site this evening doing
> > some price comparisons ... I noticed that altera has million gate plus
> > FPGA's that are priced in the $2000-4000 range , holly geeze !! , yes I
> > know a "good price or volume price " is certainly lower ... but does
> > anyone outside of perhaps the military actually buy and build product
> > with FPGA's that cost a couple of grand ??  just curious ... my designs
> > are always under such cost pressure that part prices much over 100 bucks
> > is difficult to use ... thanks for the enlightenment .. KB
>
> In any low volume system these make sense. The cost of developing an ASIC
> can me millions more that an FPGA for several reasons, 1) mask charges
> run from $500K to $1.3M, 2) Tools, $250-500K, 3) Much longer development
> times and costs, $500K-$1.5M. If you take the low end of the those costs
> then you can see that an ASIC can cost you at least a $1M more to develop
> than an FPGA. If you are only going to use 500 chips over the life of the
> design you would break even on a $2000 FPGA even if the resulting ASIC
> were free. When you factor in the value of getting to market a year
> earlier using an FPGA, even a very expensive one, it's a no brainer.


Article: 54020
Subject: Re: Xilinx announces 90nm sampling today!
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Mon, 31 Mar 2003 15:52:59 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3E886139.96955371@xilinx.com>,
Austin Lesea  <Austin.Lesea@xilinx.com> wrote:
>Really?
>
>Have just annouced 90nm shipped samples.
>
>http://biz.yahoo.com/prnews/030331/sfm087_1.html
>
>so I would suspect that you might want to get in touch with another
>distributor....
>
>Might find 1+ million gates for a whole lot less....

Thats "250,000 quantities at (the end of?) 2004".  :)

-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 54021
Subject: Re: connecting 2 FPGAs
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Mon, 31 Mar 2003 11:18:54 -0500
Links: << >>  << T >>  << A >>
Andreas,
    I assume that these two chips are located in different locations.  If
not, why not go to the next larger size and keep the interface inside one
chip.  It would be much cleaner that way.  Given the absolute requirement
for two chips, you might want to look at serially connecting groups of bits
to reduce the pin count.  Other that that, I would suspect that the obvious
brute force solution is the only way to do it.  One other comment would be
to look at simultaneous switching issues.  You might want to consider
stagerring the switching in some fashion.

Theron

"Andreas Wortmann" <wortmann@informatik.hs-bremen.de> wrote in message
news:b69hvv$ds6$1@hermes1.rz.hs-bremen.de...
> Hi,
>
> I need to connect 2 FPGAs (Xilinx SpartanIIe, Virtex) via a parallel data
> link.
> i.e. 80Bit @ 50Mhz, bidirectional.
>
> Does somebody have any experience what to take care of or does somebody
know
> some good reference ?
>
> thank, andreas
>
>



Article: 54022
Subject: Re: Xilinx announces 90nm sampling today!
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Mon, 31 Mar 2003 09:04:50 -0800
Links: << >>  << T >>  << A >>
Nicholas,

The original question was "why would anyone spend $4,000."

Good question.  No one does.  Well almost no one.  I suppose the 'monster'
FPGAs (like the 2V8000, or the 2VP100) will always command a premium until
they, too, are mainstream - just a question of demand).

1M+ gates up until now has certainly been much less than $4,000 (even in small
quantities).

Now we are talking about even less money for 1M+ gates in 90 nm.

ASICs are all but dead except for those really big jobs that can afford the
$80M++ price tag to develop them.  Or those jobs where low current is required
(ie cell-phones).

Even televisions don't sell enough to afford some of the new ASIC pricetags.
Think about it.  An "appliance" doesn't sell in large enough volume to have
its own ASIC.

The recent EETimes article on IP at these geometries was especially telling.
Integration of IP at 130 nm and 90nm is a hightmare......etc. etc. etc.  The
80M$ figure above was from that article.

So 'cheap' ASICs are stuck at 180nm (and above).  But with 90nm FPGAs we are
three or more techology steps ahead (.15, .13, .09), and that makes us a
better deal.

Austin

"Nicholas C. Weaver" wrote:

> In article <3E886139.96955371@xilinx.com>,
> Austin Lesea  <Austin.Lesea@xilinx.com> wrote:
> >Really?
> >
> >Have just annouced 90nm shipped samples.
> >
> >http://biz.yahoo.com/prnews/030331/sfm087_1.html
> >
> >so I would suspect that you might want to get in touch with another
> >distributor....
> >
> >Might find 1+ million gates for a whole lot less....
>
> Thats "250,000 quantities at (the end of?) 2004".  :)
>
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu


Article: 54023
Subject: Re: microblaze gnu tool info ?
From: Petter Gustad <newsmailcomp4@gustad.com>
Date: 31 Mar 2003 19:28:52 +0200
Links: << >>  << T >>  << A >>
John Williams <jwilliams@itee.uq.edu.au> writes:

> Muzaffer Kal wrote:
> > Hi,
> > I guess some people here must be working with Microblaze processors. I
> > understand that Microblaze EDK ships with a port of GNU tools. Are the
> > sources for these tools available (from the GPL I understand that they
> > must be). When one gets the EDK, do you get the sources on the CD ?
> >
> Hi Muzaffer,
> 
> The EDK runs on top of a modified version of Cygwin, called Xygwin[1].

Is there a native version for Solaris or Linux?

> The gnu tools (mb-gcc, mb-ld, etc etc) run within Xygwin.  The source
> for these tools is publicly available for download from Xilinx.  You
> don't need to be an EDK customer to obtain it.
> I have a copy here, it's several hundred megabytes.  I looked but
> can't find the place on xilinx's website where I downloaded it.

Does anybody else have an URL?

I checked for the EDK price:

http://www.xilinx.com/xlnx/xebiz/productview3.jsp?category=-18886

But it's "Out of Stock". Does it mean that Xilinx is out of CD-R's,
manuals, etc. It would be easier if it was possible to just pay and
download the kit.

Petter
-- 
________________________________________________________________________
Petter Gustad         8'h2B | ~8'h2B        http://www.gustad.com/petter

Article: 54024
Subject: uP interface question
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Mon, 31 Mar 2003 17:39:05 GMT
Links: << >>  << T >>  << A >>
Impementing a microprocessor interface to logic inside an XC2V1000.  The I/F
is through port I/O on the uP rather than the external memory bus.  The uP
is a fairly efficient 25MHz 8051 derivative, so port I/O speed will be <10
MHz , probably <5MHz.

Some of the registers the uP will see will actually be access points into
SelecRAM lookup tables that the uP needs to fill.

In order to maximize access speed I'm thinking of using both edges of the
uP's WE pulse to run these SelecRAM ports.  The idea is to capture the data
byte on the leading edge and use the trailing edge to increment the address
counter that is driving the SelectRAM block.  With this, all the uP has to
do is present  new data and pulse WE until it fills the memory bank.

I'm looking for feedback on this technique.  Any problems?  Any reason for
not taking this approach?  Any other approaches that might warrant
consideration?

Thank you!

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"





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