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Messages from 53350

Article: 53350
Subject: Re: Cyclone power up problem
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 12 Mar 2003 07:52:14 +1300
Links: << >>  << T >>  << A >>
Martin Schoeberl wrote:
> 
> Hello Thorsten,
> 
> > Xilinx provides a nice app note which describes you problem (Power on
> surge)
> > and gives an advices how to deal with it.
> > Xilinx app notes 450 (Power-On requirements for the Spartan II and Spartan
> > IIe famlies)
> > and 451 (Power Assist circuits for the Spartan II and Spartan IIe
> families)
> >
> Thanks for the information. These app notes describe the problem in detail.
> Would be nice if these information is available for the Altera FPGAs.
> 
> Just Power Assist circuits look for me like a little work around. I've found
> a solution ('work around') for my board: Adding some 'charge' from the 3.3V
> over two diodes to the 1.5V to help the drop-down regulator to start up.
> 
> If there is interest in some oscilloscop pictures about the problem and an
> equivilant circuit to test your power supply for Cyclone devices I can write
> a summary on my web site.

Good idea 
- also take some tests with it as cold as practical, as this effect
worsens
as temp drops. 
 With diodes you will need to watch for Vcc 'creep' above 1.5V 
at low Icc and low temp, and for insufficent feed-forward current,
limited by the diode slope, and the 3.3V itself.

 Suggestion for the IC vendors - Spice models for this effect anyone ?

-jg

Article: 53351
Subject: Re: Can you recommend a text on...?
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 11 Mar 2003 10:55:00 -0800
Links: << >>  << T >>  << A >>
In the world of FPGAs, a lot depends on the hardware-implementation
choices made by the various IC manufacturers:
Remember when dedicated carry was first implemented. It made almost (!)
all sophisticated carry schemes meaningless because the simple dedicated
carry was faster than any complex (programmable) alternative ( and also
much cheaper = free ). Now the dedicated carry has gotten even faster
(looking at two bits at a time).
Or when dedicated multipliers started to appear....
Or because pipelining became essentially free in flip-flop-rich FPGAs.

It is no secret that dedicated logic is faster and smaller than
programmable logic, but it is also inflexible. So you see us and our
competitors constantly struggling with these trade-offs.
And thus occasionally changing the best application model...

Peter Alfke, Xilinx Application. 
=====================================
m, a, ellis wrote:
> 
> Hi all,
> 
> Could people recommend a good text that meets these requirements, please:
> 
> 1) Describes doing arithmetic in logic,
> 2) with HDL examples, preferably,
> 3) that describes varying levels of optimisation (e.g. divider area/speed
> trade offs, and the various types of adder optimisations)
> 
> and, more difficult,
> 
> 4) how these functions could/should be realised for given types of
> technology (e.g. how carry chains are done in FPGAs (typically), and why
> carry saves wont help).
> 5) comments on combining hardware in an ALU to get more functions in less
> area (a Steve Furber book describes separating a single ALU (ARM2) into
> separate units for logic and arithmetic (later ARM)).
> 
> I have a decent Comp Sci degree, and have read some amount of logic design
> texts, so ideally something that wont waste my time with the truth table
> for a NAND gate. :o)
> 
> There's a web based arithmetic generator (hiding somewhere in my bookmarks,
> hmm, can't find) - I'd like to be able to understand the options to this
> too (Wallace trees, and the like).
> 
> A little on asynchronous arithmetic a bonus (though I'm not very fussed
> about this at the moment).
> 
> Sorry if this looks a bit 'please do my homework', but I really don't know
> where to start with this.
> 
> Cheers
> Martin Ellis
> 
> PS. Brownie points for HDL models of an ARM-style barrel shifter *with an
> explanation* :o)

Article: 53352
Subject: Re: State of the PCB world
From: bobsrefusebin@hotmail.com (Bob Perlman)
Date: 11 Mar 2003 11:07:50 -0800
Links: << >>  << T >>  << A >>
"Stan Lackey" <stanlackey@hotmail.com> wrote in message news:<v6qqiedhqdt445@corp.supernews.com>...
> > > Nowadays, passive components are little flecks of ceramic with solder
> > > pads at each end, small ICs come in tiny flat-packs with centipede
> > > fringes of legs around, and the interesting ones come either in large
> > > flat-packs with centipede fringes, or in BGA form. And I presume the
> > > signal-integrity requirements are such that bread-board, and even the
> > > two-layer PCB, are Right Out.  The BBC Micro and the ISA slot have
> > > gone the way of the dinosaur; the parallel port is dying out.
> 
> Um, folks?  Just because some components are available in these forms,
> doesn't force you to use them!  Even if there are elitists in this group
> that threaten to call you names if you don't!  Components are still
> available in the old forms, if you're doing a project like people used to,
> there's no crime in using components that are easier to handle !!   -Stan

Uh, well, no one will call you names if you use through-hole parts,
but a few of us will point out that such components often have rather
nasty parasitics, particularly inductance.  So if you do a project
with old package types, it may be a good idea to use older, slower
logic families as well.  There's nothing elitist about ground bounce
and signal corruption; they're equal-opportunity system-wreckers.

Have fun storming the castle,
Bob Perlman
Cambrian Design Works

Article: 53353
Subject: Re: Are there any FPGA magazines/journals?
From: johnjakson@yahoo.com (john jakson)
Date: 11 Mar 2003 11:09:18 -0800
Links: << >>  << T >>  << A >>
Joe <Joe@pacbell.net> wrote in message news:<3E6D0679.71C524BF@pacbell.net>...
> ... Thanks in advance ...

Also besides the FPGA companies, look at the EDA companies.

Mentor dishes out quite a bit of free stuff, tutorials events.

Also minievents happen a few times a year, esp in major EE towns

The EDA Tech Forum is happening 
> 3/24 Princeton, NJ 
> 3/27 Waltham, MA 

Register at
http://www.mentor.com/events/tb/tech_forum1 


Check out Symplicity, Xilinx road events too
EETimes etc often links to material of interest

JJ

Article: 53354
Subject: Help understanding 7408 and gate chip
From: nidar@rediffmail.com (Niranjandas)
Date: 11 Mar 2003 11:15:55 -0800
Links: << >>  << T >>  << A >>
please find me if DM7408 chip
 2 input Quad AND gate has ESD diodes(Elesctro static diodes).
 if yes please let me know.
 thank you.
Nidar@rediffmail.com

Article: 53355
Subject: Leon processor + MMU + linux port
From: eiselekd@web.de (Konrad Eisele)
Date: 11 Mar 2003 12:32:03 -0800
Links: << >>  << T >>  << A >>
Anybody who wants to join porting linux on 
Open source processor Leon? (www.gaisler.com)
A MMU has been added. Linux porting can be done
in the Leon sparc simulator "tsim".
For patches and vhdl source of LeonMMU goto
http://www.ra.informatik.uni-stuttgart.de/LeonMMU/
--Greetings Konrad

Article: 53356
Subject: Re: State of the PCB world
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Tue, 11 Mar 2003 15:59:36 -0500
Links: << >>  << T >>  << A >>


Bob Perlman wrote:

> "Stan Lackey" <stanlackey@hotmail.com> wrote in message news:<v6qqiedhqdt445@corp.supernews.com>...
> > > > Nowadays, passive components are little flecks of ceramic with solder
> > > > pads at each end, small ICs come in tiny flat-packs with centipede
> > > > fringes of legs around, and the interesting ones come either in large
> > > > flat-packs with centipede fringes, or in BGA form. And I presume the
> > > > signal-integrity requirements are such that bread-board, and even the
> > > > two-layer PCB, are Right Out.  The BBC Micro and the ISA slot have
> > > > gone the way of the dinosaur; the parallel port is dying out.
> >
> > Um, folks?  Just because some components are available in these forms,
> > doesn't force you to use them!  Even if there are elitists in this group
> > that threaten to call you names if you don't!  Components are still
> > available in the old forms, if you're doing a project like people used to,
> > there's no crime in using components that are easier to handle !!   -Stan
>
> Uh, well, no one will call you names if you use through-hole parts,
> but a few of us will point out that such components often have rather
> nasty parasitics, particularly inductance.  So if you do a project
> with old package types, it may be a good idea to use older, slower
> logic families as well.  There's nothing elitist about ground bounce
> and signal corruption; they're equal-opportunity system-wreckers.
>
> Have fun storming the castle,
> Bob Perlman
> Cambrian Design Works

Bob,
    I am glad you wrote that because I was thinking exactly the same thing.  An additional point...
While BGA parts require some expertise, surface mount capacitors and resistors are a piece of cake.
All it requires is a small tip soldering iron to handle them.  A small iron is helpful but not
required.  Also, paste solder _may_ make it easier to use them.  None of these is required.  Initially,
I would check them for shorts underneath imediately after each part is mounted.  That may save you some
headaches.  I personally hand solder 0603 parts all the time and anything larger is a piece of cake.  I
am 47 years old and wear glasses for everything I do (well almost everthing.)

Theron


Article: 53357
Subject: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
From: john_doebertson@yahoo.com (Chip)
Date: 11 Mar 2003 13:13:45 -0800
Links: << >>  << T >>  << A >>
Had a similar thing happen to me recently.  Check to make sure that
you are not unintentionally connecting a vcc pin on the fpga to a
ground via or vice versa (as has been stated a couple of times
already).

I recently got a board back from a board house and vcc and gnd were
isolated on a unpopulated board, but all the populated boards had the
1.5V connected to the 3.3V.  For a short period of time I thought it
was the fpga, but as it turned out I had accidentally connected one of
the 3.3V fpga pins to the 1.5V net when I was fanning out the part. 
Internally this shorted both power levels together.  In my case it was
an error carried into my layout from the schematic.  Using a bf957
part I had hundreds of power connections and I accidentally connected
one to the wrong net.

I fixed this by milling out the problem via and disconnecting the
incorrect power connection and luckily the fpga works fine.

  


"Nial Stewart" <nial@spamno.nialstewart.co.uk> wrote in message news:<3e6cedbb$0$229$fa0fcedb@lovejoy.zen.co.uk>...
> > Padraig FitzGerald <pfitzgerald@conwin.ie> wrote in message
>  news:ee7c445.-1@WebX.sUN8CHnE...
> > Hi,
> > I was wondering if anybody had come accross this problem when using Xilinx
>  FPGA's and if so do they know how to solve it.
> > I have just recieved a PCB design back from FAB and We are having an issue
>  with a short between the VCC and GND planes. This however
> > only occurs when the Xilinx Spartan XL XCS30 is populated on the board, ie
>  the short is finding it's way through the silicon of the
> > FPGA.
> > Immediately I suspected an error on the footprint of the FPGA but it was
>  correct, then I thought maybe an IO pin which was
> > externally pulled up or down was shorted to the opposite level internal to
>  the chip. Ijn trying to determine this I lifted every pin
> > except the PWR pins and the short still occurs, so I can categorically say
> that the short is iunternal betweent the two levels.
>                                                            ^^^^^^^^^^^^^
> 
> .....or that you've connected one of the power pins to the wrong net, or
> you've not been handling your
> boards with proper ESD protection and the device has been damaged that way
> or......
> 
> > My question is this.
> > Is it possible that when an FPGA leaves the FAB it is configured in this
>  way? Perhaps for ESD protection??? Does anyone know how to
> > overcome this problem?
> 
> Check _everything_ very carefully again, or even better get someone else to
> check it all.
> 
> Nial.

Article: 53358
Subject: Re: FIR Filter from Xilinx
From: johnjakson@yahoo.com (john jakson)
Date: 11 Mar 2003 13:38:29 -0800
Links: << >>  << T >>  << A >>
"Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message news:<NgCRvrS4CHA.2556@exchnews1.main.ntu.edu.sg>...
> Additional info : 
>  
> My input and the filter coefficients have the following bit assignments 
> :
> MSB
> 1 bit : signed bit
> 2 bit : integer
> 9 bit : decimal
> LSB
>  
> Once the output becomes 24 bits, How do I arrange the bit assignment in 
> the output of my filter?
> 
> -----Original Message-----
> From: Basuki Endah Priyanto 
> Posted At: Sunday, March 02, 2003 6:26 AM
> Posted To: fpga
> Conversation: FIR Filter from Xilinx
> Subject: FIR Filter from Xilinx
> 
> 
> Hi,
>  
> I'm newbie in implementation filter in FPGA. I've just create a 
> distributed arithmetic FIR filter from Xilinx Coregen. The input signal 
> is 12 bit and the filter coef bit resolution is 12 bit. Thus, it makes 
> the output signal resolution is about 24 bit. My The bit resolution of 
> my DAC is 12 bit. How to reduce from 24 to 12 bit ?
>  
> pls, gimme advice as i'm newbie in this area.
>  
> Thanks.
>  
> Basuki

Well even if you use CoreGen, you probably should be doing some
analysis in say C beforehand to study whatifs. I won't write the code
for you but you will have signed int array for coeffs & z elements,
you will perform a dot product then shift the z's down (or use cyling
indexes) and insert next signal value. Your output will be easier to
analyize with C than HW dev tools. Sounds like a good text on binary
arithmetic for DSP is in order too.

If your signal is nearly full scale and your coeffs avg value are also
near full scale then your final signal will be right near the top of
24bit output save 1 bit assuming 1 product.

Consider all your math to be fractional, ie +-0.4999 * +-0.4999
+-0.249999 etc.
Always avoid signal or coeff at maximum -0.5 since that can't be
negated.

Now if you accumulate 2 products you could reach max range of 24bit
output right away.

Now if you accumulate 8 products you either need 2 extra overflow bits
or you should scale back your coeffs by 4.

If your coeffs count is n, then you will need n/2 overflow or bits or
scale back coeffs same.

Ofcourse the avg coeff value will be a fraction of peak value so that
also gives you back a few bits of margin. You can also arrange to
fractionally scale the coeffs to maximize the signal in the output
range given a specimen signal. Coeffs can also be scaled to minimize
amount of HW needed if only additions are used by minimizing the coeff
"compexity".

Besides deciding where the best place to take your 12bits of output,
you might take into acount that right shift by n is & never will be
same as div 2^n unless you are using 1's complement (unlikely). For
2's complement the rounding fraction varies with the sign of data but
thats getting a little picky and beyond what most would bother with.
As your DSP knowledge grows, you will need to be more aware of subtle
integer issue.

JJ

Article: 53359
Subject: Re: Can you recommend a text on...?
From: Ray Andraka <ray@andraka.com>
Date: Tue, 11 Mar 2003 22:08:06 GMT
Links: << >>  << T >>  << A >>
I haven't found a single good text on this, you need to pick and choose from
several.
Israel Koren's book ( http://www.amazon.com/exec/obidos/ASIN/1568811608/andraka
)
is a decent primer for computer arithmetic.  It is geared toward hardware but
never explicitly
says so (and has no actual implementations).  Uwe Meyer-Baese has a good book
out on digital
signal processing with FPGAs (
http://www.amazon.com/exec/obidos/ASIN/3540413413/andraka ),
which has some code examples.  For signal processing, especially if doing any
kind of wireless,
I think the Frerking book (
http://www.amazon.com/exec/obidos/ASIN/0442016166/andraka ) is a
must have, as it has a reasonable emphasis on hardware implementations.  Based
on what you've told
me, I think I would pick up the Meyer-Baese book first.

As to the carry chains, these are as far as the user is concerned, ripple carry
structures.  The virtex
circuit actually uses a little bit of carry look ahead in the di-bit to speed
it up a little.  The reason
other carry schemes usually do not fare well in FPGAs is because such schemes
use the general purpose
routing and logic rather than the optimized carry logic.  The general purpose
stuff is about an order of
magnitude slower than the dedicated carry logic, so you need to have huge gains
to overcome the advantage.
The gains by using carry look-ahead, carry save, carry skip etc schemes do not
save enough time to
match the performance of the specialized logic.  Most of these also require
general purpose logic for
the carry logic, where the dedicated chains give you the additional logic for
free.




m, a, ellis wrote:

> Hi all,
>
> Could people recommend a good text that meets these requirements, please:
>
> 1) Describes doing arithmetic in logic,
> 2) with HDL examples, preferably,
> 3) that describes varying levels of optimisation (e.g. divider area/speed
> trade offs, and the various types of adder optimisations)
>
> and, more difficult,
>
> 4) how these functions could/should be realised for given types of
> technology (e.g. how carry chains are done in FPGAs (typically), and why
> carry saves wont help).
> 5) comments on combining hardware in an ALU to get more functions in less
> area (a Steve Furber book describes separating a single ALU (ARM2) into
> separate units for logic and arithmetic (later ARM)).
>
> I have a decent Comp Sci degree, and have read some amount of logic design
> texts, so ideally something that wont waste my time with the truth table
> for a NAND gate. :o)
>
> There's a web based arithmetic generator (hiding somewhere in my bookmarks,
> hmm, can't find) - I'd like to be able to understand the options to this
> too (Wallace trees, and the like).
>
> A little on asynchronous arithmetic a bonus (though I'm not very fussed
> about this at the moment).
>
> Sorry if this looks a bit 'please do my homework', but I really don't know
> where to start with this.
>
> Cheers
> Martin Ellis
>
> PS. Brownie points for HDL models of an ARM-style barrel shifter *with an
> explanation* :o)

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 53360
Subject: Re: picoChip - DSP as fast as an FPGA - is this for real
From: rupert_baines@yahoo.com (Rupert Baines)
Date: 11 Mar 2003 14:15:03 -0800
Links: << >>  << T >>  << A >>
Folks,

Just to reply to the thread...

Yes, the picoChip product is for real.  We have sampled several major
OEMs with working silicon, but we are still focussing on a few key
accounts and it isn't on general release yet.

The performance claims are real too. 430 individual processors (each
reasonably capable) on one die can deliver a huge amount of processing
horsepower;  depending on how you measure it, at least 200
Giga-operations-per-second or 30 giga MACs.  Just take a normal DSP
and multiply by 430 ;)

Although our commercial focus is big, complex comms infrastructure, it
is worth stressing we are a programmale device and could address a
range of problems.

There are a number of companies working on parallel processors.
Classically, the problem has been getting them to co-operate &
cordinate. We've solved that problem - that is heart of the
development. Consequently, the device is very easy to program &
develop for - arguably, easier than most conventional DSPs, and
certainly a lot simpler than FPGAs. Admittedly, we've solved it for
embedded/dedicated systems, not a universal/general-purpose case, but
for the applications we are going for, that is fine.

We have not yet submitted for independent Benchmarks. We are
discussing these with Berkeley Design (www.bdti.org) and I will follow
up with EEMBC too.

However, a couple of trusted analysts have looked at our architecture
(eg Forwaerd Concepts, MPR), and there are articles on the
architecture - these are listed on our website (www.picochip.com). 
One of the most in-depth independent pieces was just published by IEE
(British equivalent of IEEE) in
http://www.iee.org/OnComms/PN/syschip/index.cfm (scroll down a bit to
find the PDF in the library box)
 
I don't want to get flamed for commercial posting, but if anyone is
interested in finding out more, please contact me directly at
rupertb@picochip.com or register at the website.


Rupert Baines
VP Marketing
rupertb@picochip.com




"Jan Gray" <jsgray@acm.org> wrote in message news:<b3lb22$ep0$1@slb9.atl.mindspring.net>...
> "Rita_Conaty" <rita_conaty@yahoo.com> wrote
> > Is it really as fasdt as an FPGA ?
> 
> I sent the following to the fpga-cpu list some months back:
> [http://groups.yahoo.com/group/fpga-cpu/message/1411]
> (((6 GMAC/s => 12 Gops)))
> 
> "The high end FPGA CPU is only ~150 MHz. But you can multiply instantiate
> them. I have an unfinished 16-bit design in 4x8 V-II CLBs that does about
> 167 MHz and includes a pipelined single-cycle multiply-accumulate. You can
> put 40 of them in a 2V1000 for a peak 16-bit computation rate (never to
> exceed) of 333 Mops * 40 = ~12 Gops. In a monster 2VP100 or 2VP125 you're
> looking at up to 10X that -- over 50 Gmacs (100 Gops). (Whether your problem
> can exploit that degree of parallelism, or whether the part can handle the
> power dissipation of such a design, I just don't know.)"
> 
> 
> The above design is not and will not be for sale.  But it (V-II-based
> parallel processor (chip or multi-chip mesh of same) consisting of
> tens/hundreds of 4x8 V-II-CLB 167 MHz pipelined 16-bit soft RISC+MAC tiles)
> seems perfectly feasible.  So where cost is no object, big FPGAs can hold
> their own in the 50 GMAC/s C-programmable parallel processor space.
> 
> I believe putting an austere 16-bit soft RISC in front of each of the
> tens/hundreds of multiplier+BRAM blocks can be an effective way to map many
> signal processing algorithms onto an FPGA fabric.
> 
> And where memory bandwidth or inter-node (inter-chip) interconnect is of
> concern, modern FPGAs can also hold their own, with fast DDR-DRAM
> interfacing and with a rich variety of high speed serial and parallel link
> options.
> 
> No doubt we will eventually see commercial FPGA-based massively parallel
> processor designs following in these footsteps.
> 
> Jan Gray, Gray Research LLC
> FPGA CPU News: www.fpgacpu.org

Article: 53361
Subject: Re: Cyclone power up problem
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 11 Mar 2003 14:39:30 -0800
Links: << >>  << T >>  << A >>
Jim,

We have also seen sensitivities at specific hot temperatures.

Unless you are willing to test every temp, on every part......very scarey.

In order to have a spec that results in 100% power on success, it takes a lot of
work.

We know.  Been there, done that.  Don't want to ever go there again.

Austin

Jim Granville wrote:

> Martin Schoeberl wrote:
> >
> > Hello Thorsten,
> >
> > > Xilinx provides a nice app note which describes you problem (Power on
> > surge)
> > > and gives an advices how to deal with it.
> > > Xilinx app notes 450 (Power-On requirements for the Spartan II and Spartan
> > > IIe famlies)
> > > and 451 (Power Assist circuits for the Spartan II and Spartan IIe
> > families)
> > >
> > Thanks for the information. These app notes describe the problem in detail.
> > Would be nice if these information is available for the Altera FPGAs.
> >
> > Just Power Assist circuits look for me like a little work around. I've found
> > a solution ('work around') for my board: Adding some 'charge' from the 3.3V
> > over two diodes to the 1.5V to help the drop-down regulator to start up.
> >
> > If there is interest in some oscilloscop pictures about the problem and an
> > equivilant circuit to test your power supply for Cyclone devices I can write
> > a summary on my web site.
>
> Good idea
> - also take some tests with it as cold as practical, as this effect
> worsens
> as temp drops.
>  With diodes you will need to watch for Vcc 'creep' above 1.5V
> at low Icc and low temp, and for insufficent feed-forward current,
> limited by the diode slope, and the 3.3V itself.
>
>  Suggestion for the IC vendors - Spice models for this effect anyone ?
>
> -jg


Article: 53362
Subject: Re: Are there any FPGA magazines/journals?
From: Joe <Joe@pacbell.net>
Date: Tue, 11 Mar 2003 23:48:21 GMT
Links: << >>  << T >>  << A >>
Thanks for all the fine replies ....

Joe wrote:

> ... Thanks in advance ...


Article: 53363
Subject: FPGA new problems.
From: javaguy11111@yahoo.com (db)
Date: 11 Mar 2003 16:45:17 -0800
Links: << >>  << T >>  << A >>
Not sure if this should go to comp.arch.fpga or comp.lang.verilog

I am new to working with Verilog and FPGA's. I recent bought a board
from Digilent. So far I have managed to do fairly simple things like
get leds to flash on the IO board when a button on the io board is
pressed.  I have also
been working through some online tutorials. I thought I was ready to
tackle getting the LCD display up an running. However I have run into
a complete brick wall.

I am trying to initialize the LCD display, which is several steps, but
I can not even get past the first step.
 
Basically I am running into an error saying 

WARNING:Xst:524 - All outputs of the instance <clockDiv> of the block
<ClockDiv> are unconnected in block <LCDMod>. This instance will be
removed from the design along with all underlying logic.

When I try to look at the schematic, there is nothing there.
Everything has been optimized away!

ClockDiv is just a divide by counter to step the clkIn from 50Mhz to
1Mhz.  intClk is being referenced. I am running into several other
issues, but maybe if I can understand why Xst thinks intClk is not
being used, I can understand the other problems. The Xilinx answer
database was of little help.

Is it my imagination or does Verilog in the tutorials bear little
resemblence to Verilog when applied to FPGA's?

Thanks in advance for any suggestions.

module LCDMod(clkIn,lcdReady,reset);
//Assuming clockDiv instance is 1Mhz
parameter wait20ms=20000;
parameter wait1ms=1000;
parameter wait37us=37;
parameter wait1p52ms=1520;	//Wait 1.52 milliseconds

input clkIn,reset;
output lcdReady;  //Will be true when lcd is ready to use
reg wait20msState,functionSetState;
reg [15:0] wait20msCounter;
reg lcdReadyBuffer;

wire intClk;   //I have tried this commented and not commented out.
               // Same problem
ClockDiv #(50) clockDiv (clkIn,intClk);

//Wait 20ms state
always @(posedge intClk or posedge reset)
begin
	if(reset) begin
		wait20msState=1;
		wait20msCounter=wait20ms;
	end
	else if(wait20msState) begin
		if(wait20msCounter==0)begin
			wait20msState=0;
			functionSetState=1;
		end
		else begin
			wait20msCounter=wait20msCounter-1;
		end
	end

end

//Function set state
always @(posedge intClk or posedge reset)
begin
	if(reset) begin
		functionSetState=0;
	end
	else begin
		functionSetState=1;
	end
end


endmodule

Article: 53364
Subject: Re: Prob. with data-input of SDRAM-Controller
From: "S. Ramirez" <sramirez@cfl.rr.com>
Date: Wed, 12 Mar 2003 01:46:33 GMT
Links: << >>  << T >>  << A >>
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3E6D4AF3.F30ACBA6@yahoo.com...
> You need to confirm the amount of delay in the data sheet for your
> SDRAM.  The delay depends on the speed grade of your chip and the clock
> speed you are running.  I recommend that you go to the web sites of
> several SDRAM manufacturers and find all the data sheets and app notes
> you can.  Several years ago I found a lot of info at Micron that helped
> me understand how this all works.  There are a lot of timing issues in
> these parts and it can be hard to make sure you meet them all.
>
> To add delay to your state machine just add one or two "dummy" states as
> needed before you latch the data.   Read State --> Dummy1 --> Dummy2 -->
> Latch Data...
>
> Rick "rickman" Collins


Rick,

While you're at it why don't you pick up a Verilog or VHDL model of the
SDRAM?  They give them away for free and they report errors and timing
violations big time!

Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA



Article: 53365
Subject: Re: best way to read/write contents of BRAM to a file during simulation?
From: wrighton@ieee.org (Michael Wrighton)
Date: 11 Mar 2003 17:57:54 -0800
Links: << >>  << T >>  << A >>
wrighton@ieee.org (Michael Wrighton) wrote in message news:<d2e340ce.0303071526.48c9c9b@posting.google.com>...
Following up on my own question. This may be helpful for someone (it's
probably not perfect yet, but this gives an easy debugging
interface/technique for memories). I'd appreciate any comments.


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;

-- Parameterized Block RAM
-- Provides DP Block RAM of Configurable Size via generics
-- Desirable to do via inferencing instead of coregen because this
results in a
-- more parameterized/portable design.

-- Setup allows for easy debugging:
-- From modelsim command line can do something like:
-- "force foo/bar/BlockRam/inputTrigger true"
-- And the RAM is loaded from a file.

-- Author: Michael Wrighton
-- Created: March 11, 2003

entity BlockRam is  
  generic (
    depth      : natural := 128;
    width      : natural := 16;
    addr_width : natural := 7;
    inputFile  : string := "inFile.hex";
    outputFile : string := "outFile.hex");

  port (
    clk : in std_logic;
    addra : in std_logic_vector(addr_width -1 downto 0);
    din : in std_logic_vector(width - 1 downto 0);
    wea : in std_logic;
    douta : out std_logic_vector(width - 1 downto 0);
    addrb : in std_logic_vector(addr_width - 1 downto 0);
    doutb : out std_logic_vector(width - 1 downto 0));
end BlockRam;

architecture rtl of BlockRam is


  type mem_type is array(depth - 1 downto 0) of std_logic_vector(width
- 1 downto 0);

  shared variable mem : mem_type;

  signal addra_clk, addrb_clk : std_logic_vector(addr_width - 1 downto
0);
  -- specify that this is block RAM
  attribute syn_ramstyle : string;
  attribute syn_ramstyle of mem : variable is "block_ram";

  -- synthesis translate_off
  signal inputTrigger, outputTrigger : boolean := false;
  -- synthesis translate_on
begin
  
  -- synthesis translate_off
  OUTPUTMEM:  process(outputTrigger)
    file outFile : text is out outputFile;
    variable data_line : line;
    variable datum : std_logic_vector(width - 1 downto 0);
  begin
    if outputTrigger then      
      for i in 0 to depth - 1 loop
        datum := mem(i);
        hwrite(data_line, datum);
        writeline(outFile, data_line);
      end loop;  -- i
    end if;
  end process;

  INPUTMEM: process(inputTrigger)
    file inFile : text is in inputFile;
    variable data_line : line;
    variable datum : std_logic_vector(width - 1 downto 0);
  begin
    if inputTrigger then
      for i in 0 to depth - 1 loop
        readline(inFile, data_line);
        hread(data_line, datum);
        mem(i) := datum;
      end loop;  -- i
    end if;
  end process;
  -- synthesis translate_on

  process(clk)
  begin
    if rising_edge(clk) then
      if (wea = '1') then
        mem(conv_integer(addra)) := din;
      end if;
      addra_clk <= addra;
      addrb_clk <= addrb;
    end if;
  end process;

  douta <= mem(conv_integer(addra_clk));
  doutb <= mem(conv_integer(addrb_clk));

  
end rtl;
library ieee;
use ieee.std_logic_1164.all;

entity BlockRam_tb is
end BlockRam_tb;

architecture testbench of BlockRam_tb is


  component BlockRam  
  generic (
    depth      : natural := 128;
    width      : natural := 16;
    addr_width : natural := 7);

  port (
    clk : in std_logic;
    addra : in std_logic_vector(addr_width -1 downto 0);
    din : in std_logic_vector(width - 1 downto 0);
    wea : in std_logic;
    douta : out std_logic_vector(width - 1 downto 0);
    addrb : in std_logic_vector(addr_width - 1 downto 0);
    doutb : out std_logic_vector(width - 1 downto 0));
    
  end component;

  constant addr_width : integer := 7;
  constant width : integer := 16;
  constant period : time := 10 ns;
  signal done : boolean := false;

  signal clk, wea : std_logic := '0';
  signal addra, addrb : std_logic_vector(addr_width - 1 downto 0);
  signal din, douta, doutb : std_logic_vector(width - 1 downto 0);
  

  
begin  -- testbench

  BR1: BlockRam
    port map (
      addra => addra,
      din   => din,
      wea   => wea,
      douta => douta,
      addrb => addrb,
      doutb => doutb,
      clk   => clk);
  
  CLKPROC: process
  begin
    clk <= not clk;
    wait for period / 2;
    if done then
      wait;        
    end if;
  end process;

  process
  begin
    wait for 200 ns;
    done <= true;
    wait;
  end process;
end testbench;


do file for modelsim

rm -rf work
vlib work
vcom -93 ../vhdl/BlockRam.vhd
vcom -93 ./BlockRam_tb.vhd
vsim BlockRam_tb
add wave clk
add wave BR1/mem
run 10ns
force BR1/inputTrigger true
run 40 ns
force BR1/outputTrigger true
run

Article: 53366
Subject: Re: Help understanding 7408 and gate chip
From: johnjakson@yahoo.com (john jakson)
Date: 11 Mar 2003 18:11:19 -0800
Links: << >>  << T >>  << A >>
nidar@rediffmail.com (Niranjandas) wrote in message news:<4f155288.0303111115.732d73f4@posting.google.com>...
> please find me if DM7408 chip
>  2 input Quad AND gate has ESD diodes(Elesctro static diodes).
>  if yes please let me know.
>  thank you.
> Nidar@rediffmail.com

Simple bipolar devices like glue logic would'nt need much protection
from ESD, its intrinsic to the device, no thin oxides to protect
right?. Later on VLSI bipolar did start to get the same type of hard
ESD protection as CMOS was getting when the features got to small to
wing it.

In fact TTL was so tough as old boots, there are Fairchild stories
that Chinese fabs used to make ripoff TTL in fabs where the air
conditioning was an open window.

By the way this is the wrong NG, and the wrong century.

Article: 53367
Subject: Re: Cyclone power up problem
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 12 Mar 2003 16:02:27 +1300
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> 
> Jim,
> 
> We have also seen sensitivities at specific hot temperatures.

By this I presume you are saying the I_StartMAX vs Temp curve is not
monotonic,
but can have one (or more?) peaks ?

> Unless you are willing to test every temp, on every part......very scarey.
> 
> In order to have a spec that results in 100% power on success, it takes a lot of
> work.
> 
> We know.  Been there, done that.  Don't want to ever go there again.

OK, so we take from this (and other comments) that the very-newest 
Xilinx devices have reduced the problem - but there are still 
design starts with older families. You may have the luxury 
of never going there again, field designers are not so lucky :)

So, I still believe models that allows designers to see the differences
in families, and get a handle on the numbers, is a good idea.
Yes, even for the very newest Xilinx devices.

Has anyone tried to model this ?

-jg

Article: 53368
Subject: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
From: "ntinsider" <ntinsider@yahoo.com>
Date: Wed, 12 Mar 2003 03:23:48 GMT
Links: << >>  << T >>  << A >>

All other things considered there is a possibility your chip is bad. I
work mainly with the Virtex series and in
the design process I have smoked input/output pins and I have had the
chip short to ground.

I thought I saw a response indicating that they thought you might need
more power to run the FPGA.
Going against common sense one night, when my power supplys current
light came on, I did just that
gave the system a little more current and boom!! a flaming cap shot out
the back.

I see that you indicated that you had lifted/disconnected every pin
except the PWR pin(aka VCC?) and I
imagine the ground is also still there. What I would do is take
resistence measurements with the FPGA
in circuit and out of circuit between its VCC and ground, no power
applied of course. The Virtex chip I had flamed
a cap with had a short between ground and VCC.

If you are lucky enough to have a spare Spartan you might want to
compare its vcc to gnd measurements with
the one on your board...Basically for your piece of mind I have seen
Xilinx chips short to ground before BUT for
the sake of Xilinx's QA reputation it is most likely due to the nature
of the system I am working on.

Hopefully this helps..

BJD


  "Padraig FitzGerald" <pfitzgerald@conwin.ie> wrote in message
news:ee7c445.-1@WebX.sUN8CHnE...
  Hi,
  I was wondering if anybody had come accross this problem when using
Xilinx FPGA's and if so do they know how to solve it.

  I have just recieved a PCB design back from FAB and We are having an
issue with a short between the VCC and GND planes. This however only
occurs when the Xilinx Spartan XL XCS30 is populated on the board, ie
the short is finding it's way through the silicon of the FPGA.

  Immediately I suspected an error on the footprint of the FPGA but it
was correct, then I thought maybe an IO pin which was externally pulled
up or down was shorted to the opposite level internal to the chip. Ijn
trying to determine this I lifted every pin except the PWR pins and the
short still occurs, so I can categorically say that the short is
iunternal betweent the two levels.

  My question is this.

  Is it possible that when an FPGA leaves the FAB it is configured in
this way? Perhaps for ESD protection??? Does anyone know how to overcome
this problem?

  Padraig



Article: 53369
Subject: unsupported switches of PAR
From: Utku Ozcan <utku.ozcan@netas.com.tr.spamela>
Date: Wed, 12 Mar 2003 10:58:44 +0200
Links: << >>  << T >>  << A >>

I'm using M3.1i SP8 IPv4 on Solaris 2.8.

I am trying to use MPPR using command line with -m option.
When I run the tool, in stdout following message comes out:

------------------
par -t 10 -ol 5 -w -m 0 -s 3 map.ncd m2.ncd m2.pcf
Release v3.3.08i - Par D.27
Copyright (c) 1995-2000 Xilinx, Inc.  All rights reserved.



Using unsupported HOGLOCK switch.

Constraints file: m2.pcf
------------------

The line "HOGLOCK" above is not in PAR report file, also
there is NO information in Xilinx site also NOT any info
around in web.

Anybody has seen the same?

Utku



Article: 53370
Subject: RESET --- Synchronous Vs Asynchronous
From: "LIJO" <lijo_eceNOSPAM@hotmail.com>
Date: Wed, 12 Mar 2003 14:56:26 +0530
Links: << >>  << T >>  << A >>
hi,
which reset is better synchronous or asynchronous

thanks
lijo




Article: 53371
Subject: DRC/ LVS
From: "LIJO" <lijo_eceNOSPAM@hotmail.com>
Date: Wed, 12 Mar 2003 15:04:36 +0530
Links: << >>  << T >>  << A >>
hi,
can anyone tell me
What is design Rule Check and Layout vs schematic

thanks
Lijo



Article: 53372
Subject: FPGA BitStream
From: Kostas <ksiop@ee.duth.gr>
Date: Wed, 12 Mar 2003 13:42:22 +0200
Links: << >>  << T >>  << A >>
Hi,

I use the T-VPack and VPR academic tools from Toronto University in 
order to make the placement and routing of simple designs. I have the 
problem that there is no bitstream tool available from this team.

I have found the JBITS from XILINX, that also use a modified version of 
VPACK and VPR. The problem is that tools from Xilinx supports Virtex 
FPGAs and not the FPGA architecture that supported by Toronto.

Has anyone any idea about how can i make the bitstream file ?

Thanks


Article: 53373
Subject: Re: Are there any FPGA magazines/journals?
From: "Stephen Melnikoff" <s.j.melnikoff@REMOVE-THIS-BIT.iee.org>
Date: Wed, 12 Mar 2003 11:45:49 -0000
Links: << >>  << T >>  << A >>
There's now also FPT (IEEE International Conference on Field-Programmable
Technology) at http://www.icfpt.org/.

Steve Melnikoff.

--
Steve Melnikoff - s.j.melnikoff@REMOVE-THIS-BIT.iee.org
Electronic, Electrical and Computer Engineering
University of Birmingham, Birmingham, UK



Article: 53374
(removed)




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