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Messages from 48825

Article: 48825
Subject: Re: Pin locking Virtex 2 FPGA
From: jhallen@world.std.com (Joseph H Allen)
Date: Fri, 25 Oct 2002 03:33:11 GMT
Links: << >>  << T >>  << A >>
In article <e8caa675.0210240939.389b197f@posting.google.com>,
M Schreiber <mschreiber75@yahoo.com> wrote:
>Hello,
>I am in the process of a new design.  The design is probably about 50%
>complete.  All of the interfaces are defined to and from the chip but
>the internal fpga logic is not completely defined.  Now I need to
>start the PCB design effort, and lock down some pins.

The most important thing is to run your selected pin locations through
the tool flow to check for hidden contraints.  If the logic is not done,
make up some simple fake logic which includes input and output flip flops
clocked with whatever clock is going to be used for your real design. 
Include all I/O standards.  Make sure that the tool puts IOB flip flops in
the IOBs (synthesis tools sometimes duplicate an input flip flop or route
the signal from an output flip flop to some other logic- either of these
will prevent the flip flop from being placed in the IOB).

There are many gotchas involved with routnig the clocks from the clock pins
to the DCMs.

Be very careful about the voltages requried for different I/O standards. 
The bank with the configuration pins requires 3.3V for VCCO.

I suggest that you when you assign the pins, keep fpga_editor open as a
reference. Adjacent pins on the package are not necessarily adjacent on the
die, so you need to check with fpga_editor.

The tool will sometimes lock resources together in pairs for placement- for
example some slice flip flops for bits 6 and 7 might always be placed as a
pair.  Thus if you have bit 6 on one side of your chip and bit 7 on the
other, the slice will be placed in the middle and you get very long routes
to each pin.

Duty cycle distortion of forwarded clocks (for example, for a ZBT RAM) is a
big issue, so make sure your clock output pin is close to the DCM which
generates the clock.  If you have to route a clock from one end of the chip
to a pin on the other end, it goes through 100 CMOS buffers and comes out
very distorted.  It is preferable to use a DDR mux to reproduce a forwarded
clock off of a global clock net, but this doesn't work for ZBT RAM clock
mirrors (since you don't want to waste a bufg for clock mirror).  There is
no conenction between a global clock net and a pin, so if you try to connect
them in HDL, you will get a general routing trace from the input of the BUFG
to the output pin (big delay, lots of distortion).

Locking down the pins is really a big job.  Plan on taking some time for it.

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Article: 48826
Subject: Re: LVDS standard
From: "Bob" <nimby1_not_spmmm@earthlink.net>
Date: Fri, 25 Oct 2002 03:34:42 GMT
Links: << >>  << T >>  << A >>

"Tom Burgess" <tom.burgess@nrc.ca> wrote in message
news:ap9ae3$97v$1@moonstone.imsb.nrc.ca...
> Bob wrote:
> <snipped>>
> > By the way, I believe that the latest software supports differential
DCI, so
> > LVDS inputs will be terminated right at the pads (if DCI is enabled).
> >
> > Bob
> >
> >
> Yes, for inputs only, I think. Saw this in answer record 15633 regarding
> 5.1 SP1. A bit of a power hog, though : "Note that internal  LVDS
> termination comes with a power-cost of 62.5mW per termination."
> Versus about a milliwatt for an external resistor. Let's see, 32
> inputs * 62.5 mW = 2 watts. Ouch.
>
> regards, Tom
>
>

Ouch is right! When I powered-up our first Virtex-II, with DCI on about 40
lines, I thought that something was wrong. After looking at the data sheet
carefully, and realizing how they really implemented the DCI, it explained
where all the heat was coming from.

I think from now on, I will only use DCI when the signal's frequency truly
warrants it (to minimize stub length), and when the signal count is low
enough.

Bob



Article: 48827
Subject: Re: LVDS standard
From: "Bob" <nimby1_not_spmmm@earthlink.net>
Date: Fri, 25 Oct 2002 03:40:06 GMT
Links: << >>  << T >>  << A >>

"Brijesh" <brijesh_spamNot@vt.edu> wrote in message
news:Zt0u9.7637$gA1.539846@news2.east.cox.net...
> I had question too.
> Can we mix LVTTL and LVDS buffers in the same bank?
> The documentation doesn't mention anything against it, but it doesn't
mention that it can be done also.
> I guess, since LVDS does not require Vref, we can mix LVTTL and LVDS,
right?
>
> Thanks
> Brijesh
>

You ought to read the Xilinx documentation carefully if you plan to use
Virtex-II. If you need a standard that requires VREF, then all VREF's in
that bank must be connected. That same bank may still be used for any other
type of I/O standard as long as it's compatible with that bank's VCCO.

Bob



Article: 48828
Subject: Re: Pin locking Virtex 2 FPGA
From: jhallen@world.std.com (Joseph H Allen)
Date: Fri, 25 Oct 2002 03:41:57 GMT
Links: << >>  << T >>  << A >>
In article <3DB87064.181FD533@andraka.com>,
Ray Andraka  <ray@andraka.com> wrote:

>Virtex2's bottle neck for speed is typically in the carry chains, which you
>are likely using in the counter/timer.  There, you'll want to register the
>inputs to the carry chain and place those registers immediately adjacent to
>the carry chain.  A 24 bit counter timer is going to put you right at the
>edge at 200 MHz in a -4 part.

I've seen the tools split a carry chain- you should definitely check for
this (oddly, the floorplanner doesn't let you do it).

Now for counters, carry chains are never really a problem.  You can always
make a pipelined counter: register the carry output from bit 11 and feed
that into a second coutner for the upper 12-bits.  The same goes for adders
if you can afford a pipeline stage.

I hate floorplanning, so I usually pipeline the sh*t out of everything. 
I've gotten 170+ MHz floorplanning free designs this way.

Context swapping is your friend: it is better to run 4 problems at once,
each taking four times the time than one problem in 1/4 the time.  The cost
is usually more buffering, which the FPGAs typically have lots of.  Use LUT
shift registers for local context buffers.
-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Article: 48829
Subject: C to verilog
From: "zhengyu" <zhengyu@attbi.com>
Date: Fri, 25 Oct 2002 04:11:34 GMT
Links: << >>  << T >>  << A >>
Hello,

 Does anyone know any reliable tools that convert C code into Verilog, VHDL
or some other format that can be mapped
into FPGAs very very quickly?

  OR maybe there are tools that compile C into FPGA directly.

Jimmy



Article: 48830
Subject: maxplus2 on WinXP
From: "scd" <scd@nospam.com>
Date: Fri, 25 Oct 2002 04:49:20 GMT
Links: << >>  << T >>  << A >>
Hi,

I just bought a new computer with Win XP on it.
I installed Maxplus2 10.2 and the compiler works
fine but the programming software can't find my
parallel port byteblaster.  Is there an XP driver that
needs to be installed in order for XP to recognize
the parallel port byteblaster?

Thanks,
Scott



Article: 48831
Subject: Please recommend a FPGA chip!
From: swda_ic@yahoo.com (sean da)
Date: 24 Oct 2002 21:54:35 -0700
Links: << >>  << T >>  << A >>
HI,

I am designing a low speed(less than 1MHz clock) digital signal
processing unit.

It comprise:
1)4K bit ROM
2)8*8 multiplier
3)2 12 bit accumulators
4)1K SRAM
5) 1 dozen registor and some control logic circuits.

Please recommend a right choice for the FPGA chips, which has the
right capacity and good price. I have a ISE 4.2 foundation package
from Xilinx, nor sure which series FPGA I should choose, X4000, X9000,
Vertex , Spartan ..., Other vendors product also are considered.

Appreciate!

Article: 48832
Subject: Re: maxplus2 on WinXP
From: Marcin E. Hamerla <mehamerla@pro.onet.pl>
Date: Fri, 25 Oct 2002 07:06:59 +0200
Links: << >>  << T >>  << A >>
scd napisal(a):

>I just bought a new computer with Win XP on it.
>I installed Maxplus2 10.2 and the compiler works
>fine but the programming software can't find my
>parallel port byteblaster.  Is there an XP driver that
>needs to be installed in order for XP to recognize
>the parallel port byteblaster?

Yes, there is a driver for win2000/xp that must be installed. There is
a note on Altera site describing instalation.

-- 
Pozdrowienia, Marcin E. Hamerla

"If we can put a man on the moon, we can build a computer made entirely 
of recycled paper"

Article: 48833
Subject: comp.cad.synthesis.
From: "Soul in Seoul" <Far@East.Design>
Date: Fri, 25 Oct 2002 13:58:09 +0800
Links: << >>  << T >>  << A >>
Hey, I want to check if the news group named comp.cad.synthesis still
running?

--
Xu Qijun
----------------------------------------------------
 Oki Techno Centre (Singapore) Pte Ltd
 20 Science Park Road #02-06/10, Teletech Park,
 Singapore Science Park II, 117674 Singapore.
 Tel: +65-6779-1621  Fax: +65-6779-2382
 DID: +65-6770-7081
 E-mail: qijun677@oki.com
 URL: www.okitechno.com
----------------------------------------------------
Friends may come and go, but enemies accumulate.



Article: 48834
Subject: Re: Who has some Lecture materialson I2C Bus?
From: "Soul in Seoul" <Far@East.Design>
Date: Fri, 25 Oct 2002 13:59:21 +0800
Links: << >>  << T >>  << A >>
yeah, the I2C manual is quite comprehensive. Thank you Geoffrey.


"Geoffrey Furman" <geoff_furman@iisvr.com> wrote in message
news:urfuloo96tc33c@corp.supernews.com...
> Philips started I2C bus and publish the spec as well as other app notes
>
>
>
> "Soul in Seoul" <Far@East.Design> wrote in message
> news:3db74e36@news.starhub.net.sg...
> > Hi,
> >
> > I went to yahoo for "Lecture I2C Bus" and it returned me a bunch of
french
> > websites.
> > Has anyone seen a good decent lecture notes on I2C bus?
> >
> > Thanks.
> >
> >
> >
>
>



Article: 48835
Subject: Re: Xilinx FPGA troubles
From: Roberto Waltman <rwaltman@verizon.net>
Date: Fri, 25 Oct 2002 02:00:33 -0400
Links: << >>  << T >>  << A >>
On 23 Oct 2002 02:00:57 GMT, Jens.Toerring@physik.fu-berlin.de wrote:
>Hi,
>
>  I guess this is a bit off-topic here, but I have no idea where else
>to ask and all google-searches didn't came up with anything useful
>until now....
>
>I'm trying to write or improve drivers for two cards that have a
>Xilinx FPGA, one card is an ISAPnP card, the other one is a PCI card.
>In both cases the Xilinx FPGA seems to be responsible for the ISAPnP/
>PCI functionality of the card and in both cases some binary "program"
>must be downloaded to the chip before it starts to work. My problem
>isn't so much the download of the data but that this download only
>works one time. Since one of the cards is in a machine I have no
>physical access to I can only be sure about the PCI card: when I
>try to do the download a second time I get errors (some bits
>indicating success won't get set). I have to switch off the machine
>completely and only then I can again do the download (just
>"shutdown -r now" won't do).
>
>Now my question is if anybody has some experience with these chips
>and knows if there is a way to figure out if it has already been
>initialized (in which case I simply could leave out the initiali-
>zation)? Or is there any source of information which I was too
>stupid to find?
>                                    Regards, Jens

The correct group for this post is comp.arch.fpga.  There are
many very knowledgeable people between "the regulars"
(Crossposting my answer there ....)

For more information see:
  http://www.andraka.com/whatisan.htm
  http://www.burched.biz/faq.html
  http://cardit.et.tudelft.nl/~heco/courses/et4-226/FPGA-tutorial.ps

Roberto Waltman


Article: 48836
Subject: Re: C to verilog
From: "glen herrmannsfeldt" <gah@ugcs.caltech.edu>
Date: Fri, 25 Oct 2002 06:04:06 GMT
Links: << >>  << T >>  << A >>

"zhengyu" <zhengyu@attbi.com> wrote in message
news:Wv3u9.90472$zE6.315596@rwcrnsc51.ops.asp.att.net...
>
>  Does anyone know any reliable tools that convert C code into Verilog,
VHDL
> or some other format that can be mapped
> into FPGAs very very quickly?
>
>   OR maybe there are tools that compile C into FPGA directly.

Why would you want to do that?  The only reason I can think of
would be to make a hardware implementation of an algorithm
already written in C.   The problem is, that good hardware
implementations of algorithms are very different than good
software implementations.

C code is executed, at least conceptually, one statement at
a time.  Structural model verilog, and presumably VHDL,
with the continuous assignment statement is designed so
that all statements are executed all the time.  There is no
easy, or even hard, way to map one into the other.

If that isn't what you want, then just write in verilog.  It
is enough C like to make C programmers happy.

-- glen



Article: 48837
Subject: Re: Please recommend a FPGA chip!
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Fri, 25 Oct 2002 06:09:45 GMT
Links: << >>  << T >>  << A >>
On 24 Oct 2002 21:54:35 -0700, swda_ic@yahoo.com (sean da) wrote:

>HI,
>
>I am designing a low speed(less than 1MHz clock) digital signal
>processing unit.
>
>It comprise:
>1)4K bit ROM
>2)8*8 multiplier
>3)2 12 bit accumulators
>4)1K SRAM
>5) 1 dozen registor and some control logic circuits.
>
>Please recommend a right choice for the FPGA chips, which has the
>right capacity and good price. I have a ISE 4.2 foundation package
>from Xilinx, nor sure which series FPGA I should choose, X4000, X9000,
>Vertex , Spartan ..., Other vendors product also are considered.

1MHz is very slow.  A software emulation of your function on a CPU may
be more cost effective than an FPGA.

Regards,
Allan.

Article: 48838
Subject: PCI burst reads w/ Spartan
From: "Rain One" <rainyfork@yahoo.com>
Date: Fri, 25 Oct 2002 06:21:06 GMT
Links: << >>  << T >>  << A >>
We have designed our own PCI core on a Spartan II.
However, we cannot get burst reads to work at all.
The computer is an pentium III and we use the Windriver tool.

Does anyone have a suggestion of how to make this work?

I think i read somewhere that the only way to do this is through a DMA.
is this true?



Article: 48839
Subject: Re: Xilinx FPGA troubles
From: "Giuseppeł" <gziggio.pleasedontsendmeanything@tin.it>
Date: Fri, 25 Oct 2002 08:21:27 +0200
Links: << >>  << T >>  << A >>
> >I'm trying to write or improve drivers for two cards that have a
> >Xilinx FPGA, one card is an ISAPnP card, the other one is a PCI card.
> >In both cases the Xilinx FPGA seems to be responsible for the ISAPnP/
> >PCI functionality of the card and in both cases some binary "program"
> >must be downloaded to the chip before it starts to work. My problem
> >isn't so much the download of the data but that this download only
> >works one time. Since one of the cards is in a machine I have no
> >physical access to I can only be sure about the PCI card: when I
> >try to do the download a second time I get errors (some bits
> >indicating success won't get set). I have to switch off the machine
> >completely and only then I can again do the download (just
> >"shutdown -r now" won't do).
> >                                    Regards, Jens
>

You have to update your ISE software at 5.1 service pack 1.
Before there is a bug in the Jtag software that not reset correctly the FPGA
before program it.

Another way is to use the slave serial mode. In this mode the PROGRAM pin is
used, so you can drive it low and high and reset copletely the FPGA.

If you use the Insight JTAG Cable model IJC-2 is possible that you can
improve your communication with the FPGA if you open the JTAG interface and
remove the C1 capacitor in the TDO line.
Then you can put a capacitor of 100pF nearest the TDO pin of the FPGA.

Regards
Giuseppe




Article: 48840
Subject: Just some newbie ISE questions...
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Fri, 25 Oct 2002 09:03:19 +0200
Links: << >>  << T >>  << A >>
Hi

I have just installed ISE 4.2i, after using Foundation previously, and so
quickly moving along the learning curve. I prefer to use the schematic
entry, and so in order to get familiar with the environment, started going
through the "in-depth" ISE tutorial (the watch tut!).

Right... now my question. In foundation, it was very easy to do a functional
simulation...just click, wave window pops up, and you could step through
clock cycles and change signals while you were at it. And you could easily
stick probes on to the schematic. Now, in the ISE tutorial, to simulate the
design I first need to create a testbench (and setup stimuli first), and
then double click Generate Expected Simulated Results. This calls up
ModelSim which does the simulation, and shows the results. My questions are
the following:

(a) I installed ModelSim with ISE, but do not have a license for ModelSim so
have to use starter license. When ModelSim was called for the watch tut, I
got a warning that the design was too big. Does this mean I am going to be
severely limited in simulations when I move onto bigger and better things?

(b) What, if there are any, the equivalents of the Functional Simulation and
Timing Simulation in Foundation?

(c) Is there another way to simulate my schematic in ISE without it using
ModelSim?

(d) It was never very apparent in Foundation, so I didn't really bother
about it, but upon completion of schematic design, does the system convert
this design into HDL before simulation?

Thanks

Adrian




Article: 48841
Subject: FPGA board recommendation
From: Michael Hosemann <hosemann@ifn.et.tu-dresden.de>
Date: Fri, 25 Oct 2002 09:42:36 +0200
Links: << >>  << T >>  << A >>
hello,

we are looking for a board with one or more FPGAs which will be used to 
implement a first version of a DSP chip we are currently designing. 

Since the chip will be fairly large in terms of gates and memory ( around 
2MBit), only the latest Xilinx Virtex II or Altera Stratix will do. 

We found a series of boards from avidda on the altera webpage. These boards 
have a PCI connection which would help us a lot getting the data on and off 
chip since we wouldnt have to build our own hardware around it

Does anybody already have experience with such boards, avidda and others?

All comments and sugestions are appreciated.

Michael Hosemann

Article: 48842
Subject: Re: LVDS standard
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 25 Oct 2002 07:46:11 -0000
Links: << >>  << T >>  << A >>
>I had question too.
>Can we mix LVTTL and LVDS buffers in the same bank?
>The documentation doesn't mention anything against it, but it doesn't mention that it can be done also.

There is a chart in the data sheet showing what VCCO and VREF
each IO standard needs.  Find that chart.  It's your friend when
you have problems like this.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 48843
Subject: Re: PCI burst reads w/ Spartan
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 25 Oct 2002 08:18:42 -0000
Links: << >>  << T >>  << A >>
>We have designed our own PCI core on a Spartan II.
>However, we cannot get burst reads to work at all.
>The computer is an pentium III and we use the Windriver tool.

>I think i read somewhere that the only way to do this is through a DMA.
>is this true?

[I don't know anything about the Windriver tool.]


Which direction are you trying to read?  CPU reading data from FPGA
or FPGA DMAing bits out of memory?

I think most/all Intel chip sets don't do burst reads from PCI to CPU.
I'd expect Alphas to do it.  Maybe not the really old ones.

You should be able to get DMA reads to work in bursts.  Put a logic
analyzer on your PCI bus and watch disk or ethernet traffic.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 48844
Subject: Re: FPGA board recommendation
From: "Paul Baxter" <pauljnospambaxter@hotnospammail.com>
Date: Fri, 25 Oct 2002 09:41:59 +0100
Links: << >>  << T >>  << A >>
I can personally recommend the boards from www.gidel.com

You can have up to 5 large stratix on their latest board.

Personally I avoided the ProcWizard and other software that you can buy but
if you do have a PCI solution then it comes with a PCI interface example
code (both VHDL and C++ for the OS) and lots of other stuff.

Board also includes DRAM etc

Paul
PS I used the Apex20KE board


"Michael Hosemann" <hosemann@ifn.et.tu-dresden.de> wrote in message
news:aparjd$nrl$1@rks1.urz.tu-dresden.de...
> hello,
>
> we are looking for a board with one or more FPGAs which will be used to
> implement a first version of a DSP chip we are currently designing.
>
> Since the chip will be fairly large in terms of gates and memory ( around
> 2MBit), only the latest Xilinx Virtex II or Altera Stratix will do.
>
> We found a series of boards from avidda on the altera webpage. These
boards
> have a PCI connection which would help us a lot getting the data on and
off
> chip since we wouldnt have to build our own hardware around it
>
> Does anybody already have experience with such boards, avidda and others?
>
> All comments and sugestions are appreciated.
>
> Michael Hosemann



Article: 48845
Subject: Re: Virtex2 Prototyping Board
From: Mike Rosing <rosing@neurophys.wisc.edu>
Date: Fri, 25 Oct 2002 03:57:24 -0500
Links: << >>  << T >>  << A >>
hiro wrote:
> Dear all,
> 
>  I am looking for an FPGA prototyping board with
>  the Virtex-II implemented.
>  My requirements for a board are blow.
> 
>    * it's not so expensive(hence smaller Virtex-II than XC2V250)
>       and to develop with ISE WebPack
>    * I can access as many usable FPGA I/Os as possible
>      via on-board pin headers(which have its space of 100mil) 
>    * I can select vcco voltage arbitrarily(especially for LVDS standard)
>    *A oscillator is installed which is in form of PLL or crystal
>     with socket mounted for various frequency generation. 
> 
>   Anyone who has any information please let me know.

I have a very low cost board from Avnet.  I use WebPack and
built my own JTAG interface card to program it with too (the
schematic is on Xilix web site).  It has an XC2V40, lots of
headers and a few other parts.  I've already blown away its
flash rom with my own code :-)

It seems like it should do everything you're asking, but check
Avnet's web site.  The part number is ADS-XLX-V2-EVL.

Patience, persistence, truth,
Dr. mike



-- 
Mike Rosing
www.beastrider.com                   BeastRider, LLC
SHARC debug tools


Article: 48846
Subject: Xilinx ISE 4.2i Student edition on Windows XP
From: "Michael Nicklas" <michaeln@nospam.slayer.com>
Date: Fri, 25 Oct 2002 10:00:06 +0100
Links: << >>  << T >>  << A >>
Hi

does anybody have any problems running Xilinx ISE 4.2i Student edition on
Windows XP.  It seemed to be going OK until I installed the most recent
service pack - downloaded from the Xilinx University Program website
www.xup.msu.edu/

Now it wont even open up.

--
Cheers!

Mike



Article: 48847
Subject: Re: PCI burst reads w/ Spartan
From: Steven Derrien <sderrien@irisa.fr>
Date: Fri, 25 Oct 2002 11:40:07 +0200
Links: << >>  << T >>  << A >>


Rain One wrote:
> 
> We have designed our own PCI core on a Spartan II.
> However, we cannot get burst reads to work at all.
> The computer is an pentium III and we use the Windriver tool.
> 
> Does anyone have a suggestion of how to make this work?
> 
> I think i read somewhere that the only way to do this is through a DMA.
> is this true?

On most x86 plat-form the chipset are not smart enough to detect burst 
sequences when doing mmap. The only way to observe burst is then to use
PCI devices bus-mastering capabilities (in other words DMA).

Have a look at the paper at 

http://citeseer.nj.nec.com/1690.html

Steven

Article: 48848
Subject: Re: C to verilog
From: "Alan Fitch" <alan.fitch@doulos.com>
Date: Fri, 25 Oct 2002 10:43:34 +0100
Links: << >>  << T >>  << A >>

"zhengyu" <zhengyu@attbi.com> wrote in message
news:Wv3u9.90472$zE6.315596@rwcrnsc51.ops.asp.att.net...
> Hello,
>
>  Does anyone know any reliable tools that convert C code into
Verilog, VHDL
> or some other format that can be mapped
> into FPGAs very very quickly?
>
>   OR maybe there are tools that compile C into FPGA directly.
>
> Jimmy
>
There are EDA tools based on SystemC (which of course is not quite
C!)
such as Synopsys Cocentric SystemC Compiler, and Forte Design
Systems
Cynthesiser.

Adelante Technologies see tools which process C and produce
VHDL or Verilog.

Celoxica sell a tool Handel-C which translates C and targets
FPGAs directly.

There are a couple of "free" tools as well. The only one I can
remember off hand is "Streams C" - look it up on Google.

kind regards

Alan

--
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[HDL Consultant]

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Article: 48849
Subject: Re: DLL and PLL in Xilinx and Altera
From: caliskan@uni-wuppertal.de (caliskan)
Date: 25 Oct 2002 03:00:27 -0700
Links: << >>  << T >>  << A >>
calyskan <caliskan@uni-wuppertal.de>wrote:
 How are PLLs with NCO for clock recovery implemented?



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