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Amen. "Arash Salarian" <arash.salarian@epfl.ch> wrote in message news:3da69af1$1@epflnews.epfl.ch... > "Dmitry Zarubin" <dmitry_zarubin@yahoo.com> wrote in message > news:93603cec.0210101918.775beda3@posting.google.com... > > There is an interesting discussion on Verilog vs VHDL going on on the > > comp.arch.verilog. > > > > Any comp.arch.fpga user group opinions about the above topic :) ? > > > > I am a big Verilog fun myself and did all my FPGA's in Verilog > > This is a type of question that, in my opinion, has no definitive answer. As > in the software world, selecting a programming language over another is not > a black/white decision. You find strong points in Both VHDL and Verilog that > is not present in the other one. For example, being a designer mostly > involved in DSP application in FPGAs, I tend to heavily use the mixture of > signed and unsigned calculations inside a module. For this type of > applications, so far, VHDL has been much simpler and synthesizers happily > accept such a code and produce decent results. But in Verilog, well, it's > not an easy task... > > But the good point here is that today, mixed language support is present in > both synthesize and simulation tools and this gives us a unique opportunity > to mix VHDL and Verilog code inside a single design, using each one of them > to find the most efficient way to describe each single module. > > Personally, yet I continue to use VHDL most of the time because of it's type > system that sometimes let's me to program in a "higher" level of abstraction > and also create beasts that would both simulate and synthesize very well. > Yet, in some occasions I use verilog to describe certain parts of my designs > as I find it easier to do it for those certain tasks easier. > > The moral of the story is, as a designer I feel free to use anything that > would help me do my job easier. If VHDL does it, then I use it. If Verilog > does it, then I use it. And I feel no obligation to keep my toolset the same > for all my designs.... use what you find best suit your application and > always be open to learn new things. > >Article: 48126
Hello. For my university degree I'm working on PCI digital oscilloscope card. I've got many problems with PCI core. Few days ago I wrote Configuration Block and after it passed OK all my Post Place&Route Simulation on 33MHz (in MXE5.5e) I've programmed Configuration Flash. I've plugged card into PC and run computer. Card was succesfully detected&configured by BIOS on Power On Self Test (memory addres assigned), and under DOS all Configuration Registers are correctly displayed. When I've run Windows, card was founded by OS as Early PCI non VGA device. I haven't wrote driver yet, thats why I skip further installation procedure.From thats moment there were many problems. Windows extremally slows down, PCI network adapter all time trying to connect to local network. When I start TV software (TV card on PCI) computer is hanging:( I don't understand the cause of problems. Card should be neutral for all PCI transaction except Configuration Read/Write whitch require signal IDSEL to change FSM State(and do sth on outs). I've off course add PCI_33_5 buffers to all PCI signals. I haven't experienced in programmable logic, it's my first project and I don't see cause of that problem. If You have some ideas, please help me. Thaks very much. Best regards. LeszekArticle: 48127
"C.W. THomas" <cwthomas@bittware.com> schrieb im Newsbeitrag news:uqdmese7uhhs93@corp.supernews.com... > dies the output of a register written in VHDL look like eg: > > > signal data_reg : std_logic_vector (3 downto 0); > > process blah... > > > begin > > if (clk'event and clk = '1') then > > data_reg <= "1010"; > > > > > what will the signal name for the input(s), output(s) , clock and enable(if > used) be? Signals directly driven by FlipFlops (so the output) are not renamed during synthesis. So is the clock, but this can get tricky, since some (all?) synthesis tools rename the clock signal because it is driven not directly by the clock input pin but by a (automatically inserted) clock buffer. For input signals and CEs Iam afraid you are lost, they are arbitrary named, mostly numbered. Best is, do a complete implementation, search the output signals, zoom into the CLB and there you find the names for data in and CE. Not really nice. Thats why a plain VHDL simulation is a VERY nice thing. -- MfG FalkArticle: 48128
Sorry of my English:)Article: 48129
C.W. THomas wrote:
> signal data_reg : std_logic_vector (3 downto 0);
> process blah...
> begin
> if (clk'event and clk = '1') then
> data_reg <= "1010";
>
> what will the signal name for the input(s), output(s) ,
That would be the port names in the entity section.
Might not be the same as the corresponding signals.
> clock
clk
> and enable
always enabled with that code.
-- Mike Treseler
Article: 48130
To get the initialized values to stick, I think the global resets have to use
the async resets, in which case reset has to be in the sensitivity list
process(clk,global_reset)
begin
if global_reset='1' then
set_ff<='1';
clr_ff<='0';
elsif rising_edge(clk) then
set_ff<= not_set_ff;
clr_ff<= not_clr_ff;
end if;
end process;
In order for this to stick, global_reset has to persist through synthesis. Use
of the ROC component will keep it there. set_ff will initialize as a '1' in
this case, while clr_ff initializes as '0'.
Ken Mac wrote:
> Ray,
>
> I don't instantiate flip-flops but I do infer a lot of them - how do I tell
> if the global reset sets an inferred flip-flop? Do I have to make this
> happen or is it inferred from a coding style?
>
> On the general topic of signal initialisation - I think my best option is to
> add a RESET signal to my entity and have a process something like this:
>
> SignalInit : process (CLK)
>
> begin
>
> if (rising_edge(CLK)) then
>
> if (RESET = '1') then
>
> signalblah <= '1';
> signalblah2 <= "1010";
>
> // etc
> end if;
>
> end if;
>
> end process;
>
> I think Synplify will warn me that RESET is not in the sensitivity list of
> the process but will it make any difference to the synthesis/mapping results
> if RESET is in the list or not?
>
> If the process is synchronous to the rising edge of CLK, why would it matter
> what RESET is doing if nothing happens unless there is a rising clock edge?
>
> Surely, all that ever need be in the sensitivity list is CLK for synchronous
> designs?
>
> Thanks for your time,
>
> Ken
>
> > You can indeed put an initialization on the flip-flops. Synplicity will
> > automatically put the attribute on the inferred flip-flop if the global
> reset
> > sets that flip-flop. If you instantiate flip-flops, the FDSE, FDS types
> will
> > default to initial 1, others to '0'. You can change that by adding an
> INIT=
> > attribute:
> > attribute INIT of FF0: label is "S"; to set, or
> > attribute INIT of FF0: label is "R"; to clear
> > these attach the appropriate attribute string tothe flip-flop primitive in
> the
> > edif file. To make simulation match the hardware, you also need to
> set/reset the
> > INIT generic to match.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48131Hi all, I am trying to develop a SRAM controller using Quartus 2.1 from Altera. The design contains a controller and also a Verilog file with SRAM model (which I need for simulation and other kinds of verifications). The question is: how to separate controller files from SRAM files in a design, so that Quartus doesn't put SRAM together with controller on a chip. Unfortunately, I was not able to achieve this so far. Any comments appreciated. ======================== Victor Ober TranstechArticle: 48132
Although there are some possibilities of why your PCI card is
crashing in Windows, my guess is that, your PCI IP core's sequencer
(FSM) doesn't have a bus busy state.
After an idle cycle, when FRAME# is asserted, yes, you do check AD[31:0]
for a BAR address match and check the command (For a Configuration
Cycle, it's AD[10:0] and IDSEL.), and very likely the assumption you are
making is that if there were no address matches, the PCI IP core can
just stay in an idle cycle, and wait for the next address phase.
However, in PCI, you cannot make that assumption.
According to PCI Specification Appendix B's state machine example,
FRAME# assertion is what starts an address phase.
However, FRAME# can also be kept asserted during a burst cycle and
during a single cycle in which the initiator is inserting wait states
(For the latter case, refer to PCI Local Bus Specification Revision 2.2
3.5.2. Master Data Latency.).
In your case, it is possible that when the Ethernet card or the TV Tuner
card is doing burst initiator (bus master) transfers, the content of
AD[31:0] and C/BE#[3:0] happens to match the BAR of your PCI
oscilloscope card, the command (C/BE#[3:0]) you are looking for, and
FRAME# also happened to be asserted because of a burst transfer.
When that happens, your card probably thinks that an address phase just
started, leading it to a crash.
My guess is that, when you developed your PCI IP core, you
probably didn't have access to PCI Local Bus Specification, therefore,
you didn't read Appendix B.
Appendix B gives you an example state machines (target and initiator),
and that's where it mentions about the bus busy state.
Neither PCI Hardware and Software (Annabooks, written by Ed Solari'.)
nor PCI System Architecture (Mindshare) gives you an example state
machines like the specification does.
In my opinion, I find the PCI Specification a lot more helpful than
those two books, although it doesn't hurt to have them anyway.
The PCI Specification is now up to 2.3, and costs $100 (It used to cost
$40 + shipping a year ago. Is PCISIG becoming financially desperate? Why
raise the price?).
Frankly, I am not sure why your PCI oscilloscope card, which is
doing nothing in Windows since you didn't write the driver for it, is
causing the computer to slow down.
One thing I will mention about a Configuration Cycle is that you
should be aware that a Configuration Cycle is not guaranteed to be
always a single (non-burst) transfer.
A burst Configuration Cycle is allowed by the specification, and in
fact, I am told that Intel 430FX chipset (Released sometime back in
1995.) does perform it.
If you don't want to deal with a burst Configuration Cycle (No one wants
to.), signal Disconnect with Data (DEVSEL# = 'L', TRDY# = 'L', and STOP#
= 'L') when accepting a Configuration Cycle.
Also, make sure you are correctly decoding AD[10:0] and IDSEL (You
already got IDSEL.) correctly when a Configuration Cycle starts to avoid
malfunction.
Since this is a course project, you probably shouldn't worry too
much about 33MHz PCI's timings (Tsu < 7ns, Tval (Tco) < 11ns, and Thold
<= 0ns).
About 14 months ago, I developed a PCI IP core, and tested it with
Insight Electronics' Spartan-II PCI card.
I got the card working perfectly two and a half weeks after I first
fired it up (The card didn't work perfectly the the first time because I
didn't do a post P&R simulation . . .), but the worst Tsu and Tval were
around 10ns and 15.5ns, respectively, but the card somehow worked fine
(The static timing analysis was done at 70 degrees Celsius, but the card
ran at room temperature.).
I personally don't advocate not meeting the PCI's timings, but since
this a course work, you should not waste too much time on dealing with
it.
After I got the PCI IP core working, it took me another 5 months (I
worked on it when I had some free time.) to get the timings right.
The trick was, after all, to use CE (Clock Enable) FFs for the AD[31:0]
output FFs, but it took me while to figure that out.
Xilinx LogiCORE PCI uses a secret (Some call it undocumented.) small
logic block called PCILOGIC that has dedicated connections to IOB output
FFs' CE input, but if you are dealing with 33MHz PCI, you really don't
need it (It's for 66MHz PCI which is hell . . .).
If you want to know more about PCILOGIC, do a newsgroup search of
news:comp.arch.fpga at Google about PCILOGIC, and I am sure you will
find more information about it.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
epson wrote:
>
> Hello.
> For my university degree I'm working on PCI digital oscilloscope card. I've
> got many problems with PCI core. Few days ago I wrote Configuration Block
> and after it passed OK all my Post Place&Route Simulation on 33MHz (in
> MXE5.5e) I've programmed Configuration Flash. I've plugged card into PC and
> run computer. Card was succesfully detected&configured by BIOS on Power On
> Self Test (memory addres assigned), and under DOS all Configuration
> Registers are correctly displayed. When I've run Windows, card was founded
> by OS as Early PCI non VGA device. I haven't wrote driver yet, thats why I
> skip further installation procedure.From thats moment there were many
> problems. Windows extremally slows down, PCI network adapter all time
> trying to connect to local network. When I start TV software (TV card on
> PCI) computer is hanging:( I don't understand the cause of problems. Card
> should be neutral for all PCI transaction except Configuration Read/Write
> whitch require signal IDSEL to change FSM State(and do sth on outs). I've
> off course add PCI_33_5 buffers to all PCI signals. I haven't experienced in
> programmable logic, it's my first project and I don't see cause of that
> problem. If You have some ideas, please help me.
> Thaks very much.
> Best regards.
> Leszek
Article: 48133A salesman has approached me with Active HDL 5.2. Some of the older Xilinx or Altera tools used Aldec and I thought it was pretty decent at the time, but didn't have much basis to judge. Does anyone have anything good or bad to say about these tools? They are supposed to good for any vendor - is that true? Any hidden problems, poor synthesis, etc,? Thanks, EdArticle: 48134
I'm still not sure how to update the weights.
I have a 100 input channels and each input channel has its
FIR(10taps).
If I implement FIR with one LUT I'll have a 100 LUTs. To update the
weights, I need to calculate the error so I need to sum all 100
outputs from 100 inputs and find the error by comparing with desired
signal.
(1)How to update all the weights(10 weights x 100 = 1000 weights)
t t t
- recall w (n+1)=w (n)+mu*e(n)*x(n)
k k k
k : input channel number, 1~100
t : tap number, 1~10
-Do I need the memory to save 1000 weights and 100 inputs?
-After updating the weights, how to update 100 LUTs?
To update each LUT, I need to calculate every possible partial
products, right? Then how to save to LUT? and I need to update another
99 LUTs, right?
(2) Am I on the right track to implement adaptive filter with many
input channels?
thanks for your kind advices..
Ray Andraka <ray@andraka.com> wrote in message news:<3DA1FD92.278C3EBC@andraka.com>...
> It also helps to take into account what else needs to be done in the device. A
> DSP, for example might handle the filter fine, but then add in perhaps a
> demodulator, the update mechanism and some other stuff, and now it may no longer
> fit on a DSP. For very low sample rates (eg, audio samples), it often is more
> advantageous to use a multiplier and block rams instead of attempting to do it
> with distributed arithmetic. For example, one can use a pair of block rams (one
> for coefficient store, one for sample delay) and a pair of accumulators (one
> connected as a scaling accumulator multiplier) to get a very effective FIR
> filter in a very small amount of chip resources. We do that for the audio
> filters at the back end of our FPGA shortwave radio demo.
>
> Falk Brunner wrote:
>
> > > implement FIR for one input channel, do I need to prepare another 99
> > > pairs LUTs and adders for 99 input channels FIR ?
> >
> > If you go this way, yes. But at such low sampling rates, its a good idea to
> > do some multiplexing, means runn your DSP core at a high clock rate and use
> > one MAC unit for multiple channels.
> >
> > > And how to update those LUTs after calculating the errors?
> >
> > There are many ways. You could use the LUTs a dual port distributed RAM. One
> > port is for updating the coefficients, one for read access by the DSP
> > engine.
> >
> > But again. Do a estimation on data throughput (sample rate, bit width of
> > samples), estimate the number of operations needed to recalculate the
> > coefficients, estimate the number of operations neede for the filter itself.
> > Then compare this to common available DSP. THEN it is time to think about
> > using a FPGA or DSP.
> > --
> > MfG
> > Falk
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
Article: 48135
First, Aldec is a design entry and simulation tool, not a synthesis tool so if
you get poor synthesis it is the fault of your synthesizer, not Aldec.
We use both Aldec and Modelsim. I much prefer the Aldec (we use Modelsim
because some of our customers ask for it). Aldec offers much more for your
money, including a first class design entry system, on-line help and tutorials
beyond compare, source control, some core generation, tool integration and much
more. I suggest you get the 20 day free trials of both Aldec and Modelsim and
compare. I think you'll find that you'll need most of the 20 days to getup to
speed with modelsim, where you'll only need a day or two for Aldec (the user
interface is that much better). Aldec's tech support is also much more
responsive than Modelsim's is, if you ever need it (especially if you utter the
magic words: "but it works correctly under modelsim"). I only know that from
earlier versions, I haven't had any troubles with the tools in the last few
releases.
"Ed Browne, Precision Electronic Solutions" wrote:
> A salesman has approached me with Active HDL 5.2. Some of the older Xilinx
> or Altera tools used Aldec and I thought it was pretty decent at the time,
> but didn't have much basis to judge. Does anyone have anything good or bad
> to say about these tools? They are supposed to good for any vendor - is
> that true? Any hidden problems, poor synthesis, etc,?
>
> Thanks,
> Ed
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48136"Ed Browne, Precision Electronic Solutions" <ed_b_pes@swbell.net> wrote in message news:5tFp9.4401$%P5.835760304@newssvr30.news.prodigy.com... > A salesman has approached me with Active HDL 5.2. Some of the older Xilinx > or Altera tools used Aldec and I thought it was pretty decent at the time, > but didn't have much basis to judge. Does anyone have anything good or bad > to say about these tools? They are supposed to good for any vendor - is > that true? Any hidden problems, poor synthesis, etc,? It might pay you to do a google search of the recent past as several people including myself have recently discussed this issue. In short I think its excellent and easy to use and speed wise on a par with Modelsim but with lots of additional useful HDL design tools. I use it integrated with Altera Quartus for PAR and Leonardo OEM for synthesis. I would say though that your own optimised synthesis /place&route process may be preferable since the integrated AHDL route does not allow all the same tweaks as if you do it yourself. Don't get me wrong, it does work, just not providing necessarily optimal speed or area results. (Results based on Leonardo in 5.1 SP3 - 5.2 will be on my desk next week to try.) The additional HDL entry tools are a welcome addition and I find block diagrams far easier to create than with Quartus. Bottom line is the simulator is as good as Modelsim (though not as 'industry-standard' as Modelsim), it has lots of other features including good project organisation, testbench generation and HDL entry and its well integrated as an application. Paul BaxterArticle: 48137
"Engineer" <victor1357@hotmail.com> wrote in message news:b041a362.0210111058.742f72e0@posting.google.com... > Hi all, > I am trying to develop a SRAM controller using Quartus 2.1 from > Altera. The design contains a controller and also a Verilog file with > SRAM model (which I need for simulation and other kinds of > verifications). > The question is: how to separate controller files from SRAM files in a > design, so that Quartus doesn't put SRAM together with controller on a > chip. > Unfortunately, I was not able to achieve this so far. > Any comments appreciated. > ======================== > Victor Ober > Transtech The big problem you'll probably run into is that Quartus is a synthesis-only simulator so quite often models of RAMs etc simply do not work in Quartus. What you're describing is having the main design synthesised and placed to provide a full timing-correct 'model of your device under test. A simulation testbench then models the connections of your DUT with the SRAM for simulation. Altera does provide a limited edition Modelsim license in the full version which CAN do this sort of thing. Personally I found ActiveHDL a far easier and comprehensive simulator but this unfortunately costs more money (similar to a purchase of the full Modelsim license) I really would recommend downloading the ActiveHDL trial (www.aldec.com) as it also has comprehensive help files explain just such a setup. Good luck Paul BaxterArticle: 48138
Ed Browne, Precision Electronic Solutions wrote: > A salesman has approached me with Active HDL 5.2. Some of the older Xilinx > or Altera tools used Aldec and I thought it was pretty decent at the time, > but didn't have much basis to judge. Does anyone have anything good or bad > to say about these tools? They are supposed to good for any vendor - is > that true? For a windows platform and a non-emacs user I would recommend aldec. A lower cost windows solution is oem-licensed modelsim. For functional vhdl simulation, the oem brand A or X doesn't matter. For gate simulation, the only difference is a library compilation. For an emacs user on a linux platform the aldec product is something completely different (riviera) while Mentor-licensed modelsim is exactly the same on either platform. -- Mike TreselerArticle: 48139
Hey new joke in town: Question: How can both Xilinx and Altera have the "worlds lowest cost FPGA" ? Answer: They come from different Worlds! Check it out! http://xilinx.com/ http://www.altera.com/corporate/news_room/releases/products/nr-cyclone.html? xy=whp1_cycpr SteveArticle: 48140
HI; What is the attribute to keep a component from being optimized away in ise 4.2?? thanks;Article: 48141
Hi Petter, > The Quartus II Linux edition GUI behaves rather odd (at least under > fvwm2). It will always stay on top of all other windows. There is no > way to raise other windows like xterms on top of Quartus. Even when > minimized it punches through all other windows on the desktop. Have > anybody else experienced this behavior? Quartus does the same thing under KWM and a bunch of others; you're not alone. There's a workaround though. The Quartus GUI was compiled using a Windows portability layer called MainWin. MainWin's startup code will try to autodetect the window manager. There is a limited number of window managers that MainWin can detect with 100% accuracy. If it detects one of those it will be meek as a lamb and comply with the current WM's instructions. If not, MainWin will try to do its own window handling, causing focus messages to be discarded etc. However, MainWin has an environment variable called MWWM that can be used indicate which WM is being used. There's a whole bunch of WMs supported, but to be concise, if you set this environment variable to ALLWM, the MainWin window handler should always comply with the current window manager, even though it has to make a few assumptions due to border size estimates etc (see http://www.mainsoft.com/kb_mainwin/kbmw0034.html). However, in the $QUARTUS/adm/qenv.csh file that is invoked by the $QUARTUS/bin/quartus script, this variable is always removed from the environment. Thus, what I suggest to get rid of your problem is to change the line in $QUARTUS/adm/qenv.csh that says unsetenv MWWM to say setenv MWWM ALLWM with me this works fine under RedHat 7.3. However, this will probably void your warranty ;-) Best regards, BenArticle: 48142
Hi Kevin, Thanks for the reply. I too am trying to develope a 33MHz PCI interface without a spec. Any insight is a great help. regards Dave "Kevin Brace" <kev3inbrac5eusen7et@ho9tmail.c1om> wrote in message news:ao77og$no1$1@newsreader.mailgate.org... > Although there are some possibilities of why your PCI card is > crashing in Windows, my guess is that, your PCI IP core's sequencer > (FSM) doesn't have a bus busy state. > After an idle cycle, when FRAME# is asserted, yes, you do check AD[31:0] > for a BAR address match and check the command (For a Configuration > Cycle, it's AD[10:0] and IDSEL.), and very likely the assumption you are > making is that if there were no address matches, the PCI IP core can > just stay in an idle cycle, and wait for the next address phase. > However, in PCI, you cannot make that assumption. > According to PCI Specification Appendix B's state machine example, > FRAME# assertion is what starts an address phase. > However, FRAME# can also be kept asserted during a burst cycle and > during a single cycle in which the initiator is inserting wait states > (For the latter case, refer to PCI Local Bus Specification Revision 2.2 > 3.5.2. Master Data Latency.). > In your case, it is possible that when the Ethernet card or the TV Tuner > card is doing burst initiator (bus master) transfers, the content of > AD[31:0] and C/BE#[3:0] happens to match the BAR of your PCI > oscilloscope card, the command (C/BE#[3:0]) you are looking for, and > FRAME# also happened to be asserted because of a burst transfer. > When that happens, your card probably thinks that an address phase just > started, leading it to a crash. > My guess is that, when you developed your PCI IP core, you > probably didn't have access to PCI Local Bus Specification, therefore, > you didn't read Appendix B. > Appendix B gives you an example state machines (target and initiator), > and that's where it mentions about the bus busy state. > Neither PCI Hardware and Software (Annabooks, written by Ed Solari'.) > nor PCI System Architecture (Mindshare) gives you an example state > machines like the specification does. > In my opinion, I find the PCI Specification a lot more helpful than > those two books, although it doesn't hurt to have them anyway. > The PCI Specification is now up to 2.3, and costs $100 (It used to cost > $40 + shipping a year ago. Is PCISIG becoming financially desperate? Why > raise the price?). > Frankly, I am not sure why your PCI oscilloscope card, which is > doing nothing in Windows since you didn't write the driver for it, is > causing the computer to slow down. > One thing I will mention about a Configuration Cycle is that you > should be aware that a Configuration Cycle is not guaranteed to be > always a single (non-burst) transfer. > A burst Configuration Cycle is allowed by the specification, and in > fact, I am told that Intel 430FX chipset (Released sometime back in > 1995.) does perform it. > If you don't want to deal with a burst Configuration Cycle (No one wants > to.), signal Disconnect with Data (DEVSEL# = 'L', TRDY# = 'L', and STOP# > = 'L') when accepting a Configuration Cycle. > Also, make sure you are correctly decoding AD[10:0] and IDSEL (You > already got IDSEL.) correctly when a Configuration Cycle starts to avoid > malfunction. > Since this is a course project, you probably shouldn't worry too > much about 33MHz PCI's timings (Tsu < 7ns, Tval (Tco) < 11ns, and Thold > <= 0ns). > About 14 months ago, I developed a PCI IP core, and tested it with > Insight Electronics' Spartan-II PCI card. > I got the card working perfectly two and a half weeks after I first > fired it up (The card didn't work perfectly the the first time because I > didn't do a post P&R simulation . . .), but the worst Tsu and Tval were > around 10ns and 15.5ns, respectively, but the card somehow worked fine > (The static timing analysis was done at 70 degrees Celsius, but the card > ran at room temperature.). > I personally don't advocate not meeting the PCI's timings, but since > this a course work, you should not waste too much time on dealing with > it. > After I got the PCI IP core working, it took me another 5 months (I > worked on it when I had some free time.) to get the timings right. > The trick was, after all, to use CE (Clock Enable) FFs for the AD[31:0] > output FFs, but it took me while to figure that out. > Xilinx LogiCORE PCI uses a secret (Some call it undocumented.) small > logic block called PCILOGIC that has dedicated connections to IOB output > FFs' CE input, but if you are dealing with 33MHz PCI, you really don't > need it (It's for 66MHz PCI which is hell . . .). > If you want to know more about PCILOGIC, do a newsgroup search of > news:comp.arch.fpga at Google about PCILOGIC, and I am sure you will > find more information about it. > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) > > > > epson wrote: > > > > Hello. > > For my university degree I'm working on PCI digital oscilloscope card. I've > > got many problems with PCI core. Few days ago I wrote Configuration Block > > and after it passed OK all my Post Place&Route Simulation on 33MHz (in > > MXE5.5e) I've programmed Configuration Flash. I've plugged card into PC and > > run computer. Card was succesfully detected&configured by BIOS on Power On > > Self Test (memory addres assigned), and under DOS all Configuration > > Registers are correctly displayed. When I've run Windows, card was founded > > by OS as Early PCI non VGA device. I haven't wrote driver yet, thats why I > > skip further installation procedure.From thats moment there were many > > problems. Windows extremally slows down, PCI network adapter all time > > trying to connect to local network. When I start TV software (TV card on > > PCI) computer is hanging:( I don't understand the cause of problems. Card > > should be neutral for all PCI transaction except Configuration Read/Write > > whitch require signal IDSEL to change FSM State(and do sth on outs). I've > > off course add PCI_33_5 buffers to all PCI signals. I haven't experienced in > > programmable logic, it's my first project and I don't see cause of that > > problem. If You have some ideas, please help me. > > Thaks very much. > > Best regards. > > LeszekArticle: 48143
"Arash Salarian" <arash.salarian@epfl.ch> wrote in message news:<3da1520e$1@epflnews.epfl.ch>... > hmmmm your method seems very interesting. Can you provide some source codes? > I find it difficult to follow the same path by just reading what you've > written here. You know, such tricky methods are much more difficult to > explain in plain English than C++ :) > > Regards > Arahs > I'm sorry because I have just discovered that all those programs were lost. But don't worry, this 'theory' that I have dubbed as SBFT for Single Bit Fourier Transform can be described as taking the half positive sine and cosine waves as "1", and the negative half as "0". If you know the Fourier Transform theory you will not take too much work to reinterpret it with all the consequences of being completelly digital. Someone has told to me it is a completlly new method, does anybody know if it is true? see you Narcís Nadal > "Narcís Nadal" <nnadal@terra.es> wrote in message > news:4f3703fe.0210051234.78737c59@posting.google.com... > > "Darryl Groom" <dgroom@continental-microwave.co.uk> wrote in message > news:<ee795d5.-1@WebX.sUN8CHnE>... > > > Has anyone tried to implement a tone detector based around a goertzel > algorithm filter. I am looking for an example in VHDL or schematic form as > we are experiencing difficulty in getting the System Generator software > working to be able to pull our Matlab/Simulink model into the Spartan-II > device we are currently using. > > > > Is the first time I heard about goertzel and had to do a search with > > the google. Its very interesting but if you want a very fast and easy > > way to detect DTMF tones or other frequencies perhaps I may help you. > > > > 5 years ago I began a project whith the slowest CPU I know, the ST6, > > and was decoding DTMF from the telephone line to detect the numbers > > typed from any phone of a house. Early becomes evident that the > > methods learned in the university was unusables for that CPU and I > > began investigating and simulating other ways. The solution came from > > taking the essence of the Fourier Transform. I conver all analog > > signal to digital without using the ST6'ADC, I feed an smith trigger > > whith the analog line for doing right edges, and then directly to an > > ST6 digital input. The Fourier resulting coefficients were stored in 8 > > counters, each one representing a frequency. The counters with greater > > values showed the frequencies received . > > > > I will try to explain it in my poor english, for detecting the tones > > we dont need to calculate the exact values of the coeficients but only > > the ones with greater values thus we can eliminate the final > > calculations, making the resulting coeficients of the Fourier > > Transform obtained multiplicating the right point of the sine and > > cosine waves and adding or substracting the resulting value to others > > obtained before. First at all I calculate this waves and put them in a > > constant binary table which contains a "1" if the wave was >0 volts in > > this point and a "0" if was <0 volts. The sum of values for making the > > coeficients was stored in up-down counters, I thing 2 for every > > frequency. > > > > You also need 2*n tables, been n the number of frequencies detected. > > You dont need to multiplicate anything because the tables and the > > input are 1 bit values, you only XOR the two values. Dont add the > > resulting value to the others because is 1 bit wide, store it in a > > counter. When the result was "1" I incremented the right counter, and > > when was "0" I decremented it, or incremented another one. Well, I > > dont remember exactly how it was but the simulations on BorladC++ > > showed a strong correlation between the input frequences and the value > > of the counters. I remember to simulate a lot and as more samples > > taken more correlation done and the other counters had very low > > values. > > > > It was incredible to put that in so slow CPU but it worked very well, > > if you dont belive it you can simulate with a C++ program. If you > > implement that in a FPGA I am sure the wasted recurses will be much > > lower than whith the Goertzel Algorithm filter,and once the > > simulations were done you can implement it in few hours, even in > > schematics because it only has any counters, rom tables and xor gates. > > Of course if you are interested I can give you more details and look > > for the simulations. > > > > Narcís NadalArticle: 48144
I personally didn't like ModelSim, either. I grooved with Synapticad Verilogger, and it was (relatively) cheap. For the SRAM model, substitute an equivalent megafunction which can be made w/ the megafunction wizard. Hmmm, then he should simulate with the megafunction, instead of the model, once that stage is reached. However, that's a bit more complicated. And hopefully the controller is not a model, too. ========================================= "Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message news:3da72d0e$0$1291$cc9e4d1f@news.dial.pipex.com... > > "Engineer" <victor1357@hotmail.com> wrote in message > news:b041a362.0210111058.742f72e0@posting.google.com... > > Hi all, > > I am trying to develop a SRAM controller using Quartus 2.1 from > > Altera. The design contains a controller and also a Verilog file with > > SRAM model (which I need for simulation and other kinds of > > verifications). > > The question is: how to separate controller files from SRAM files in a > > design, so that Quartus doesn't put SRAM together with controller on a > > chip. > > Unfortunately, I was not able to achieve this so far. > > Any comments appreciated. > > ======================== > > Victor Ober > > Transtech > > The big problem you'll probably run into is that Quartus is a synthesis-only > simulator so quite often models of RAMs etc simply do not work in Quartus. > > What you're describing is having the main design synthesised and placed to > provide a full timing-correct 'model of your device under test. A simulation > testbench then models the connections of your DUT with the SRAM for > simulation. > > Altera does provide a limited edition Modelsim license in the full version > which CAN do this sort of thing. Personally I found ActiveHDL a far easier > and comprehensive simulator but this unfortunately costs more money (similar > to a purchase of the full Modelsim license) > > I really would recommend downloading the ActiveHDL trial (www.aldec.com) as > it also has comprehensive help files explain just such a setup. > > Good luck > > Paul Baxter > >Article: 48145
So, if I understand you correctly, you want Quartus to see the results coming in from externally connected ram & you want that ram to be functional. It would seem that the contents of the Verilog SRAM model should behave as your SRam. Though I'm getting fairly good at verilog programming, I still have to learn how to use the simulation models. If you contacted Altera, you'll probably get the answer to do everything in verilog & use Leonardo Spectrum for simulation. My all in Quartus solution would be something like this: Make a second dummy Quartus project which emulates your SRAM using standard RAM_DQ. Create a symbol for that project. Now, in your main project's simulation block diagram, place the SRAM projects I have successfully done this for 8 megabit sram. It worked fine for functional simulation, but, in timing mode, everything messed up. Warning: If you use Quartus to compile your *.v files, changing from Q2.0 to Q2.1 can mess up a whole lot of things... My recent finds are: ---> if (adr[7:0] == 8'b1000xxxx') begin... The don't cares 'x' no longer work, and they don't work even with the '===' when they should, Quartus2.1 will simplify out this 'if' block to do nothing. ---> notadr[7:0] <= !adr[7:0]; This also used to work, now, it also does something funny. ____________ Brian Guralnick innerdimension@hotmail.com (514) 624-4003 "Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message news:3da72d0e$0$1291$cc9e4d1f@news.dial.pipex.com... > > "Engineer" <victor1357@hotmail.com> wrote in message > news:b041a362.0210111058.742f72e0@posting.google.com... > > Hi all, > > I am trying to develop a SRAM controller using Quartus 2.1 from > > Altera. The design contains a controller and also a Verilog file with > > SRAM model (which I need for simulation and other kinds of > > verifications). > > The question is: how to separate controller files from SRAM files in a > > design, so that Quartus doesn't put SRAM together with controller on a > > chip. > > Unfortunately, I was not able to achieve this so far. > > Any comments appreciated. > > ======================== > > Victor Ober > > Transtech > > The big problem you'll probably run into is that Quartus is a synthesis-only > simulator so quite often models of RAMs etc simply do not work in Quartus. > > What you're describing is having the main design synthesised and placed to > provide a full timing-correct 'model of your device under test. A simulation > testbench then models the connections of your DUT with the SRAM for > simulation. > > Altera does provide a limited edition Modelsim license in the full version > which CAN do this sort of thing. Personally I found ActiveHDL a far easier > and comprehensive simulator but this unfortunately costs more money (similar > to a purchase of the full Modelsim license) > > I really would recommend downloading the ActiveHDL trial (www.aldec.com) as > it also has comprehensive help files explain just such a setup. > > Good luck > > Paul Baxter > >Article: 48146
I'm not convinced that Verilog will let you use 'x' as a don't care. I do know that 'x' from a simulation result found on a wire is not a don't care, but an error (no signal driven, or contention) "Brian Guralnick" <innerdimension@videotron.ca> wrote in message news:KSKp9.9423$dE6.195978@weber.videotron.net... > So, if I understand you correctly, you want Quartus to see the results coming in from externally connected ram & you want that ram > to be functional. > > It would seem that the contents of the Verilog SRAM model should behave as your SRam. Though I'm getting fairly good at verilog > programming, I still have to learn how to use the simulation models. If you contacted Altera, you'll probably get the answer to do > everything in verilog & use Leonardo Spectrum for simulation. > > > My all in Quartus solution would be something like this: > > Make a second dummy Quartus project which emulates your SRAM using standard RAM_DQ. Create a symbol for that project. Now, in your > main project's simulation block diagram, place the SRAM projects > > I have successfully done this for 8 megabit sram. It worked fine for functional simulation, but, in timing mode, everything messed > up. > > > Warning: If you use Quartus to compile your *.v files, changing from Q2.0 to Q2.1 can mess up a whole lot of things... > My recent finds are: > ---> if (adr[7:0] == 8'b1000xxxx') begin... > The don't cares 'x' no longer work, and they don't work even with the '===' when they should, Quartus2.1 will simplify out this 'if' > block to do nothing. > ---> notadr[7:0] <= !adr[7:0]; > This also used to work, now, it also does something funny. > > ____________ > Brian Guralnick > innerdimension@hotmail.com > (514) 624-4003 > > > "Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message news:3da72d0e$0$1291$cc9e4d1f@news.dial.pipex.com... > > > > "Engineer" <victor1357@hotmail.com> wrote in message > > news:b041a362.0210111058.742f72e0@posting.google.com... > > > Hi all, > > > I am trying to develop a SRAM controller using Quartus 2.1 from > > > Altera. The design contains a controller and also a Verilog file with > > > SRAM model (which I need for simulation and other kinds of > > > verifications). > > > The question is: how to separate controller files from SRAM files in a > > > design, so that Quartus doesn't put SRAM together with controller on a > > > chip. > > > Unfortunately, I was not able to achieve this so far. > > > Any comments appreciated. > > > ======================== > > > Victor Ober > > > Transtech > > > > The big problem you'll probably run into is that Quartus is a synthesis-only > > simulator so quite often models of RAMs etc simply do not work in Quartus. > > > > What you're describing is having the main design synthesised and placed to > > provide a full timing-correct 'model of your device under test. A simulation > > testbench then models the connections of your DUT with the SRAM for > > simulation. > > > > Altera does provide a limited edition Modelsim license in the full version > > which CAN do this sort of thing. Personally I found ActiveHDL a far easier > > and comprehensive simulator but this unfortunately costs more money (similar > > to a purchase of the full Modelsim license) > > > > I really would recommend downloading the ActiveHDL trial (www.aldec.com) as > > it also has comprehensive help files explain just such a setup. > > > > Good luck > > > > Paul Baxter > > > > > >Article: 48147
The 'x' was a habit gained from the AHDL language. When I started with verilog a few months back, I figured it might work. In
Quartus2.0 and earlier, it did work. It was very handy in creating a bus decoder with different pages.
eg:
parameter adr_range = "16b'1x000000xxxxxxxx'";
OLD:
......
if (adr_in == adr_range) ena <= 1;
else ena <= 0;
......
new:
......
if ( (adr_in[15] == 1) && (adr_in[13:8] == 0) ) ena <= 1;
else ena <= 0;
......
The problem here is that I can not use the parameter, unless there is a proper way to do the compare within Verilog.
____________
Brian Guralnick
innerdimension@hotmail.com
(514) 624-4003
"Blackie Beard" <BlackBeard@FearlessImmortalWretch.com> wrote in message news:YbLp9.3453$qb.2015@nwrddc01.gnilink.net...
> I'm not convinced that Verilog will let you use 'x' as a don't care.
> I do know that 'x' from a simulation result found on a wire is not
> a don't care, but an error (no signal driven, or contention)
>
>
> "Brian Guralnick" <innerdimension@videotron.ca> wrote in message
> news:KSKp9.9423$dE6.195978@weber.videotron.net...
> > So, if I understand you correctly, you want Quartus to see the results
> coming in from externally connected ram & you want that ram
> > to be functional.
> >
> > It would seem that the contents of the Verilog SRAM model should behave as
> your SRam. Though I'm getting fairly good at verilog
> > programming, I still have to learn how to use the simulation models. If
> you contacted Altera, you'll probably get the answer to do
> > everything in verilog & use Leonardo Spectrum for simulation.
> >
> >
> > My all in Quartus solution would be something like this:
> >
> > Make a second dummy Quartus project which emulates your SRAM using
> standard RAM_DQ. Create a symbol for that project. Now, in your
> > main project's simulation block diagram, place the SRAM projects
> >
> > I have successfully done this for 8 megabit sram. It worked fine for
> functional simulation, but, in timing mode, everything messed
> > up.
> >
> >
> > Warning: If you use Quartus to compile your *.v files, changing from Q2.0
> to Q2.1 can mess up a whole lot of things...
> > My recent finds are:
> > ---> if (adr[7:0] == 8'b1000xxxx') begin...
> > The don't cares 'x' no longer work, and they don't work even with the
> '===' when they should, Quartus2.1 will simplify out this 'if'
> > block to do nothing.
> > ---> notadr[7:0] <= !adr[7:0];
> > This also used to work, now, it also does something funny.
> >
> > ____________
> > Brian Guralnick
> > innerdimension@hotmail.com
> > (514) 624-4003
> >
> >
> > "Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message
> news:3da72d0e$0$1291$cc9e4d1f@news.dial.pipex.com...
> > >
> > > "Engineer" <victor1357@hotmail.com> wrote in message
> > > news:b041a362.0210111058.742f72e0@posting.google.com...
> > > > Hi all,
> > > > I am trying to develop a SRAM controller using Quartus 2.1 from
> > > > Altera. The design contains a controller and also a Verilog file with
> > > > SRAM model (which I need for simulation and other kinds of
> > > > verifications).
> > > > The question is: how to separate controller files from SRAM files in a
> > > > design, so that Quartus doesn't put SRAM together with controller on a
> > > > chip.
> > > > Unfortunately, I was not able to achieve this so far.
> > > > Any comments appreciated.
> > > > ========================
> > > > Victor Ober
> > > > Transtech
> > >
> > > The big problem you'll probably run into is that Quartus is a
> synthesis-only
> > > simulator so quite often models of RAMs etc simply do not work in
> Quartus.
> > >
> > > What you're describing is having the main design synthesised and placed
> to
> > > provide a full timing-correct 'model of your device under test. A
> simulation
> > > testbench then models the connections of your DUT with the SRAM for
> > > simulation.
> > >
> > > Altera does provide a limited edition Modelsim license in the full
> version
> > > which CAN do this sort of thing. Personally I found ActiveHDL a far
> easier
> > > and comprehensive simulator but this unfortunately costs more money
> (similar
> > > to a purchase of the full Modelsim license)
> > >
> > > I really would recommend downloading the ActiveHDL trial (www.aldec.com)
> as
> > > it also has comprehensive help files explain just such a setup.
> > >
> > > Good luck
> > >
> > > Paul Baxter
> > >
> > >
> >
> >
>
>
Article: 48148FS: ByteBlaster cable - $45 email me damps800@yahoo.comArticle: 48149
Dunno. What I do is hook up reset. To -any- input pin. And you'll need to connect at least one output pin - tie it to an unused IOB. SH7 On Fri, 11 Oct 2002 17:49:34 -0400, "C.W. THomas" <cwthomas@bittware.com> wrote: > > > >HI; > > >What is the attribute to keep a component from being optimized away in ise >4.2?? > >thanks; >
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