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"Xu Qijun" <fly@high.com> schrieb im Newsbeitrag news:ank32f$vot$1@reader01.singnet.com.sg... > Yeah, to be honest I am a hobbyist. > I am not sure how I can make a good medium size FPGA on a twin layer PCB. Question is, WHAT do you like to do? Are you more interested in FPGA stuff, so the hardware is "just" a tool, or do you enjoy doing the PCB stuff too? For the first one, go and get a ready made board. They are cheap and good. For the later one, a two layer solution is not really difficult. Been there, done that. I packed a TQ144 Spartan-II onto a two layer board, no real problems. Also not with the PROM. Also hand soldering these stuff isnt that tricky as it may look. BUT this wont work with 20 mil traces, I used 8 mil traces (the smallest available from the PCB manufacturer). I did the schematics, layout and soldering, but the PCB was made by a professional company. Many offer this service on the net for reasonable prices. -- MfG FalkArticle: 47826
Jan Gray wrote > (*My* bookshelf, by the way, holds a Bell and Newell, and also a Siewiorek, > Bell, and Newell. Absolutely. I was referring to the unusual/inconvenient page width of Bell&Newell ;)Article: 47827
Just one more -- something I sent around a while back:
I keep finding that just about anything interesting in (serial) computer
architecture was first tried before 1970. Take hardware multithreading
(multiple PCs anyway) and 'bytewise simd' (partitionable subword ALUs).
Both are present in the 1956-era Lincoln TX-2:
"The result of all this activity has been a computer of rela-
tively large capability. In addition to incorporating high-
speed transistor circuits and a large magnetic core memory
array, the Lincoln TX-2 has two major and distinguishing de-
sign characteristics:
1. The structure of the arithmetic element can be
altered under program control. Each instruc-
tion specifies a particular form of machine in
which to operate, ranging from a full 36-bit
computer to four 9-bit computers with many
variations. Not only is such a scheme able to
make more efficient use of the memory in storing
data of various word lengths, but it also can
be expected to result in greater over-all machine
speed because of the increased parallelism of
operation.
Peak operating rates must then be referred to
particular configurations. For addition and
multiplication, these peak rates are given in
the following table:
PEAK OPERATING SPEEDS OF TX-2
Word Lengths Additions Multiplications
(in bits) per second per second
36 150,000 80,000
18 300,000 240,000
9 600,000 600,000
2. Instead of one instruction counter, the TX-2
has 32 such counters which are assigned
separately to different users of the computer,
who then compete for operating time from in-
struction to instruction. A special part of
the machine selects a particular user based
partly on a predetermined priority schedule
and partly on the current needs of that user.
This multiple-sequence operation, in which many
essentially independent instruction sequences
interrupt and interleave one another, is an
extension of the breakpoint operation found in
DYSEAC of the National Bureau of Standards.
The value of these features will have to be assessed during
the course of future machine operation. The features them-
selves are discussed in more detail in the following sections
of this report."
-- THE LINCOLN TX-2 COMPUTER DEVELOPMENT, Wesley A. Clark, (6M-4968,
pp.5-6),
presented at the WJCC, L.A, CA, 2/57.
See also:
http://groups.google.com/groups?selm=1993Apr21.142942.28679%40hubcap.clemson
.edu.
This is pretty neat too: http://wps.com/texts/EDVAC/index.html.
Article: 47828You mention you need 5V I/O. If you'd use an 84 pin MAX 7000 (Altera) or a 95108 (Xilinx) you might be interested in the boards we have for them at http://www.al-williams.com/pldhome.htm -- you might also enjoy the tutorials for WebPack, MAX II Plus, and Verilog that we have there. Yes, I know you want to make your own boards, but still might give you some ideas and the two chips mentioned are pretty large 5V CPLDs (a 7160S has 3200 gates and 160 flip flops @ 149MHz; A 95108 has 108 macrocells and a good number of gates too). Al Williams AWC http://www.al-williams.comArticle: 47829
Below is an example Web server application we did for the paper. It
provides an HTTP interface to a hypothetical zoned climate controller. The
final object code size including OS/Network stack/Program was 32K. CPU
processing for an HTTP request was about a second on a processor running at
5MHz.
--Scott
# write new zone data to the controller
proc update_zone {zone no assign} {
set pos [expr [string first "=" $assign] + 1]
set val [string range $assign $pos end]
write_reg [expr ($zone << 1) + $no - 2] $val
}
# read zone data and format into HTML
proc zonehtml {zone no} {
set data [read_reg [expr ($zone << 1) + $no - 2]]
set hour24 [expr ($data >> 10) & 31]
if {$hour24 > 12} {
set hour12 [expr $hour24 - 12]
} else {
set hour12 $hour24
}
set quarter [expr ($data >> 8) & 3]
set min [expr ($quarter << 4) - $quarter]
set temp [expr $data & 255]
if {$hour24 == 24 || $hour24 < 12} {
set ret [format "<TD>%d @ %d:%02d am</TD>" $temp $hour12 $min]
} else {
set ret [format "<TD>%d @ %d:%02d pm</TD>" $temp $hour12 $min]
}
return $ret
}
# process an incomming HTTP request
proc www_req {handle} {
set req [split [gets $handle] " ?+"]
set loc [lindex $req 1] # get file name part of URL
puts $handle "<HTML><BODY>"
switch $loc {
/current {
puts $handle "<TABLE border=5><TR><TD>Zone 1</TD><TD>Zone
2</TD></TR>"
set l [join [list "<TR>" [zonehtml 1 0] [zonehtml 2 0] "</TR>"]]
puts $handle $l
set l [join [list "<TR>" [zonehtml 1 1] [zonehtml 2 1] "</TR>"]]
puts $handle $l
puts $handle "</TABLE>"
}
/update {
update_zone 1 0 [lindex $req 2]
update_zone 1 1 [lindex $req 3]
update_zone 2 0 [lindex $req 4]
update_zone 2 1 [lindex $req 5]
puts $handle "Request completed."
}
}
puts $handle "</BODY></HTML>"
close $handle
}
# accept a new HTTP connection
proc accept {handle ip port} {
# create a callback to "www_req" whenever the new connection becomes
readable
fileevent $handle readable [mk_cmd www_req $handle]
}
proc main {} {
# initialize device driver
set fd [init_dev]
# start PPP server with IP address 192.158.0.25
ppp_attach $fd [list 192 168 0 25]
# create TCP server on port 80 (HTTP) with the callback procedure
"accept"
socket -server accept 80
while {1} {
update
}
}
"Jim Granville" <jim.granville@designtools.co.nz> wrote in message
news:3D9CA7AC.5F1F@designtools.co.nz...
> Scott Thibault wrote:
> >
> > Tcl interpreter uses a bytecode compiler internally to improve
performance.
> > That bytecode is not suitable for hardware implementation, however. We
> > designed a special bytecode for this purpose, and yes, the FPGA is like
a
> > virtual machine for this bytecode.
> >
> > --Scott
>
> Sounds interesting - Can you post a small example of the flows ?
> - something like tiny source code / intermediate sizes / final speed,
> and size of the Tcl engine itself.. ?
>
> Not everyone here will know Tcl in detail, but the general
> application of script handling within FPGA is usefull to get a handle
> on.
>
> - jg
Article: 47830"Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:ania26$ce1$1@agate.berkeley.edu... > In article <upolclncc0qr16@corp.supernews.com>, > Scott Thibault <thibault@gmvhdl.com> wrote: > > >Tcl is not so different from Scheme if you replace []'s with ()'s, but ... > > Actually, its a big difference due to scoping rules. Tcl's scope > semantics (dynamic scope) is a BUG, but a bug which arrises from its > original incarnation as string munging which meant that it couldn't > have proper closures. The default behavior is not dynamic scoping without explicit use of the uplevel or upvar commands. We do not support this in our compiler. > >there are a couple of advantages to using Tcl. First, memory is managed with > >reference counting, which is simple and predictable. > > Only because Tcl doesn't allow real structures & references. > Reference counting can't collect cyclic structures. Yes, and there is an important application space that does not need them, and can benefit from refrence counting. --ScottArticle: 47831
This is for an interlock system that we are trying to implement. It is possible to use two boards, but I would prefer just one board. I can reduce my I/O lines to 166 if you know of any other boards. "Tony Burch" <tony@burched.com.au> wrote in message news:3d998258$0$30862$afc38c87@news.optusnet.com.au... > Hi pbpc, > > Unfortunately I can't help you with > 200 I/O lines, > but there's a low cost board with 144 I/Os brought > out to headers (and 300K gates also:)) > http://www.burched.biz/b5x300.html > > I wonder if you could get away with the lower number > of I/Os, maybe by busing or serializing some > of your I/O? What is your application? Is it a router > of some kind? > > Best regards > Tony Burch > http://www.BurchED.biz > FPGA boards for System-On-Chip prototyping and education > * * 10% off the normal price of all products, sale now on * * > > "pbpc" <pbpc@yahoo.com> wrote in message > news:amqfm5$n0v$1@usenet.Stanford.EDU... > > Does anyone know of a xilinx prototype board which has over 200 IO lines > > brought out to headers for use. > > > > > >Article: 47832
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<anjpdk$f19hj$4@ID-84877.news.dfncis.de>... > <noone@aol.com> schrieb im Newsbeitrag > news:amtppucmeahlsaju3pagmh5r1hqi1v0ad0@4ax.com... > > I am configuring an EP1K30 with a microprocessor. I send all the > > bytes in the .RBF file, as instructed by their app note. The part > > comes out of configuration and goes into user mode BEFORE all the > > bytes are sent; specifically, after the first of the three FFs at the > > end of the file are sent. This causes a problem because the extra two > > writes upset the logic. > > > > The question is, are those last two FFs necessary? Forget asking > > I suppose the two 0xFF are dummy bytes. AFAIK its similar to Xilinx devices, > the FPGA need some (2..8??) additional clock cycles after all configuration > data is written to the FPGA to start the FPGA. During this start phase, > global reset and tristate lines are released. They should be dummy bytes. Only the first 0xFF is needed. Another option is to go to "Devices and Pin Options" and select "Enable User Supplied Start up Clock". Currently what is probably happening is that the clock you are using to send configuration data to the device is probably a lot slower than the internal oscilloscope. And since the user supplied clock option is off, the internal oscilloscope is being used for Start Up configuration.Article: 47833
Funny, about the same thing can be said for hardware DSP. Back then, you either
found a very hardware efficient way to do it, or you just didn't.
Jan Gray wrote:
> Just one more -- something I sent around a while back:
>
> I keep finding that just about anything interesting in (serial) computer
> architecture was first tried before 1970.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47834If memory serves its the theoretical speed of the longest combinational path in your logic from in pin to out pin. And just so you know, the estimated clock frequencies reported by Synplify can be VERY far from reality. The only way you know for sure to is to also run the place and route software for whatever FPGA you're really considering. Best regards Ensoul Chee <mpub@163.com> wrote in message news:<20020930223140.A1E5.MPUB@163.com>... > I am using synplify for a test. That is the log file of it. I am not > sure what does the System Line mean? Can any body give me a hand? > > Thanks in advance. > > Requested Estimated Requested Estimated Clock > Starting Clock Frequency Frequency Period Period Slack Type > ---------------------------------------------------------------------------------------------- > Clk 200.0 MHz 192.1 MHz 5.000 5.205 -0.205 inferred > System 200.0 MHz 816.3 MHz 5.000 1.225 3.775 system > ==============================================================================================Article: 47835
Holger Veit wrote: > Falk Brunner <Falk.Brunner@gmx.de> wrote: > > "Karl" <Far@East.Design> schrieb im Newsbeitrag > > news:3d9d3652@news.starhub.net.sg... > >> Is there any FPGA which has an PROM on it so that we can program with thie > >> PROM instead of > >> an external PROM which makes PCB difficult to do? CPLD is too small for an > >> application anyway. > > > > Actel has some. Lattice?? Other may have too. But whats the problem with a > > external PROM? They are available in tiny SO8 packages. And with serial > > configuration, just 4 lines go between the FPGA and the PROM. Hardly a PCB > > design issue. > > I don't understand this issue either. You have a PCB issue anyway with > FPGAs with some hundred I/O pins, or even a BGA package - almost no chance > to do with a two layer PCB. I have done a project using a 2-layer board, and a Xilinx XCS30-TQ144 FPGA. This is a small, 144-pin part, with .5mm lead pitch. THAT was the hard part, hand soldering in those chips! But, laying out the 2-layer board was not extremely hard. Yes, things got pretty tight around the FPGA, especially because I wanted a good power distribution and ground field for the multiple power and ground pins. JonArticle: 47836
For your amusement : Original Pacman hardware (including cpu) running in a single FPGA, with VHDL source code. www.fpgaarcade.com Site is a bit primitive at the moment MikeJArticle: 47837
Hi Ulises Hernandez, Thank you for your kindness. Just wait for my test result!:o) Wish you good mood!!! CisaArticle: 47838
We're building a function generator that uses a 24 bit Direct Digital Synthesis oscillator. It will fit into an FPGA with no problem, but I'd really like to shoehorn this thing into a PLD to avoid the need for a boot ROM chip and to keep the cost down. The Xilinx 9000 series PLD's I've tried won't do because of the requirement for a 24 bit adder. Anyone have any suggestions of other chips I should investigate for this? Thanks for the help - Peter -- Peter D. Hiscocks Department of Electrical and Computer Engineering Ryerson University, 350 Victoria Street, Toronto, Ontario, M5B 2K3, Canada Phone: (416) 979-5000 Ext 6109 Fax: (416) 979-5280 Email: phiscock@ee.ryerson.ca URL: http://www.ee.ryerson.ca/~phiscockArticle: 47839
"Hal Murray" <hmurray@suespammers.org> wrote in message news:upjioaku2e1le1@corp.supernews.com... > [suggest software] > > iam not looking for such a solution TCP/IP in hardware is it feasible > > Look at the source code for a TCP stack. It's a huge state machine. > Just take a page or two of code and try to convert that to hardware. > > I haven't seen any reports of doing TCP in hardware, but I could > easily have missed something. (But somebody would probably mention > it here.) > > As an example, consider just routing, a small part of the TCP/IP stack. > High end routers do some of the table lookup in hardware, but they > normally drop back to software for the hard/rare cases. One could always build a simple processor in the FPGA and then program that. You could even write a C compiler for it, and generate code from C source. Considering that many processors are microcoded, (not quite the same, but similar idea), the idea of doing TCP/IP in hardware doesn't make so much sense. -- glenArticle: 47840
Rudolf Usselmann wrote: > Understand first when a CMOS device "burns" power: Each time a > node changes level (from 0 to 1; or from 2 to 0). [There is lot > more but thats typically controlled by the technology vendor, > use a LOW-POWER library if you are doing an ASIC ...] > > From the coding aspect, there are two things you can do: > 1) Reduce the Clock speed > 2) Reduce overall toggle rate > ---------------------------------------------- > www.asics.ws - Solutions for your ASIC needs - Remember the power consumed per transition is proportional to the capacitance of the net. Minimizing the transitions of a FSM will rarely minimize the power. More often than not, a state encoding that gives good power and timing will also be a good encoding for power. (letting the synthesis tool pick the state encoding will almost always give a better encoding than a hand choosen encoding - I then hard code the encodings back into the rtl to make gate sims match and simplify ecos) -- Dr. Eric OlsonArticle: 47841
Ole wrote: > > Rudolf Usselmann wrote: > > Understand first when a CMOS device "burns" power: Each time a > > node changes level (from 0 to 1; or from 2 to 0). [There is lot > > more but thats typically controlled by the technology vendor, > > use a LOW-POWER library if you are doing an ASIC ...] > > > > From the coding aspect, there are two things you can do: > > 1) Reduce the Clock speed > > 2) Reduce overall toggle rate > > > ---------------------------------------------- > > www.asics.ws - Solutions for your ASIC needs - > > Remember the power consumed per transition is proportional to the > capacitance of the net. Minimizing the transitions of a FSM will > rarely minimize the power. More often than not, a state encoding > that gives good power and timing will also be a good encoding for > power. (letting the synthesis tool pick the state encoding will > almost always give a better encoding than a hand choosen encoding > - I then hard code the encodings back into the rtl to make gate sims > match and simplify ecos) > > -- > Dr. Eric Olson I don't agree with this. If the state encoding uses 6 bits, the average number of bits changing will be more than two most likely. In addition the number of LUTs used on each bit will be greater since the logic will be more complex. With one hot encoding the number of bits is larger, but each transition only changes two bits. And the logic feeding the bit is normally very simple using very few LUTs. Unless the state machine is some degenerate case that just does not map at all well to a one hot encoding, this should always produce a near optimal design for power consumption. In the cases where the natual state machine does not map well to one hot encoding (such as states with many input transitions) you can always use state splitting to reduce the complexity of any give state. Then your only degenerate FSM becomes one with nearly all states transitioning to nearly every other state. Not many FSMs of any size are constructed that way. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47842
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag news:3D9D7554.9FD02FC8@andraka.com... > A one-hot is pretty much minimal power for a decoded state machine. All the > bits in a state machine necessarily have to have an even number of transitions > in a complete cycle of the state machine. The one-hot puts both transitions in > adjacent states. We've used a shft register style state machine where '1's get > shifted in. Sort of like a sticky one-hot. While this reduces the number of > input terms to each flip-flop, it only postpones the 1 to 0 transition to the > end of the cycle. A grey coded machine is an encoded machine. It has fewer > transitions (one per state instead of two) and less flip-flops so its power is > less. Be aware that any gains in the state machine might be lost in the state > decode, especially if there are not many 'hidden' states. A grey coded machine > becomes difficult to design with many branches unless extra filler states are > added, since every loop in the state diagram must have an even number of states. > Hello Ray, I have read here a lot about the power savings in the area of the flipflops used in the state machine, but all have forgotten that there is a lot of logic around the state flipflops which also change its level. Normally there are lots of AND and OR gates feeding the state flipflops. Especially the gray coder could dissipate more power than the less changing flipflops will save. Have anybody really measured any numbers in a real circuit? Best Regards HelmutArticle: 47843
I sort of alluded to that. In an FPGA it is even more true, as the routes
also consume power. I like the shift register (bar graph) type machines
because they minimize the logic leading into each state since the next state
only needs an equation for set, not for reset. Unfortunately, they are a bit
more obtuse to code and the synthesizers generally don't have them as an option
style. They also are convenient for the SRL16 primitives.
Helmut Sennewald wrote:
> "Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag
> news:3D9D7554.9FD02FC8@andraka.com...
> > A one-hot is pretty much minimal power for a decoded state machine. All
> the
> > bits in a state machine necessarily have to have an even number of
> transitions
> > in a complete cycle of the state machine. The one-hot puts both
> transitions in
> > adjacent states. We've used a shft register style state machine where
> '1's get
> > shifted in. Sort of like a sticky one-hot. While this reduces the number
> of
> > input terms to each flip-flop, it only postpones the 1 to 0 transition to
> the
> > end of the cycle. A grey coded machine is an encoded machine. It has
> fewer
> > transitions (one per state instead of two) and less flip-flops so its
> power is
> > less. Be aware that any gains in the state machine might be lost in the
> state
> > decode, especially if there are not many 'hidden' states. A grey coded
> machine
> > becomes difficult to design with many branches unless extra filler states
> are
> > added, since every loop in the state diagram must have an even number of
> states.
> >
>
> Hello Ray,
> I have read here a lot about the power savings in the area of
> the flipflops used in the state machine, but all have forgotten
> that there is a lot of logic around the state flipflops which also
> change its level. Normally there are lots of AND and OR gates
> feeding the state flipflops. Especially the gray coder could
> dissipate more power than the less changing flipflops will save.
> Have anybody really measured any numbers in a real circuit?
>
> Best Regards
> Helmut
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47844hamish@cloud.net.au wrote in message news:<3d9adedd$0$30860$afc38c87@news.optusnet.com.au>... > Dan <hombecker1962@hotmail.com> wrote: > > I have a quick question. We are looking to get a new computer to > > simulate Virtex II pro (1 power pc processor). I was curious as to > > recommendations. I see they recommend 2-3 gigs of ram for this > > particular device. Does anyone out there know if Xilinx ISE 5.1 runs > > faster on dual processor SMP machines that are mainly dedicated to > > that task (i.o.w. does it use multiple threads)? If so do you suggest > > The tools themselves won't use multiple CPUs, but a second CPU is useful > for other stuff; screen updates, disk I/O, run TRCE/Floorplanner/etc while > routing (if you have enough RAM etc). Or Run VNC to connect while routing > (VNC is a bit of a CPU hog in my experience.) > > > P4 ? AMD XP+? I would think the large cache on the 2.8 GHz P4's would > > be a big advantage. Also RAMBUS is sort of expensive compared to DDR, > > is it worth the 2-3x increase in price ? We will probably go with 3 > > The best route machine I have is dual P-III 866 MHz with 2Gb of SDRAM, > so I can't really comment. Haven't tried AMD yet for routes but planning > to. > > By the way, from what I hear, Windows applications can't use more than > 2Gb anyway. If your route needs more, it will crash. So 3Gb of RAM might > not be worth it, unless you will run other memory-intensive tasks at the > same time as PAR. > > Hamish Hi I just wanted to say thanks for the advice, and to point out that with special hooks you can get windows 2000/XP to use up to 3 gigs of RAM but evidently there are some caveats to that, but it can be done as the Xilinx manual points that out (at least for 5.1i) Thanks.Article: 47845
Ole <olsonville@mindspring.com> wrote in message news:<YGun9.910$j17.76148949@newssvr13.news.prodigy.com>... > Rudolf Usselmann wrote: > > Understand first when a CMOS device "burns" power: Each time a > > node changes level (from 0 to 1; or from 2 to 0). [There is lot > > more but thats typically controlled by the technology vendor, > > use a LOW-POWER library if you are doing an ASIC ...] > > > > From the coding aspect, there are two things you can do: > > 1) Reduce the Clock speed > > 2) Reduce overall toggle rate > > > ---------------------------------------------- > > www.asics.ws - Solutions for your ASIC needs - > > Remember the power consumed per transition is proportional to the > capacitance of the net. Minimizing the transitions of a FSM will > rarely minimize the power. More often than not, a state encoding > that gives good power and timing will also be a good encoding for > power. (letting the synthesis tool pick the state encoding will > almost always give a better encoding than a hand choosen encoding > - I then hard code the encodings back into the rtl to make gate sims > match and simplify ecos) Well, Dr. Eric Olson, Dr. R. Usselmann disagrees with the second part of your statement :*). The optimal state encoding will depend on the usage of the FSM and many other factors.I'm not sure I agree with you that a tool can chose the best encoding for me either. Definitely not Synplify. Synopsys Design Compiler, hmm, I'd trust it more. Not sure how long you have been writing RTL, but my "gut feeling" enables me to chose the best encoding style 90% of the time. In any case, I have originally stated it all boils down to your toggle rate ! Best Regards, rudi ---------------------------------------------- www.asics.ws - Solutions for your ASIC needs -Article: 47846
Hi.
I have a xilinx virtex2 DCM with the following cofiguration:
// ---------- Verilog code start here
defparam DCM.DLL_FREQUENCY_MODE = "HIGH";
DCM DCM (.CLKFB (clk250),
.CLKIN (clkout),
.DSSEN (1'b0),
.PSCLK (lbclk), // non relevant to the question
.PSEN (psen), // non relevant to the question
.PSINCDEC (psincdec),// non relevant to the question
.RST (~rst),
.CLK0 (clk250_int),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLK90 (),
.CLKDV (clk125_int),
.CLKFX (),
.CLKFX180 (),
.LOCKED (locked), // non relevant to the question
.PSDONE (psdone), // non relevant to the question
.STATUS ()
);
BUFG bufg_clk250 (.I(clk250_int), .O(clk250));
BUFG bufg_clk125 (.I(clk125_int), .O(clk125));
always @ (posedge clk125) b <= a;
always @ (posedge clk250) c <= b;
// ---------- Verilog code end here
CLKDV is division by 2 of CLKIN.
Although I see that the DCM is clocked,
and although I have no alert from the trce timing report,
I fear that I have a race / skew between
the register that sample 'a' to 'b' by 'clk125'
and the register that sample 'b' to 'c' by 'clk250' .
Is there a possible race / skew in this configuration,
or am I insures that there is no skew between the clocks
because of the locked DCM ?
ThankK,
Nahum.
Article: 47847If the frequency isn't extreme (what is it?), I don't know why the 24 bit adder is a problem. Aside from a 24 bit phase accumulator, do you have other functionality in the desired chip? A phase-to-sine function isn't manageable in a CPLD. Are you driving an external memory to get the various "functions?" An 8-pin DIP is the simplest configuration ROM to deal with; 4 wires, power supplies, and the FPGA gives you what you need. Cost is always an issue - do you need many devices? For a single device, would it be worth the extra design time and compromises? An xc2s15 (smallest Spartan-II device) seems to be about $10us and the xc2s50e (smallest Spartan-IIE) is about $15us, both prices from Avnet distribution. Peter Hiscocks wrote: > We're building a function generator that uses a 24 bit Direct Digital > Synthesis oscillator. It will fit into an FPGA with no problem, but I'd > really like to shoehorn this thing into a PLD to avoid the need for a boot > ROM chip and to keep the cost down. > > The Xilinx 9000 series PLD's I've tried won't do because of the requirement > for a 24 bit adder. Anyone have any suggestions of other chips I should > investigate for this? > > Thanks for the help - > Peter > >Article: 47848
By its very nature, TCP/IP is not real time. Network can have delays, packets can get lost. I think TCP/IP lends itself better to a software implementation. Well, it's interesting if you can jam all the TCP logic in a sub 1000 k gates , do all the checksumming in one clock cycle, match IP's in a CAM, etc... ehehe "geeko" <jibin@ushustech.com> wrote in message news:<anb9gh$c55ul$1@ID-159027.news.dfncis.de>... > What are the chances of implementing a TCP/IP stack using VHDL anybody do > anything similar.Can the Spartan FPGA be used to hold the designArticle: 47849
I look forward to more answers from those closer to the problem, but the simple answer is there *could* be a problem depending on the quality of the clock supplied to your chip (input jitter) as well as the more manageable internal characteristics like clock net loading and logic placement. If b and c are in adjacent CLBs, the routing time could be extremely small and a skew due to external jitter and/or internal clock net skew could result in a metastable event. To be "completely" safe, you could resample within adjacent CLBs (for the tight cycle times - 500MHz effective, I believe) to transfer with a negedge clk250. always @ (posedge clk125) b <= a; always @ (negedge clk250) bx <= b; // each transfer is within always @ (posedge clk250) c <= bx; // half a clk250 period. If your data is only going one direction, a clean offset between clk125 and clk250 might be applied rather than using the .CLK0 port. If the data flow is bidirectional, that wouldn't work. There's also the alternative of using a 250MHz with a 125MHz clock enable rather than the separate net, but logic resource and power concerns might keep you from that solution. Nahum Barnea wrote: > Hi. > I have a xilinx virtex2 DCM with the following cofiguration: > > // ---------- Verilog code start here > defparam DCM.DLL_FREQUENCY_MODE = "HIGH"; > DCM DCM (.CLKFB (clk250), > .CLKIN (clkout), > .DSSEN (1'b0), > .PSCLK (lbclk), // non relevant to the question > .PSEN (psen), // non relevant to the question > .PSINCDEC (psincdec),// non relevant to the question > .RST (~rst), > .CLK0 (clk250_int), > .CLK180 (), > .CLK270 (), > .CLK2X (), > .CLK2X180 (), > .CLK90 (), > .CLKDV (clk125_int), > .CLKFX (), > .CLKFX180 (), > .LOCKED (locked), // non relevant to the question > .PSDONE (psdone), // non relevant to the question > .STATUS () > ); > > BUFG bufg_clk250 (.I(clk250_int), .O(clk250)); > BUFG bufg_clk125 (.I(clk125_int), .O(clk125)); > > always @ (posedge clk125) b <= a; > always @ (posedge clk250) c <= b; > // ---------- Verilog code end here > > CLKDV is division by 2 of CLKIN. > > Although I see that the DCM is clocked, > and although I have no alert from the trce timing report, > I fear that I have a race / skew between > the register that sample 'a' to 'b' by 'clk125' > and the register that sample 'b' to 'c' by 'clk250' . > > Is there a possible race / skew in this configuration, > or am I insures that there is no skew between the clocks > because of the locked DCM ? > > ThankK, > Nahum. >
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