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Bob W wrote > Why can't Xilinx Software be as good as Altera Software? I am not much of an expert on Altera stuff, but the X product seems to be up the industry standard :-) My biggest Xilinx gripe is that lots of their error messages are plainly generated by 'assert' failures, and nobody has taken the trouble to scan the source for the asserts and document them. Then tech support treat you as a nutcase when you report the error... Just in case someone from X is reading this thread.Article: 47976
Use an add-in parallel port card.Article: 47977
Do they have an app note or something? What are intermediate parts? We need to use the USB to transfer data back and forth between PC and FPGA, as well as download bitstream to the FPGA. To do this we hooked up the FTDI module to a Xilinx 95108 CPLD which distingquishes between the two types (data or configuration). If I get what you guys are saying you can hook up that FTDI module directly to the FPGA to boot it. Thanks, Tony "Jon Schneider" <jon@axisREmilMOVEton.ltd.uk> wrote in message news:memo.20021008222529.4573A@xxx.cix.co.uk... > In article <anus53$hkp3q$1@ID-92522.news.dfncis.de>, Jensniemann@gmx.de > (Jens Niemann) wrote: > > > is there somewhere a reference design or some information about > > booting a SRAM-based FPGA via a USB interface? > > The newer FTDI devices have a way of doing just this. > > http://www.ftdichip.com > > Jon >Article: 47978
Hi, I have come across a low-end portable MP3 player, which uses a parallel cable to load songs into the SmartMedia cards and the player's internal memory. Can anybody tell what are the steps involved in designing this MP3 player? What core expertise do I need to design this toy? -- Xu Qijun ---------------------------------------------------- Oki Techno Centre (Singapore) Pte Ltd 20 Science Park Road #02-06/10, Teletech Park, Singapore Science Park II, 117674 Singapore. Tel: +65-6779-1621 Fax: +65-6779-2382 DID: +65-6770-7081 E-mail: qijun677@oki.com URL: www.okitechno.com ----------------------------------------------------Article: 47979
On 8 Oct 2002 15:00:57 -0700, kevinbraceusenet@hotmail.com (Kevin Brace) wrote: >First of all, notice that I changed the title slightly. > > > While I agree that Quartus II's help system is better than >ISE's, Altera doesn't seem to have detailed manuals of their software >available for download unlike Xilinx. I failed to mention that I use Altera's MaxPlus software rathern than Quartus II. Sorry, I should have mentioned that in my original post > > >> The Xilinx toolset is a hodgepodge of command line tools with a lousy >> user interface on top of it. The tools don't talk to each other, the >> error handling is terrible and the help files are useless. An analogy >> comes to mind. I would compare the Altera software to a sports car and >> the Xilinx to a donkey. Both modes of transportation will get you >> where you want to go. The sports car has an enjoyable ride. The donkey >> gets you there eventually, but the ride stinks. >> > > > I use ISE's GUI flow rather than running tools from a batch >file, so what you are saying is not a issue to me at all. > I use ISE's GUI also. It really is more of a shell over a bunch of command lines tools rather than a real GUI. None of the tools can talk to each other. For example, in Maxplus when you get an error, you click on it and it takes you to the source file and shows you the location of the problem. ISE shows an error. If you click on that error, most of the time nothing happens. If it does show you something, it is usually in an intermediate file. For example, you have an error in the schematic and ISE shows you the VHDL file that it made from the schematic. It then points to a net with a Xilinx generated name. It is up to the user to hunt around in the schematic and find the problem. > > > I find Xilinx's error messages adequate for tracking down >problems. >I don't use Xilinx's schematic tool, so I don't really have any >comments about it. > I have gotten error messages from the Xilinx tools that even Xilinx tech support can't explain without putting me on hold while they ask around. > > > >> 6) Options have to be set within many different separate programs. To >> set some options you may have to click on the Synthesizer, than the >> Fitter, then the Program file generator. >> > > > I like the fact that ISE's built-in synthesis tool XST has far >more synthesis options supported than Altera's built-in synthesis tool >(Okay, I can also use LeonardoSpectrum-Altera, but when I tried to run >it through Quartus II's NativeLink feature, I was not able to set >synthesis options from Quartus II. If I wanted to tinker with >synthesis options, I had to run LS-Altera separately.). >Personally, I prefer that the options are broken up, and assigned to >different programs (NGDBUILD, MAP, PAR, etc.). > > > >> 7) Sometimes when you edit the pins assignments, save them in >> Chipview, and then try to recompile the design nothing happens. You >> have to remember that as long as Chipview is open, the Project >> Navigator will ignore you and not show any reason why. (Oh yeah, I >> have to close that program before it will respond). >> > > > I assign pin assignments through a UCF file, so what you >mentioned is not a issue. >Don't you also assign pin assignments through a CSF file in Quartus >II? > Chipview is just a quick and dirty editor that edits the UCF file. Even if you manually edit the UCF file by clicking on Edit UCF you end up with the same problem. > >> 9) I try to run the included ModelSim simulator. The ModelSim splash >> screen comes up but nothing happens. The program doesn't start. The >> Project Navigator shows no error. After much wasted time, I find that >> the license for the simulator is tied to the IP address of the >> computer it is used on. Since I was using a laptop, its IP address >> depends on where it is plugged in. So I need a license for each IP >> address my laptop uses. There was no error message (How about "Invalid >> License!") from Navigator or ModelSim. This is poor software >> integration. >> > > > I usually run ModelSim XE-Starter by itself, not through ISE. The same problem happens whether you start from the ISE or start it by itself. The splash screen starts up and the program terminates. Altera has its simulator integrated into the program. If there is an error (even a licensing issue, it tells you. You then click on the error and it takes you to the source of the problem. > > > >> There are just a few examples of the types of problems that users have >> to live with. The Xilinx software is certainly usable and I have done >> many designs with it. It just makes things much harder than they >> should be. As a consultant, I appreciate well written tools save me >> time and my clients money. The Xilinx tools are poorly written and >> integrated. It has been like this for years. The new release (5.1) is >> not much better. Maybe if you have the major market share like Xilinx >> does, you don't have to care about the developers. Many Xilinx users >> have never tried the Altera software and don't know what they are >> missing. >> > > > Here are my complaints of Quartus II. Again, I use Altera MaxPlus so I can't comment on Quartus's shortcomings. > >1) When running Quartus II on a Windows 98 PC, it drains System >Resources rapidly that, I often have hard times running it along with >another program (i.e., Internet browser). >When the System Resources drain gets so bad, I often have to exit >Quartus II, and restart it again, which is irritating. >This problem doesn't happen with ISE, and ISE keeps the System >Resources usage to a minimum (10% to 15% at the most.), so I don't >have to restart it so many times. >Sure, I can get Windows 2000 or XP, but I personally pay anymore OS >tax to Microsoft (I am sure switching to Windows 2000 or XP will >improve my productivity because the OS will crash less often . . . ). > I just ran ISE 5.1 to get a fit for a design. Because it could not route (even though I was only using about 55% of the resources), I set it to run in "Exhastive Fit" mode where it keeps trying to get a fit. After running for 2 hours and not finding a fit, it stopped because it had used all of Windows virtual memory. This is on a Windows 2K system with with 512 Mb of RAM. The program obviously has a memory leak where it eats memory on every fit attempt. > > >5) While Xilinx's floorplanner isn't perfect, it still works far >better than Altera's. In Altera floorplanner, I cannot easily see >whether or not a LUT or FF of a LE is utilized. In Xilinx's one, I can >see visually whether or not a FF or a LUT within a CLB is utilized. > Where is Xilinx's floorplanner for CPLD designs? The Altera tools work accross PLD's, CPLDs, FPGA's with the same consistant toolset. > > >8) Altera doesn't offer a low level tool like FPGA Editor in Quartus >II. Because of that, users cannot see how the fitter routed the chip. > MaxPlus has a floorplanner that shows routing. > > > >> The Altera tools have a consistent interface and were written to run >> in a Windows environment. They have an intuitive feel. The utilities >> are so well written that you never leave the main program to run > them. > >Article: 47980
Hello, I working a design with some small counters in a design operating at 50 MHz. They are at most 4 bits. Some 2. Some operate only at 10 MHz. The counters are written in my design in a behavioral style, and the signals used for counting are integers, and never leave the chip. This has been my style for a long time (years) and I have never worried about it, and never had a problem. I always declare the range of the integers used, so no wild 32 bit counters get inferred. I have been advised from both Apps engineers at Synplicity and Memec Design Services that this is not an issue, that the tools will infer a binary counter and be efficient about it. Another engineer says this is a bad idea, and that I should use only std_logic_vector for these simple counters. I have yet to try implementing the design differently and look at the RTL that Synplify generates, but will do tomorrow. Any thoughts? ClydeArticle: 47981
On Tue, 08 Oct 2002 18:31:38 GMT, Bob W <fa@_NO_SPAM_AskTheOracle.com> wrote: >Why can’t Xilinx Software be as good as Altera Software? > P.S. I failed to mention that I am using (and comparing) the Altera MaxPlus II software to the Xilinx ISE. Interesting discussion going on this topic.Article: 47982
On Tue, 08 Oct 2002 17:04:53 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >Bob W wrote: >> >> Why can’t Xilinx Software be as good as Altera Software? > >Interesting discussion and I am surprised at some of the responses. I >had a 6 month adventure with Altera MAX Plus and based on that I am >surprised that anyone would ever use an Altera tool if they could avoid >it. We were adding new features to an existing design in a 10K100A part >on a board that had many units in the field. When we tried to implement >a design that used 90% of the resources, the software could not handle >the job. Even when we reduced the logic to 80% it would not route and >meet timing. I have had a different experience with MaxPlus.I have used the MaxPlus on many 10K50 designs. I have been able to fit with high utilizations (up top 90%) . The simulator showed me results that agreed with my logic analyzer and the scope on the final product. I have a Xilinx design in a Coolrunner CPLD. It is only using 55% of the resouces. However, I find that adding or deleting a few gates causes the design to fail on routing. Then if have to try rearranging the design until I can get a fit. I took the fitted design, done in ISE 4.2 and converted it to the new ISE 5.1 and it wouldn't fit. I put the fitter into "Exhaustive fit" mode. This is supposed to try all of the combinations of fitter parameters in a sequential fashion to determine the best fit. I let it run for 2 hours and it crashed when it finally consumed all of virtual memory on a Win2K 512Mb system. There must be a memory leak through each iteration of the fitter. >I can't say that the Xilinx tools are perfect. But when you do tough >designs I find it a lot easier to see what is going on with the P&R and >to find ways to deal with any problems. The pushbutton Altera approach >seems to get in the way of seeing what is actually happening under the >hood of your design.Article: 47983
You know something? When you already know exactly how you want the hardware, why use synthesys at all? It just wastes your time. Just create the gate level netlist you want. Of course other parts of your design might be better off with synthesys - it's not all-or-nothing, y'know, and the simulators mix gates and RTL pretty well! -StanArticle: 47984
Sorry, forgot to say... This is a VHDL design.... CRS "Clyde R. Shappee" wrote: > Hello, > > I working a design with some small counters in a design operating at 50 > MHz. They are at most 4 bits. Some 2. Some operate only at 10 MHz. > > The counters are written in my design in a behavioral style, and the > signals used for counting are integers, and never leave the chip. This > has been my style for a long time (years) and I have never worried about > it, and never had a problem. I always declare the range of the integers > used, so no wild 32 bit counters get inferred. > > I have been advised from both Apps engineers at Synplicity and Memec > Design Services that this is not an issue, that the tools will infer a > binary counter and be efficient about it. > > Another engineer says this is a bad idea, and that I should use only > std_logic_vector for these simple counters. > > I have yet to try implementing the design differently and look at the > RTL that Synplify generates, but will do tomorrow. > > Any thoughts? > > ClydeArticle: 47985
On Tue, 08 Oct 2002 22:20:39 +0200, Rene Tschaggelar <tschaggelar@dplanet.ch> wrote: >To me, the ease of use is paramount. I may not have a look at >that stuff for months, and then have to do a project >immediately. I cannot read manuals to become comfortable again. >It has to be sufficiently intuitive to be used. > >Rene I agree totally. As a consultant I might not touch the tools for a year while I am working on other projects. The Altera tools are easy to pick up again. The Xilinx tools are a pain.Article: 47986
On Wed, 9 Oct 2002 00:55:03 +0100, "Tim" <tim@rockylogic.com.nooospam.com> wrote: be up the industry standard :-) > >My biggest Xilinx gripe is that lots of their error messages are >plainly generated by 'assert' failures, and nobody has taken >the trouble to scan the source for the asserts and document >them. Then tech support treat you as a nutcase when you report >the error... > I was at a design seminar for the Xilinx MicroBlaze embedded processor. Some asked what all of those warning messages are that are scrolling through the screen. The instructor says, "Oh those are the normal Xilinx warnings. Just ignore them". How come it generates so many warnings even when its working?Article: 47987
On Tue, 8 Oct 2002 19:26:48 +0000 (UTC), "Ken Mac" <aeu96186@yahoo.co.uk> wrote: > >Bob, > ><snip> > >I am a Xilinx user and I haven't tried Altera software (due to the fact that >I only have Xilinx devices!). > >Why do you think Xilinx does have the major market share? > I think they make good chips (as does Altera). I think Xilinx has better marketing. Most developers have only used one toolset or the other, not both. People want to stick with the first tools they learn. >If hardware implementations on FPGA continue to start being developed from a >software perspective (Handel-C, System-C etc.), do you think Xilinx will >retain their dominance given that software developers (who will apparently >eventually being writing software that ends up directly on hardware (!) >-) ) are used to advanced, slick GUIs such as Microsoft Visual Studio etc.? >Won't they prefer Alteras software then and if designs can be done on either >Xilinx or Altera - why not choose the tool they feel most comfortable with? > I think that C level design will be the wave of the future for some types of designs. As gates become cheap and speeds get faster, it is easier to fit a C type design into silicon. Who cares how efficent it is if it meets timing? There will always be some designs that require the most efficient design and these will be harder to achieve in C. It analagous to the Assembly language versus C code argument in software. Most of the time C does the trick. Here and there Assembly is a necessity . >Or will hardware advantages still be the most important factor? > My experience is that the hardware designers are not always the ones who actually write the FPGA code. The hardware designer doesn't necessarily know (or care) how good the development tools are.Article: 47988
In article <3DA38D4E.401FA979@world.std.com>, Clyde R. Shappee <clydes@world.std.com> wrote: >Sorry, forgot to say... > >This is a VHDL design.... Your performance targets are SO low compared to counter size, do what you want. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 47989
Theron, If you go the external route, you might look at Philips Semiconductors. I think they've got one with a PCI interface but I have no idea on price or availability. Just giving yet another vendor choice. Jerry Theron Hicks wrote: > "Ray Andraka" <ray@andraka.com> wrote in message > news:3DA21E5F.8DD5ED3@andraka.com... > >>A while back we considered USB in the FPGA, but when push came to shove, >> > it was > >>cheaper to use an external USB chip. In our case, it was the original >> > USB, and > >>we used a National Semi chip, I think it was a USBN9603 which has both the >>controller and the PHY in one package for about $2.25. When we sized the >> > USB > >>for putting in the FPGA we still needed an external PHY, and it would have >>pushed us into a larger part costing far more than the off the shelf chip. >> > I > >>don't know if the situation is similar for USB2 or not, although I suspect >> > that > >>it is. >> >> > Ray, > I am beginning to think along the same lines. The chips are about the > same price ($2 to $3 or so) and the USB2 chip is proven. Why re-invent the > wheel, especially when the quantities are so low. Just for grins I priced a > USB2 core from MEMIC and the cost for net list only, was $30000. Then it > takes about 1500 slices to implement it. That would more than quadruple the > gate count on that particular card and we aren't using all that in the first > place. > > Has anyone tried out any of the new USB2 chips? Any comments on support and > availability for the small guy? (10 to 12 systems a year or less > initially...) Even experience with USB1 would be of interest as I am > uncertain as to exactly what I might be getting into in terms of degree of > complexity. > > Thanks, > Theron > > >>Theron Hicks wrote: >> >> >>>Hello, >>> I am developing an instrument that is currently communicating over a >>>special high speed parallel board. The data rate is 6.4 million 8 bit >>> > words > >>>per second. The board works great but it costs in excess of $1600 US >>> > per > >>>copy. It also occupies a full sized PCI slot. We are considering >>>implementing an alternative I/O arrangement such as USB2 or ethernet >>>(TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some >>>other FPGA friendly technology? Note: target FPGA is a Spartan2E (or >>> > if > >>>absolutely necessary, Virtex2). >>> >>>Thanks, >>>Theron >>> >>-- >>--Ray Andraka, P.E. >>President, the Andraka Consulting Group, Inc. >>401/884-7930 Fax 401/884-7950 >>email ray@andraka.com >>http://www.andraka.com >> >> "They that give up essential liberty to obtain a little >> temporary safety deserve neither liberty nor safety." >> -Benjamin Franklin, 1759 >> >> >> > >Article: 47990
Greetings all. I'm wondering if some of the experts out there can shed some light on this. I am a student working with Altera MaxPlus2 on Flex10K devices. I am trying to minimize a simple project of mine to the lowest number of logic units possible. The project is basically a simple combinatorial which negates (2s complement) a number if a control line is high. I am down to 52 logical units for this design.. but on paper I think that 46/47 LU's are possible. From the report file it looks like MP2 is not creating exactly what I envision to be the most optimal solution. Since the design is so simple.. I am thinking this LCELL primitive might be useful. From what I understand it allows you to manually specify the configuration of cells. There are very few concrete examples available on how LCELL is used within VHDL. Does anyone have a pointer to some worked out examples or guidance on this problem? Any help would be greatly appreciated. Peter de VriesArticle: 47991
Hi Clyde, As Nicholas says, do what you want! You can use integers declaring a 'range' to avoid the default 32-bit coding or std_logic_vector but I would start using std_logic_vector from now on as a good design practice. I don't like 'integer counters' and this is only my opinion :o) Regards -- Ulises Hernandez Design Engineer ECS Technology Ltd./Agilent Technologies ulisesh@ecs-tech.com "Clyde R. Shappee" <clydes@world.std.com> wrote in message news:3DA386C6.639A58D7@world.std.com... > Hello, > > I working a design with some small counters in a design operating at 50 > MHz. They are at most 4 bits. Some 2. Some operate only at 10 MHz. > > The counters are written in my design in a behavioral style, and the > signals used for counting are integers, and never leave the chip. This > has been my style for a long time (years) and I have never worried about > it, and never had a problem. I always declare the range of the integers > used, so no wild 32 bit counters get inferred. > > I have been advised from both Apps engineers at Synplicity and Memec > Design Services that this is not an issue, that the tools will infer a > binary counter and be efficient about it. > > Another engineer says this is a bad idea, and that I should use only > std_logic_vector for these simple counters. > > I have yet to try implementing the design differently and look at the > RTL that Synplify generates, but will do tomorrow. > > Any thoughts? > > Clyde >Article: 47992
Hi What are the ebooks available for FPGA based design.Anybody willing to share ebooksArticle: 47993
Peter de Vries <devriesp@skynet.ca> wrote in message news:<vFMo9.7820$9f2.757909@news20.bellglobal.com>... > Greetings all. > > I'm wondering if some of the experts out there can shed some light on > this. I am a student working with Altera MaxPlus2 on Flex10K devices. > I am trying to minimize a simple project of mine to the lowest number of > logic units possible. The project is basically a simple combinatorial > which negates (2s complement) a number if a control line is high. > > I am down to 52 logical units for this design.. but on paper I think > that 46/47 LU's are possible. From the report file it looks like MP2 is > not creating exactly what I envision to be the most optimal solution. > Since the design is so simple.. I am thinking this LCELL primitive might > be useful. From what I understand it allows you to manually specify the > configuration of cells. There are very few concrete examples available > on how LCELL is used within VHDL. Does anyone have a pointer to some > worked out examples or guidance on this problem? > > Any help would be greatly appreciated. > > Peter de Vries I would first make sure that the "paper" version is actually correct. Then, I would try to understand why the tools did not give me an optimal result. I have personally never used MaxPlus, but in general my experience has been that most tools will/can produce better solution than I can in a reasonable amount of time on paper. Often times I have found that I would not constrain the design properly or based on my coding style the tool had a hard time to determine what I was trying to do. Try rewriting the code in a different way. Given the fact that you are a student I think you would be better of in the long term understanding why the result was not what you expected, rather then giving up and taking the "easy way" out ! Good Luck ! rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores: http://www.asics.ws/free_ip.shtmlArticle: 47994
"Ulises Hernandez" <ulises@britain.agilent.com> writes: > You can use integers declaring a 'range' to avoid the default 32-bit coding > or std_logic_vector but I would start using std_logic_vector from now on as > a good design practice. Because you then will not get pesky "Range constraint violation" errors? F'up. Cheers, ColinArticle: 47995
Tim wrote: > Use an add-in parallel port card. Is their PP drive systematically any better than that from a PC's `southbridge' ? I'd say Kolja's solution of increasing the hysteresis is the right one but isn't, unfortunately, available when using the real P-III download cable [not all the boards I work on are our design] ... well it might be if I opened it up & added the feedback Rs but I've only got one of them so if I break it ... What I'll need to do is create an intermediate stage between the flying wire JTCLK signal and the board => what I need is a single XX125 gate that can, ideally, be powered from the wire itself. It strikes me that the core of the problem is that the Centronics port is really a level based protocol spec'ed in the days of very sloooow TTL logic and, with the P-III cable, we're trying to use it to drive a clock to a modern device that can sense very small transitions. I've never had any problems with the original XC95Ks - even with a 9 device JTAG chain and no extra buffering, a few with the XC95K-XLs, and lots with the XC18V04s.Article: 47996
Heyho! I don't know the Altera tools, but I know Xilinx ISE and ispLEVER from Lattice. THAT is a bad tool! It stopped synthezising, because of an unresolvable multisource. And it said: "error xx: search in the web or ask the Lattice support". I took the source, copied it to ISE and synthezised it. Result: error with a hint on the multisource. I corrected my source and switched back to Lattice and guess what, it works... And that is an easy problem. On Version 2.0 you have the new updated download-tool ispVMSystem. The old version detected that the .jed has changed and asked which to use. The new one does not. It just uses the old one. There is no way to make it use the new one by clicking on a button like "update" or anything else... The only way is to browse to the file again and select it for downloading. That is not user-friendly. Greetz, ThomasArticle: 47997
Dear Tony,
I emailed this guy last week, and he sent me the first draft
of their 'program an FPGA over USB' datasheet. I'm sure if you ask
nicely he'll do the same for you!
Keith Dingwall
To: <support@ftdichip.com>
Sadly, as you'll find out when you read it, this scheme
outlines a way of programming the FPGA one bit at a time. The sad bit
is that each FPGA program bit needs two bytes to be sent over the USB.
(Clock goes low and set the data bit in first byte, clock goes high in
second byte.) If you don't mind waiting a while for your FPGA to
program that's ok. However, I think you can make this go 16 times
faster, i.e. clock bytes straight into the FPGA in slave select map
mode (I'm using Xilinx parts), by generating a CCLK signal for your
FPGA from signal RXF# using some Schmitt gates with an RC network. See
the data sheet for the FT245BM. I'll be trying this in a few weeks
time, but I'll be wiring it up so that I can use the slow way too,
just in case!
HTH, Symsx.
"Tony M" <tonym_98@hotmail.com> wrote in message news:<glLo9.2697$1F.959079441@newssvr10.news.prodigy.com>...
> Do they have an app note or something? What are intermediate parts?
>
> We need to use the USB to transfer data back and forth between PC and FPGA,
> as well as download bitstream to the FPGA.
>
> To do this we hooked up the FTDI module to a Xilinx 95108 CPLD which
> distingquishes between the two types (data or configuration).
>
> If I get what you guys are saying you can hook up that FTDI module directly
> to the FPGA to boot it.
>
> Thanks,
> Tony
>
> "Jon Schneider" <jon@axisREmilMOVEton.ltd.uk> wrote in message
> news:memo.20021008222529.4573A@xxx.cix.co.uk...
> > In article <anus53$hkp3q$1@ID-92522.news.dfncis.de>, Jensniemann@gmx.de
> > (Jens Niemann) wrote:
> >
> > > is there somewhere a reference design or some information about
> > > booting a SRAM-based FPGA via a USB interface?
> >
> > The newer FTDI devices have a way of doing just this.
> >
> > http://www.ftdichip.com
> >
> > Jon
> >
Article: 47998"Mike R." <mrandelzhofer@uumail.de> writes: > As a special gift, xilinx doesn' t support the synopsys fpga compiler which > is a rocket compared to the xilinx synthesis tool. Are you saying that ngdbuild in ISE 5.x can't read EDIF files generated by Synopsys FPGA Compiler II (FC2)? I've been using FC2 with ISE 3.x and 4.x without any problems. I find it hard to believe that they don't support FC2 anymore. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 47999
kevinbraceusenet@hotmail.com (Kevin Brace) writes: > While I agree that Quartus II's help system is better than > ISE's, Altera doesn't seem to have detailed manuals of their software > available for download unlike Xilinx. I don't use the Quartus II GUI much other than for floorplanning and building megafunctions. I do most of my work with Tcl scripts. Hence, I wish they had the documentation available as PDF files. I would rather see improved functionality such as SMP and cluster support for large PAR jobs rather than a fancier GUI. One big plus: Quartus II runs under Linux in native mode! The Quartus II Linux edition GUI behaves rather odd (at least under fvwm2). It will always stay on top of all other windows. There is no way to raise other windows like xterms on top of Quartus. Even when minimized it punches through all other windows on the desktop. Have anybody else experienced this behavior? Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petter
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