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Hi, for designing a > slave device. They say on pag 12 that everything (the state machine > and associated counters and shift registers are clocked on the falling > edge of SCL, 'cause on heavy loaded systems the rise time of the SCL > line may be very slow and that is dangerous on a clock a signal, > 'cause it can generate noise on it. > > However, on Philips I2C bus Specification v2.1 Jan-2000, pag 8 they > say the data on the SDA line must be stable during the HIGH period of > the clock. > And I strongly recommand to pedantically follow the Philips specification. Philips has invented the i2c bus and it does restrict the capacitive load on the bus to allow for better signal forms. In fact, on high speed mode active driving is performed (boosting) to speed up level change. Note that for instance tracing tools expect the Philips standard to be kept - otherwise they report an error see: www.tracii.de Hope this helps - RolandArticle: 42201
Steffen Thieringer wrote: > > "Russell" <rjshaw@iprimus.com.au> wrote > > > How about just using a smaller fpga as a dedicated pwm/timer peripheral > > for a cpu. Better still, a motor control dsp. > > sure, a motor control dsp solution is better, but not done in 10 minutes. > i need a driver now, and for the changeover (8051-hardware to dsp-hardware) > i want to go for the 8051 software. > > the way to go for a speeded up 8051 ip-core is for using a program which has > done the job very well on 8051 hardware, but became obsolete because of > speed. How about a Cygnal 8051 which does 50mips(?) allegedly. The 8051 seems quite a complicated bit of hardware that i think would require quite a big fpga, and the speed wouldn't be that high.Article: 42202
"Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message news:3cbeabe7$0$8514$cc9e4d1f@news.dial.pipex.com... > Secondly, why the single chip requirement? Is it a space issue? Because a > two chip mounted on either side of a board would probably take less space > and allow you to have far cheaper chips. It's because I have a certain number of input channels to deal with, and they all have to be dealt with together. It's a big pain in the ass if I have to go off chip as that is what my current design does. When it's all in one chip, I can perform certain optimizations which will make the overall product superior. GuerreArticle: 42203
"Roland Zitzke" <zitzke@gmx.de> wrote in message news:a9mh3o$n0$00$1@news.t-online.com... > Hi, > for designing a > > slave device. They say on pag 12 that everything (the state machine > > and associated counters and shift registers are clocked on the falling > > edge of SCL, 'cause on heavy loaded systems the rise time of the SCL > > line may be very slow and that is dangerous on a clock a signal, > > 'cause it can generate noise on it. > > > > However, on Philips I2C bus Specification v2.1 Jan-2000, pag 8 they > > say the data on the SDA line must be stable during the HIGH period of > > the clock. > > Take the data with a latch enabled by clock high - it'll pick the state at falling edge (-setup time). Tauno Voipio tauno voipio @ iki fiArticle: 42204
Thanx. Now it's working. Matjaz "Kerri Golden" <kgolden1@yahoo.com> wrote in message news:3abccfd0.0204160745.2095aae7@posting.google.com... > Hi Matjaz, > I have the workaround for you. > Nios 2.0 does not support Win98, but there are steps to make it work. > > First - install to a directory that is all lowercase. > > In Nios: > 1. make sure that your germs mon has a good vecbase offset. - the end > is best. > 2. generate. > 3. it will fail - it says that it made the sdk, but it didn't. So, you > have to make it. > 4. so, through the start menu, go to programs>Altera>Excalibur Nios > 2.0> Nios SDK Shell > navigate to your project dir and type mk_custom_sdk > this will make your sdk. > 5. when it is done, press generate again on your Nios design. > > This has solved all the problems we've had on Win98. > > Also note that Quartus runs MUCH faster on 2000 than on 98. > > > Kerri > > > "Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message news:<3cb69b58$0$227$cc9e4d1f@news.dial.pipex.com>... > > "Matjaz Finc" <matjaz.finc@fe.uni-lj.si> wrote in message > > news:a961r4$o9$1@planja.arnes.si... > > > Hello! > > > > > > Has anyone experienced any problems with Nios 2.0 (build 224) in Quartus > > II > > > 2.0? I can't generate it with SOPC builder - it always terminates with an > > > error. Even Altera representatives and their official support were of no > > > help (!?) until recently - they said it will be fixed in next update. My > > OS: > > > win98. > > > > Though I can't help with the specifics, I have found that all of the tools > > run far more smoothly under windows 2k. I used to dual-boot, but frankly I > > don't bother with win9x now. > > > > Another tip is to make sure all tools run from paths with no spaces. The > > batch command line scripts etc have a habit of sometimes not working with > > spaces. (e.g. Leonardo integration etc) > > > > PaulArticle: 42205
> > "Russell" <rjshaw@iprimus.com.au> wrote > How about a Cygnal 8051 which does 50mips(?) allegedly. The 8051 seems > quite a complicated bit of hardware that i think would require quite a > big fpga, and the speed wouldn't be that high. Very interesting, thank you for the link. But despite the speed of the cynal 8051, going for a software solution will better for me, because of implementing several parts of circuit(pll, pwm, memory..) in one single piece of silicon. accuraccy will then be increased. SteffenArticle: 42206
Hi, I have a design using the VirtexE DLL (HF). The Xilinx ISE 4.1i TRACE tools report a critical path which count the same path twice. The Xilinx ans. for this is that I use a two phase clock in the design which need to x2 the path delay. My desing has only two clock (clk and clkdiv from DLL) and only rising edge is used. What is the possible error. If this is by default, how can I get the *real* timing report. The original design implementing under 3.1i does not have this problem. I just add a small DFF in the original datapath to make it faster and switch to 4.1i. What's wrong? Thanks in advance. ---- BrittleArticle: 42207
"Steffen Thieringer" <steffen.thieringer@nmb.co.uk> a écrit dans le message news: a9mf36$4g6ga$1@ID-41871.news.dfncis.de... > > "UK Gary" <deton8@aol.com> schrieb im Newsbeitrag > news:a9m9g1$28d$1@helle.btinternet.com... > > I need to design something where the FPGA must have about 1000 I/O pins. > > What is my cheapest option? The design must fit into a single FPGA, but > > apart from that and the pin count I don't have any special requirements. > > Upcoming Altera Stratix devices do have more than 1000 I/O (up to 1310)! > > http://www.altera.com/products/devices/stratix/overview/stx-overview.html Xilinx Virtex-II have more than 1000 I/O (up to 1108) and they are not upcoming ! http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Platform+FPGAsArticle: 42208
Steffen Thieringer wrote: > > > > "Russell" <rjshaw@iprimus.com.au> wrote > > > How about a Cygnal 8051 which does 50mips(?) allegedly. The 8051 seems > > quite a complicated bit of hardware that i think would require quite a > > big fpga, and the speed wouldn't be that high. > > Very interesting, thank you for the link. > > But despite the speed of the cynal 8051, going for a software solution will > better for me, because of implementing several parts of circuit(pll, pwm, > memory..) in one single piece of silicon. accuraccy will then be increased. > Steffen Could try asking in news:comp.arch.embeddedArticle: 42209
William, I am just pointing out that some synthesis tools seem to fight you sometimes, and there are attributes that one can use to keep things in the design that don't seem to agree with the synthesis tool that you might be using. The technical answer in the answers database came from a case that was solved by this advice. I agree that if you tie a logic '0' to an IOB, and drive it off chip, that the tools should not get in your way: this is a long known, and often used method of improving the ground connection to the die, and reduces ground bounce by a significant amount (sometimes as much as cutting it in half). Austin William L Hunter Jr wrote: > Austin I can understand this for inputs but don't agree on outputs. > Inputs may not be required to implement a desired function and > therefore be optimized out. But setting a output to logic0 (i.e. > output<='0') should also work. ThanksBill > > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message > news:3CBDA28C.8496D40F@xilinx.com...William, > > See: > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=9780 > > For how to "keep" and "don't touch" instantiations so the > tools don't rip them out.... > > Austin > > William L Hunter Jr wrote: > > > Hi > > > > I am doing a Virtex-II design using ISE 4.2.01 and FPGA > > Express 3.6.1. I > > have a few pins on my top level entity configured as > > outputs which are used > > to set the address of some external devices. In my > > architecture, I assign > > these outputs a '0'. FPGA express is optimizing out this > > connection. If I > > look at the synthesis optimized schematic viewer the > > connection to gnd and > > output pad are missing. How do you connect outputs to GND > > in VHDL? I have > > always assigned them a '0' in the VHDL and this always > > worked. Any ideas on > > what could be wrong?? > > > > Thanks in advance > > Bill >Article: 42210
Thanks. I will have a look at it. Prashant Hari Devanath <harid@xilinx.com> wrote in message news:<3CBDE120.82B83123@xilinx.com>... > Hi Prashanth, > In particular, if you want to write HDL for Xilinx devices, this is a good > place to start: > http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/preface.html > Hari. > > Prashant wrote: > > > hi, > > I read in a post previously that VHDL/Verilog programming style > > differs when being written for an FPGA from being written for an ASIC. > > Is there any website which mentions these differences ? I'm looking to > > see what should I take care of when programming for an FPGA. > > > > Thanks, > > PrashantArticle: 42211
Unfortunately, the Telecom Bus is not a standardized bus. It was =
originally written up in an IEEE draft and then cancelled. Here is the =
bibtex reference for this draft (you will definitely have to be an IEEE =
member to find this file -- it isn't available electronically AFAIK):
@manual{bib:IEEE-P1396.1,
title =3D "IEEE Draft Std. P1396.1, COMBUS: A Backplane Bus and Package =
for
SONET Applications",
address =3D "IEEE, New York, N.Y.",
year =3D "1990",
month =3D "November"}
PMC-Sierra's standardized bus is the SBI bus, which is very similar to =
the Telecom bus (i.e., can run in 77.76 MHz parallel mode, etc.) .... =
PMC sells a number of switches, serializers, and so forth that support =
both the Telecom bus and their own SBI bus.
If you're using PMC parts, and have access to PMC's datasheets, I =
recommend looking at the SBI Bus Serializer (SBS) datasheet, or the =
actual SBI Bus info sheet (but they may not make the latter publically =
available, I dunno).
cheers,
-kris
> I am looking for spec/details on Telecom Bus (TelecomBus). I searched
> on the web and all I could get is a number of links to PMC Sierra
> which offers Telecom bus bridges, converters, serializers etc but
> does not offer much details about Telecom bus protocol. Neither could
> I find anything on the IEEE standards website.
>
> I am designing an ATM Cell Processor in FPGA which has Telecom bus
> interface. I would greatly appreciate if someone can point me to
> relevant info on Telecom Bus.
Article: 42212It looks like a nice board. I'll contact you remotely about the software. On Tue, 16 Apr 2002 12:06:15 +0200, Johann Glaser <Johann.Glaser@gmx.at> wrote: >Hi! > >> I'm looking for a SpartanXL demo board. Any good ones out there? >> >> Something I can download with my XChecker cable, and get at all the >> pins. > >Look at http://www.digilent.cc/. They have a nice board. It is available >with a Spartan or a SpartanXL FPGA (3.3V version). > >It is quite cheap, I think less than $100. The only problem is, that >Spartan and SpartanXL are not supported by Xilinx WebPack. > >Downloading the configuration is done by a parallel cable. If you need >instructions or souce code, you can have mine. I wrote a small Pascal >program for Linux, but it is easily ported to whatever you need. > >Bye > HansiArticle: 42213
Hi,all I'm now encountering a strange thing with fpga. CLKA is input to fpga through one of the GCLK pin.After IBUFG it has the net name CLKA_IN.I watch CLKA and CLKA_IN on an oscillograph. The strange thing is that sometimes when there are still transitions on CLKA,CLKA_IN will pause for a while either staying "1" or "0". I also have another clk domain in that fpga CLKB and CLKB_IN.CLKB_IN also pauses at the same time as CLKA_IN though CLKB sitll has transitions as usual. Isn't it strange?I've never ever heard of this.What should I do now? thx in advance mmArticle: 42214
Steffen,
> I am looking for a 8051 Core to implement in an Xilinx Spartan2 FPGA.
> The task for it is a control of a sensorless brushless DC motor.
> The software for the processor is already done but needs to be speeded up.
> So i need pwm, capture/compare units, several timers ans so on...
> I have several in my mind but not yet found 'the one'.
> I am not looking for freeware, but if there are some out there, please let
> me know:-)
we developed an 8051 derivative which is planned to be released as a
commercial product later on. We are currently looking for people, who are
interested in cooperating with us, to debug and verify the core in "real
life applications". We will provide the core for free, to enable such a
cooperation.
Our core is cycle-compatible to the original 8051. It provides 4 ports, 128
bytes of internal RAM, supports the complete instruction set, and implements
timers and interrupts. With this setup, the core implements quite nicely in
Spartan2 FPGAs, as the following map report reveals. However, we are
assuming that there is still some room for optimizations.
Design Summary:
Number of Slices: 1,245 out of 2,352 52%
Number of Slices containing
unrelated logic: 0 out of 1,245 0%
Total Number Slice Registers: 495 out of 4,704 10%
Number used as Flip Flops: 451
Number used as Latches: 44
Total Number 4 input LUTs: 2,297 out of 4,704 48%
Number used as LUTs: 2,211
Number used as a route-thru: 22
Number used for 32x1 RAMs: 64
(Two LUTs used per 32x1 RAM)
Number of bonded IOBs: 148 out of 140 105%
IOB Flip Flops: 94
Number of GCLKs: 1 out of 4 25%
Number of GCLKIOBs: 1 out of 4 25%
Total equivalent gate count for design: 27,016
Additional JTAG gate count for IOBs: 7,152
Steffen, if you are interested in working with us, please drop me a line, so
that we may discuss further issues.
Best regards
Felix
_____
Dipl.-Ing. Felix Bertram
Trenz Electronic
Duenner Kirchweg 77
D - 32257 Buende
Tel.: +49 (0) 5223 49 39 755
Fax.: +49 (0) 5223 48 945
Mailto:f.bertram@trenz-electronic.de
http://www.trenz-electronic.de
Article: 42215"Eric Kral" <eric.kral@planetinternet.be> schrieb im Newsbeitrag news:a9m34u$oaa$1@reader08.wxs.nl... > Hi, > > I am trying to realize a bidirectionnal bus between two components. It seems Inside the FPGA, the is no need for a "real" bidirectional bus. It can be made, but why? The are plenty of routing ressources, so use them and use unidirectional busses. > to work (I can synthesize the design but the simulation doesn't work > properly, moreover I cannot implement the design and I can find the > problem(s)). > My synthesis tool is the latest version of the Webpack from Xilinx. > The idea of the design is to enable a fast communication between several > FPGA. The target FPGA is a Virtex-E from Xilinx. The TDM entity is to enable OK, this is another story, but then you have to be carefull. And ist not easy to test the two modules inside one FPGA with INTERNAL connection, since this will change the IO drivers. So if you want to connect multiple FPGAs, create a test toplevel, drive the IOs outside (just as you would in the final application) and connect then using physical wires. -- MfG FalkArticle: 42216
Hello everyone, Iam afraid Iam missing a major point in FPGA clock routing. I have a Virtex-E (300), feed a clock from a Xtal (36 MHz) into a global clock input, divide it down by 8 by means of a DLL and provide this clock to a clock buffer. A big part of my design runs at this ~5Mhz clock. So far, so good. But now comes the tricky part. I have some block which handles a interface with another device (its a UTOPIA2). All output signals use IO FFs. The clock is simply routed to an IO pin and from there to the other chip. The interface is fully synchronous, everything works on the rising edge. I expected, that the datas are slightly delayed behing the clock, by the clock-2-output time of the IOB FF, but they were NOT!!!! The clock IS delayed by ~3 ns behind the data!!!! First question, how does this happen? I thougt the clock nets are low skew, means the clock arrives at all cell at the same time. But the P&R tools tell me, that the clock is driving non-clock load, which can cause skew trouble (and it does :-( Second, what is the clean approach for clock distribution (without DLL usage) At the moment, I use a registers clocked on the other (falling) edge to "simulate" the right phase relation between clock and data. -- MfG FalkArticle: 42217
Hi, Your error message indicates that the synthesized design has two TBUF (three-state buffers) named srampad_I4_0 and tdmpad_I26 -- which have their outputs tied together, and also share the same output enable signal. So, in operation, you can have a situation where both of them can turn on at the same time, which is an electrical no-no. I suspect you did not do this on purpose. You need to go back and re-check your code. If you can't simulate it correctly, you cannot possibly expect the synthesis result to be meaningful. I'd spend your time debugging your code in the simulator. Hope that helps, Eric Eric Kral wrote: > Hi, > > I am trying to realize a bidirectionnal bus between two components. It seems > to work (I can synthesize the design but the simulation doesn't work > properly, moreover I cannot implement the design and I can find the > problem(s)). > My synthesis tool is the latest version of the Webpack from Xilinx. > The idea of the design is to enable a fast communication between several > FPGA. The target FPGA is a Virtex-E from Xilinx. The TDM entity is to enable > the fast communication (TDM stands for time division multiplexing). > The SRAM is the interface for the SelectRam+ which is a blackbox in the > virtex-E (RAM of 4096 bits) > Finally the COMP entity should be the top design implemented in the FPGA.Article: 42218
Sum wrote: > Xilinx Virtex-II have more than 1000 I/O (up to 1108) and they are not > upcoming ! > http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Platform+FPGAs Yes, the XC2V6000 is in production, and it has 1,104 user I/O pins in the FF1517 package. The small-quantity price is several thousand dollars. You can find it listed at the distributors web sites. ( insight-electronics.com, avnet.com, nuhorizons.com,) Peter Alfke, Xilinx ApplicationsArticle: 42219
There were several comments about that topic, so I'll address some of the issues here. 1. Desired book: <What I would like to see in a book is simple: Take five or six projects of increasing complexity and have a chapter or set of chapters taking each one from inception to completion. This means from generating specifications, to choosing the chip, writing the code, fitting it to the chip, making changes and programming the chip. That would be a very useful book. > BEN: There are several issues in this proposal: Requirements definition, architectural definition, testbench planning, design, verification, and documentation. I have attempted to do that in my book "Component Design by Example ", 2001 isbn 0-9705394-0-1" where I used a UART of full complexity with error detection, FIFO, and CPU interface with priority encoding. That design is far in complexity from the UART that is at my web site that merely consisits of a parallel to serial, and serial to parallel register with clock detection. The UART in the book includes a reusable parser package. The intent of that book was really the process, and issues with design definition, implementation, and verification. <I'm afraid that the ad-hoc style of presentation with poor and inconsistently styled diagrams is the first thing to hit you. Tables of text that look like they were converted to bitmap and then stretched are really unacceptable in this day and age. Same applies to certain equations (how long would that have taken to typeset properly?)Probably an easy way of scanning source material though :( > BEN: The goals for the book "Real Chip Design and Verification Using Verilog and VHDL" were: 1. Address issues that I experienced with designers who thought that knowing an HDL meant that you were ready to do designs. That in why in the chapter on Fundamentals, I covered with guidelines, the topics of reg, latch, 2 edges of clk, and various types of counters (e.g., LFSR, Johnson, etc), memories, primitives, and clockboost). It is true that some material were extracted, with permission, from various vendors and authors. However, the object here was to put relevent information in one place. 2. Address the topic of asynchronous signals. Again, you'll be surprised as to the number of engineers who fail to understand how to deal with that issue. 3. Verification: Here I used 2 examples: a counter and a memory with EDAC. I was working on a project that spent many many (really many!) hours on the design and verification of a memory with EDAC, anyway, far more thatn the $80 cost of the book. 4. Design process in defining a control machine: I have seen horrible code an processes in the definition of such design. Here I attempted to define a usable, and hopefully practical approach with a process, or a flow. 5. In arithmetic machines, I was defining the usable packages, and issues with Verilog. 6. Mixed simulation is something that is common now because many vendors require Verilog for the release sims, and many IPs come in Verilog (at first). 7. I wanted to present Verilog as an HDL for several reasons: a. Verilog is really gaining in popularity. b. Many IPs come in VErilog first. c. Release sioms are often required in Verilog. By demonstrating designs in both HDLs, my intent was to facilitate the transition from one HDL into the other, and to sho that the real design issues are not necessarily the HDL, but the process and architectures. I also includes a tutorial of Verilog for VHDL users to explain the differences between the two HDL. <Granted there's a CD with a lot of the files on, and the book does provide a central repository, but I don't think that justifys the expenditure of your effort> The book sells for $80. If you can do better thatn than by searching things on the web, extracting meaningful info, print the material needed for less thatn $80, my hat goes to you! <There are items that everyone from newcomers to moderately well-versed HDL engineers will learn, but it isn't presented in a coherent style, instead my impression is that its stitching articles together in the hope of getting a book published quickly> You are entitled to your opinions. If you feel cheated after receiving the book, you may return for a refund. However, the reviewers of the book, including corporate VPs from Cadence and Synplicity really felt taht the book had a lot of values as an investment. By the way, writing a book, and going the process of publishing (wheter thru a major publisher or self-publishing) is not a "quick" manner and DOES take many, many hours of work, particularly when the code has to also be verified and explained. It also does take research on the web, something that was brought up as a "trivial manner, not worth the effort of the consolidation of the necessary, and filtered information". I hope that this explanation provides some info as to why I wrote the book. I know that I did my best, and with a lot of effort. Style is an issue own by the beholder. My style, like it or not, is by complete example and graphics. ---------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------Article: 42220
Falk, I do not really understand your design, but here is a brute-force solution: Use the opposite clock edge for your interface. This has beeenan old remedy, applicable in any low-frequancy situation. And 36 MHz is low frequency these days. As I said, this is not an explanation, but rather a fix. Gruß Peter ========================= Falk Brunner wrote: > Hello everyone, > > Iam afraid Iam missing a major point in FPGA clock routing. > I have a Virtex-E (300), feed a clock from a Xtal (36 MHz) into a global > clock input, divide it down by 8 by means of a DLL and provide this clock to > a clock buffer. A big part of my design runs at this ~5Mhz clock. So far, so > good. But now comes the tricky part. I have some block which handles a > interface with another device (its a UTOPIA2). All output signals use IO > FFs. The clock is simply routed to an IO pin and from there to the other > chip. The interface is fully synchronous, everything works on the rising > edge. > I expected, that the datas are slightly delayed behing the clock, by the > clock-2-output time of the IOB FF, but they were NOT!!!! > The clock IS delayed by ~3 ns behind the data!!!! > First question, how does this happen? I thougt the clock nets are low skew, > means the clock arrives at all cell at the same time. But the P&R tools tell > me, that the clock is driving non-clock load, which can cause skew trouble > (and it does :-( > Second, what is the clean approach for clock distribution (without DLL > usage) > At the moment, I use a registers clocked on the other (falling) edge to > "simulate" the right phase relation between clock and data. > > -- > MfG > FalkArticle: 42221
Yesterday I attended PW2002 in Toronto. I have attended Xilinx promotional seminars since the days of the XC2000. Until now, I have found that the Xilinx seminars provided enough technical information to make the marketing content tolerable. PW2002 was a radical shift toward marketing glitz, at the expense of useful technical content. Heck, we weren't even supplied with VirtexII Pro data books, I had to ask for one from our rep. During the IBM "technical training" track I actually got angry. At least 90% of the presentation was IBM marketing, describing various IBM PowerPC processors and cores. Now I can't remember which features are in the core that is actually used in the PowerPC, since we were bombarded with features spanning the entire IBM product line. The keynote speakers talked about stuff that had nothing to do with the VirtexII Pro, except in abstraction. Apparently, this seminar was not targeted at engineers. I'll keep that in mind the next time I get an invite to a Xilinx seminar. =================================== Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.comArticle: 42222
Is it feeding a DLL ? "mm" <lunaris_s@yahoo.com> wrote in message news:a2d0027.0204180731.3ca28548@posting.google.com... > Hi,all > I'm now encountering a strange thing with fpga. > CLKA is input to fpga through one of the GCLK pin.After IBUFG it > has the net name CLKA_IN.I watch CLKA and CLKA_IN on an oscillograph. > The strange thing is that sometimes when there are still > transitions on CLKA,CLKA_IN will pause for a while either staying "1" > or "0". > I also have another clk domain in that fpga CLKB and > CLKB_IN.CLKB_IN also pauses at the same time as CLKA_IN though CLKB > sitll has transitions as usual. > Isn't it strange?I've never ever heard of this.What should I do > now? > thx in advance > mmArticle: 42224
"Felix Bertram" <f.bertram@trenz-electronic.de> schrieb im Newsbeitrag news:a9mqfj$4l83o$1@ID-31589.news.dfncis.de... > Steffen, > > > I am looking for a 8051 Core to implement in an Xilinx Spartan2 FPGA. Hmm, maybe its worth a try to have a look at xapp213. The is a 8-Bit RISC, very small, but very clever and fast. 16 8 bit register 256 instructions program size >20 MIPS 8 bit IO port for additional hardware. interrupt capability. uses just 5% in a Spartan-II 100, even the smallest Spartan-II (XC2S15) can hold 1 and has still 40% free. all you have to add are the timers/PWM. This is easy, but this will change the project from a pure software issue to a FPGA/hardware issue. -- MfG Falk
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