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Hi, I want to create several ram modules (8x16x9, 4x16x10) as parts of an design, which will be synthesized into a XC4085xla. Which generator should I use ? What are the advantages/disadvantages ? The next problem is the functional simulation with these generated modules. If I understand right the thread "Complaint: Xilinx functional simulation libraries", this applies to me too ? Thanks ciao J=F6rgArticle: 25576
Dear NG, Im new to this group so please excuse me for asking daft questions. Are there any resources out there for ATMEL FPGAs? I just got the atmel fpga evaulation board and I have an application for which I think an FPGA like this would suited. Im a hobbiest so I do this stuff for fun, so lots of time, but no money ! :-) I wondered if anyone knows any usefull resources and/or URLs that I can look at? I am going on holiday and Im taking the books that came with it with me so I can read them and learn a bit about the structure of the thing. Many thanks Paul Maddox -- Paul Maddox DERA MALVERN E112 St Andrews Road Malvern, Worcestershire WR14 3PS UKArticle: 25577
On Thu, 14 Sep 2000 11:01:45 +0200, Michael Boehnel <boehnel@iti.tu-graz.ac.at> wrote: >Hi! > >What is the bit ordering of a frame (source, dest, ..., CRC) sent via >Ethernet NIC (3COM 905, 100Mbit)? I suppose it's the following (preamble >neglected): > >fields transmitted top to bottom, within bytes least significant bit >first. > >source > byte 5 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 > byte 4 : > byte 3 : > byte 2 : > byte 1 > byte 0 >destination > byte 5 > byte 4 > byte 3 > byte 2 > byte 1 > byte 0 >: >CRC > byte 3 > byte 2 : > byte 1 : > byte 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 > > >First bit: source - byte 5 - bit0 >Last bit: CRC - byte 0 - bit7 > >Is above correct? I don't think so. The addresses are Ok, with the first bit (byte 5/bit 0) being the I/G bit. The length field also goes high byte first. The bits of the CRC polynomial are shifted out in the order x**31 first, x**0 last. I would call the last bit out byte 0 bit 0, but I guess it could be called byte 0 bit 7 by some. EvanArticle: 25578
Martin Usher wrote: > > > > This is not correct... At least not according to MIPS's lawyers. MIPS is > > currently suing Lexra for doing software emulation of some patented > > instructions (LWL, LWR, SWL, and SWR to be exact). Of course > > Lexra's lawyers would disagree. > > > 1) What do these instructions do? (They look like 'word shift' type > operations....) They are "Load Word Left/Right" and "Store Word Left/Right". They are used when loading & storing words that are not aligned on a word boundary. > 2) Did they patent the instruction menomic or what the instruction did? If > its the latter then a patent has been issued for an algorithm. I do hope its > not a commonly employed one - I can't think of any operations at the > register level that haven't been implemented in some machine or another over > the last five decades. They patented what the instruction did. One could argue that they didn't patent an algorithm-- only a way of doing an algorithm. These instructions are basically do a load-shift-and-or. We could do these instructions using those standard 4 instructions, but the patent covers doing them in a single instruction. > 2b) I think everyone agrees that the patent office needs reinventing. It > currently does more damage than good in our business, IMHO. Amen to that! > 4) I've got a real 'thing' about people who patent bullshit things, > especially if they really believe that they invented this stuff. It takes a > special combination of arrogance and ignorance to believe that you have > truly invented something basic in our trade. They need to humble up, learn a > bit, and maybe work hard enough to actually invent something new. I think I'll patent the "Look and Feed Like S&*T". I would just love to sue Microsoft, claiming that their software violates the "Look and Feed Like S&*T" patent. Too bad about that prior art thing... David Kessner davidk@free-ip.comArticle: 25579
Austin Franklin wrote: > > > 1. Is Transmeta's SOFTWARE approach to the manipulation of x86 > > > instructions set what avoids the violation of patents' rights? If > that's > > > right, I understand that patent infringement is only possible when > there > > > is a hardware implementation. > > > > This is not correct... At least not according to MIPS's lawyers. > > Completely different issue. The instruction set is not patented, nor can > it be. Apparently it can be! Of course, we have to really look at what was patented... What was patented is the combination of several common things into four instructions. Not the instruction itself, its neumonic, or the opcode encoding. The combination of operations into some simple instructions is what's patented. And this, I believe, can be patented (as much as I disagree with patents). > > MIPS is > > currently suing Lexra for doing software emulation of some patented > > instructions (LWL, LWR, SWL, and SWR to be exact). Of course > > Lexra's lawyers would disagree. > > Here is the patent: > > http://patent.womplex.ibm.com/details?&pn=US04814976__ > > I have written code to do the same thing for over 20 years, and I know I > have seen other code before mine that did the same thing. But that doesn't matter... We've all done code that that. What's patented is that this has been put into some instructions specifically for this purpose. Where Lexra's getting into trouble is that they are doing a software solution to hardware emulation. Essentially, Lexra is still executing the instructions (but in software) and MIPS is saying that what matters is that they are being executed at all (SW or HW). > I even did a > microcode implementation similar to this in a 29203C some 20 or so years > ago for a vision processor. I'm not sure if that applies. The patent refers to a RISC CPU (i.e., no microcode). > There is sure to be plenty of prior art to > this... I downloaded a copy of the patent in its' entirety, and perhaps > there is something really patentable here, but from my initial look, it > seems like this won't hold up. Just my opinion... I agree on the prior art thing, and with your general opinion. But... Our patent system is broken. If I were on trial for murder, my punishment would come after the judge renders his verdict. But if I were on trial for patent infringement, my punishment would come during the trial, in the form of trial expenses, not once the judge gives his verdict. This is a double whammy... Not only does the patent office give frivolous patents, but there is no presumed innocence. The innocently accused will always loose, regardless of what the judge says. The only protection for this type of lawsuit is to counter sue for some other patent infringement. The two sides lock in a stalemate and are forced to settle (this is called a "cross licensing agreement"). This is one huge reason why looser companies are bought out-- since their patent portfolio can be more valuable than the actual company. Buy a small company for 10 million, but save 20 million in legal expenses... I guess my point is that the small guy has to be extra careful about this patent stuff since it's really easy to get stepped on and squished into oblivion (been there, done that). David Kessner davidk@free-ip.comArticle: 25580
news@rtrussell.co.uk wrote: >Hawker <Hawker@connriver.net> wrote: > >: Are you going into some sort of boundary scan mode? >: I had a similar problem with a XCS05. I found some >: sort of app note about adding some pull-ups and 2 small caps >: to the JTAG pins and it fixed the problem. Basically random noise >: was putting me an a boundary scan or JTAG programing mode of some sort > >That's exactly what it was! Tying the unused JTAG pins >high has fixed the problem. Many thanks for your >suggestion. Just for the record, I've had the same problem on an XCS30. I didn't find the appnote but pullups alone solved the problem in my case. Richard ------------Richard Dungan------------- Radix Electronic Designs, Orpington, UK richardATradix-designDOTcoDOTuk ---------------------------------------Article: 25581
shahzad2512@my-deja.com wrote: > > Different types of adders are available that offer different > advantages. These adders are: > Ripple Carry Adders > Carry lookahead adders > Carry Select adders > Conditional Sum adders > These adders when implemented in FPGAs deliver different performance in > terms of speed and area. Both these things are critical for FPGAs. I > implemented a Logiblox 4 bit adder and then implemented CLA adder. CLA > was equivalent in resources to the logiblox and was faster. But bigger > CLA consumes more resources than the Logiblox adder. Adders are the > basic units that are extensively used in many designs. > Has anyone done a thorough research on which adder is the best for say > Xilinx FPGA, Altera, Atmel FPGAs. If someone has done a thorough work > on Adders for say, Altera FPGAS, it will be worth sharing the > experience. If someone knows that this topic has been discussed it will > be helpful to mention the relevant site. > Regards, > SHAHZAD > > Sent via Deja.com http://www.deja.com/ > Before you buy. If the FPGA has fast ripple carry ( many do ) for work under 32 bits simple ripple carry is the fastest. The FPGA family in use will reflect the best type of carry lookahead because of the need to map the logic well to the FPGA device.I think carry select adders can work a tad faster than CLA adders. Routing plays a big part in adder design as small slower adder may run as fast as large faster adder do to routing delays. Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchukArticle: 25582
Jörg Ritter wrote: > > Hi, > > I want to create several ram modules (8x16x9, 4x16x10) as parts of an > design, which will be synthesized into a XC4085xla. > Which generator should I use ? > What are the advantages/disadvantages ? I think the CORE stuff is "preferred" these days. I haven't done Logiblox in quite a while. Logiblox doesn't even exist for Virtex. > The next problem is the functional simulation with these generated > modules. > If I understand right the thread "Complaint: Xilinx functional > simulation libraries", this applies to me too ? I just checked. The answer is: IT DEPENDS. The CORE things I've been using recently -- single and dual-port RAMs -- have models that have no timing information in them at all, which is a Good Thing. However, the sync FIFO model *does* have a 1 ns delay on all of its inputs except the clock. After doing a design with a CORE FIFO and having its simulation not meet reality, I looked at the model and saw what was going on. I ended up rolling my own FIFO. Note to Xilinx: how about adding a little timing diagram to the CORE data sheets? It shouldn't be that hard. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25583
File this under "bug in v3.4." Or file it under "FPGA Express is too stupid to live." Or file it under "Why haven't they figured out the goddamn architecture yet?" Here's the scenario. I'm doing a little experiment. Target architecture is Spartan and 4KXLA; the problem is the same for both. Most of my flops are clocked on the rising edge. One of the things I did was to have a handful of flops clocked on the falling edge. Normally, placing a period constraint on the clock is all that's required; map and p&r should go, "Ah! two-phase clock" and do the right thing. p&r runs, and the report at the end complains that there's skew in the design due to something not using a global clock net, and the skew wasn't analyzed. OK, run trace with the skew option. Ooops -- there's a bunch of flops with like 4.8 ns clock skew (100 MHz period constraint) and clocked from N1964_BUFGed. Weird. Poking around with FPGA Editor (which is really useful when you're trying to figure out just what the hell the tools did), turns out that N1964_BUFGed is the clock net for the falling-edge clocked flops. Right then, I knew exactly what the problem was: FPGA Express 3.4 is too stupid to realize that the CLB HAS A CLOCK-POLARITY MUX RIGHT IN FRONT OF THE FLOP SO IT DOESN'T NEED TO USE A CLB TO INVERT THE CLOCK! At least it knew enough to route the output of the CLB inverter to a BUFGLS, but it's still WRONG. This is a bug that needs to be fixed PRONTO. I am going to open a support case at Xilinx just as soon as their web site decides it wants come back to life. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25584
"Austin Franklin" <austin@darkroom98.com> writes: > Completely different issue. The instruction set is not patented, nor can > it be. Well, practically speaking, anything you can sneak past a patent office clerk can get registered, then it's up to the competitors to spend millions of dollars proving that it's not a valid patent.Article: 25585
Martin Usher wrote: > > > 2) Did they patent the instruction menomic or what the instruction did? If > its the latter then a patent has been issued for an algorithm. I do hope its > not a commonly employed one - I can't think of any operations at the > register level that haven't been implemented in some machine or another over > the last five decades. It not legal, but it should be legal to patent algorithms assuming you actually create a significantly new algorithm which is nontrivial to say the least. A new algorithm is a significant contribution to the world, and it would be wonderful for more money to be spent on developing new algorithms. Software code on the other hand is simply the implementation of a set of algorithms and should not be patentable any more than a short story, or in the case of M$ product an library of books. Software is properly covered by copy write laws. There should be no threat of people patenting existing algorithms, since unless a person can prove they invented something first and started the patent process with reasonable dispatch, the patent is invalid. So I can't patent Quick Sort and A*, there goes that easy trillion bucks. Muddy > > > 4) I've got a real 'thing' about people who patent bullshit things, > especially if they really believe that they invented this stuff. It takes a > special combination of arrogance and ignorance to believe that you have > truly invented something basic in our trade. They need to humble up, learn a > bit, and maybe work hard enough to actually invent something new. Until Americans acknowledge that the Government needs truly qualified people and that to get them will cost real money these problems will continue. You can't expected an agency forced to staff its offices with engineers that are paid 20-30% less than private industry, and got C's in school to be able to monitor the volume of patent applications they receive.Article: 25586
David Kessner wrote: > Martin Usher wrote: > > > > > > > This is not correct... At least not according to MIPS's lawyers. MIPS is > > > currently suing Lexra for doing software emulation of some patented > > > instructions (LWL, LWR, SWL, and SWR to be exact). Of course > > > Lexra's lawyers would disagree. > > > > > 1) What do these instructions do? (They look like 'word shift' type > > operations....) > > They are "Load Word Left/Right" and "Store Word Left/Right". They are > used when loading & storing words that are not aligned on a word boundary. > > > 2) Did they patent the instruction menomic or what the instruction did? If > > its the latter then a patent has been issued for an algorithm. I do hope its > > not a commonly employed one - I can't think of any operations at the > > register level that haven't been implemented in some machine or another over > > the last five decades. > > They patented what the instruction did. One could argue that they didn't > patent an algorithm-- only a way of doing an algorithm. These instructions > are basically do a load-shift-and-or. We could do these instructions using > those standard 4 instructions, but the patent covers doing them in a single > instruction. um... doesn't motorola have such an instruction in the 680x0 series? DavidArticle: 25587
Article: 25588
I have a XCV50 design with internal noise. CLBs changing state when they shouldn't. Could this be caused by noise from unused IOBs. Do the unused IOBs need to be configured in a certain way ? If so how ? Thanks Simon wrote: If you have a floating input, especially a control pin, it could cause weird problems. Data dependent noise could then activate some function that causes the symptoms described below. -Simon Ramirez, Consultant -Synchronous Design, Inc.Article: 25589
Ya know I'm having that problem with of all things a XC95108. You can even see the noise on the clock output pin. I changed the synth to not "demorgan" or whatever it does to reduce space and problem went away.. course design needs 33% more space! These tool sets are annoying me to no end! If PADS PCB (the other EDA software I use regularly) had as many issues it would never have made it to where it has... Thank god Xilinx does not make chips like they make there toolsets! Hawker Dan wrote: > > I have a XCV50 design with internal noise. CLBs changing state when they > shouldn't. > > Could this be caused by noise from unused IOBs. Do the unused IOBs need to > be configured in a certain way ? If so how ? >Article: 25590
Dan,
I do not believe that unused IOBs need to be configured. Xilinx takes
care of that for us.
Can you tell us a little bit more about your internal noise? How do
you know it is internal noise that is causing the problem? You can't see
internal noise in a simulation (unless you are really good!). So if you are
seeing funnies in the lab, you may be attributing the problem to internal
noise when it really is something else. Is the FPGA well grounded and
decoupled?
-Simon Ramirez, Consultant
-Synchronous Design, Inc.
"Dan" <daniel.deconinck@sympatico.ca> wrote in message
news:U7aw5.237825$Gh.5569242@news20.bellglobal.com...
> I have a XCV50 design with internal noise. CLBs changing state when they
> shouldn't.
>
> Could this be caused by noise from unused IOBs. Do the unused IOBs need to
> be configured in a certain way ? If so how ?
>
> Thanks
>
>
>
> Simon wrote:
> If you have a
> floating input, especially a control pin, it could cause weird problems.
> Data dependent noise could then activate some function that causes the
> symptoms described below.
> -Simon Ramirez, Consultant
> -Synchronous Design, Inc.
>
>
>
>
>
>
Article: 25591
Hawker,
You are not the first to make the statement below (except others used
"their").
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"Hawker" <Hawker@connriver.net> wrote in message
news:39C131EC.EFFDB7C4@connriver.net...
> Thank god Xilinx does not make chips like they make there toolsets!
Article: 25592
Andy,
The ultimate and most elegant fix is to switch to Synplicity.
-Simon Ramirez, Consultant
-Synchronous Design, Inc.
"Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message
news:8pr7ck$1s55$1@noao.edu...
> File this under "bug in v3.4." Or file it under "FPGA Express is too
> stupid to live." Or file it under "Why haven't they figured out the
> goddamn architecture yet?"
>
> Here's the scenario. I'm doing a little experiment. Target
> architecture is Spartan and 4KXLA; the problem is the same for both.
> Most of my flops are clocked on the rising edge. One of the things I
> did was to have a handful of flops clocked on the falling edge.
> Normally, placing a period constraint on the clock is all that's
> required; map and p&r should go, "Ah! two-phase clock" and do the right
> thing.
>
> p&r runs, and the report at the end complains that there's skew in the
> design due to something not using a global clock net, and the skew
> wasn't analyzed. OK, run trace with the skew option. Ooops -- there's
> a bunch of flops with like 4.8 ns clock skew (100 MHz period constraint)
> and clocked from N1964_BUFGed. Weird.
>
> Poking around with FPGA Editor (which is really useful when you're
> trying to figure out just what the hell the tools did), turns out that
> N1964_BUFGed is the clock net for the falling-edge clocked flops. Right
> then, I knew exactly what the problem was:
>
> FPGA Express 3.4 is too stupid to realize that the CLB HAS A
> CLOCK-POLARITY MUX RIGHT IN FRONT OF THE FLOP SO IT DOESN'T NEED TO USE
> A CLB TO INVERT THE CLOCK! At least it knew enough to route the output
> of the CLB inverter to a BUFGLS, but it's still WRONG.
>
> This is a bug that needs to be fixed PRONTO.
>
> I am going to open a support case at Xilinx just as soon as their web
> site decides it wants come back to life.
>
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u
>
Article: 25593Easy big fella... I am one of those ones who made some 'C's in college but I turned out fairly decent. Dang, now I have a complex! -Al Arduengo Motorola SPS / Digital Audio Organization Robert Posey <muddy_take_out_this@raytheon.com> writes: > Until Americans acknowledge that the Government needs truly qualified people > and that to get them will cost real money these problems will continue. You > can't expected an agency forced to staff its offices with engineers that > are paid 20-30% less than private industry, and got C's in school to be > able to monitor the volume of patent applications they receive.Article: 25594
One of the electronics magazine recently had a very good overview of all different family, parts, etc. I think it was EDN (probably about a month ago). And, btw, Lattice, not Altera, has the biggest CPLDs: 1080 macrocells and over 1400 registers. They are expensive though. Mark Johan Petersson wrote: > > Hi there, > > why don't you give it a try at > > www.xilinx.com > > or > > www.altera.com ??? > > Xilinx stuff is good for most cpld designs I think. Ericsson have good > experience > from using them in a couple of projects. > If you are a cpld-fetishist and need something HUGE, you should turn to > Altera. I guess they have the largest cpld's around - but they are VERY > expencive, like $100 or so for their largest - beware! > > Good luck, > Johan > > Mostafa Halas wrote: > > > > Hi,i want to know the number of registers and system gates for various CPLD products.Article: 25595
> Hi, I'm interested by pictures compressions, if someone know how to do a DCT > into an FPGA i take all what you have !! Hi, We sell a variety of image compression cores (including DCT) for FPGA and ASIC. The cores have been proved in silicon in various technologies and references are available. The full JPEG codec is now part of a soon to be released product for the mass market. Please visit our web site for more information and a datasheet. > Thx Regards, Enzo ----------------------------------------------------------- Vincenzo Liguori Ocean Logic Pty Ltd PO BOX 768 Manly NSW 1655 Australia Ph : +61-2-99054152 Fax : +61-2-99050921 WWW : http://www.ocean-logic.comArticle: 25596
Hi! I'm a student of Mondragon University and I=B4m working with Xilinx Foundation. I want to practice boundary scan, and I don=B4t know if I can= do it with a Paralle Download III cable. Can anybody help me,please?Article: 25597
I want to implement a 32 bit/33Mhz PCI bus master in a SpartanII fpga and am hesitating between buying the LogiCORE or doing it myself. In our last design we used an PLX chip to interface an Hitachi SH3 to the PCI bus, but we found all kind of problems in the PLX chip itself and in interfacing it to the SH3. As I understand it the price of the DO-DI-PCI32-S kit just dropped to $1995, so that is not much of a problem. However if we want to move up to Virtex-E the price goes up to $4995. I'm more worried about the flexibility of the core and if in the end it will save you time or just cost you time. We have already finished two SpartanII designs running at 50Mhz and I also did a PCI bus arbiter in a XC4000XL, so we feel quite at home both with the fpgas and the PCI bus. Any experiences with the LogiCORE or pros and cons of doing it yourself? Jean-Paul Smeets jeanpaul@ellips.nl J.P. Smeets business: Ellips Woenselsestr 352A 5623 EG Eindhoven tel: +31-40-2456540 fax: +31-40-2467183 email: jeanpaul@ellips.nl home: Loondermolen 23 5612 MH Eindhoven tel: +31-40-2465105 email: jpsmeets@xs4all.nlArticle: 25598
ABP wrote: > Hi, > > I need some "light" on "hardware compatibility and patent infringement". > Since Transmeta presented his Crusoe chip I've had a few doubts about > this issue. I would much appreciate any information on the following > points you could give: > > 1. Is Transmeta's SOFTWARE approach to the manipulation of x86 > instructions set what avoids the violation of patents' rights? If that's > right, I understand that patent infringement is only possible when there > is a hardware implementation. > > 2. In general (for any kind of processor), What's the way to design a > hardware device compatible with the instruction set of another processor > without infringement of patents? > > 3. If someone implements a processor compatible with the instruction set > of another processor but without copying anyting else from that original > processor > a part from the original instruction set, will that be patent > infringement? > > Although I've been looking quite thoroughly on the web for information > on patents for electronics design (the technical side of the subject) > I've had little success. Can anyone, please, point me to a good source > of information on this subject. > > Thank you all very much for your time. > > A. Petit My layman's take on this (though I did some following of the Intel et al CPU wars some years back) is that Transmeta is somewhat protected from patent violations by the fact it is using fab labs of companies that have patent cross-licensing agreements with Intel, or have acquired them by purchasing companies that had these. I would not be surprised, however, if Transmeta sales start to eat into Intel's sales, Intel's lawyers will file something. Even if Intel doesn't win, it can really wreck havoc on a small company like Transmeta to have its the bulk of its sales/marketing/managment and engineering talent sitting in a courtroom defending its technology and its products rather than working back at the company making it a sales success. Sincerely, MarcW.Article: 25599
In article <39BDE627.FF408617@no-spam.calweb.com>, Peter Hanely <hanelyp@no-spam.calweb.com> wrote: >My impression is that you can't patent an instruction set. Then again, >a lot of patents have been granted that are plain stupid. >In your favor, there are several Intel clone chips, that Intel would love >to shut down if they could. I believe Intel has some patents on the IA64 ISA, but then there are some significant new and novel features on it. -- Nicholas C. Weaver nweaver@cs.berkeley.edu
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