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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
We are seeking a motivated individual to participate in a joint Chinese University of Hong Kong and Imperial College project on implementing floating point systems using field programmable gate array (FPGA) devices. The successful applicant should have a Bachelors or higher degree in Computer Engineering, Electrical Engineering (or similar) and experience in digital design. Familiarity with FPGAs and VHDL are desirable but not mandatory. He/she will be based at the Chinese University and can work towards a postgraduate Masters or PhD degree as part of this project. The position is also suitable for a postdoctoral fellow. For further information, please contact Profs. Philip Leong (phwl@cse.cuhk.edu.hk) or Wayne Luk (wl@doc.ic.ac.uk).Article: 44926
Hello, Since I have successfully tried the VirtexDS for different demo. However I still cannot successfully connect the real board (XCV300 pq240or XCV800 hq240 by XESS) Since I've followed the instruction that save the xsvJNI.dll file and download vir.svf file. Still the error message from XHWIF "Could not download bitstream packet 10 to device 0. Exiting. (-686)", from BoardScope "Configuration error 0". I can aware of that the led on the board has a transient flash while printing the error message. Can you give me some idea what is going wrong? And how can I successfully connect the board with JBits? Thanks Terrence Mak Systems Engineering and Engineering Department Chinese University of Hong KongArticle: 44927
Peter Alfke wrote:
>
> What a tempest in a tea-pot!
> Kevin just got carried away and did not remember the original
> question:
>
> " ...I would try converting a design using free Xilinx web tools to
> one using free Altera web tools...."
>
> That's why I referred to Xilinx as the "original". Kind of interesting
> that somebody instinctively associates "original" with Xilinx...
>
Peter, I assumed you were talking in marketer's language,
therefore, I assumed the word "original" meant, "We (Xilinx) are the
first firm that came up with a concept of an FPGA, so we are the
original."
However, now I see what you meant by "original."
> More fundamentally:
> Xilinx and Altera are arch-competitors, and as such, there is no love
> lost between us. The user community should rejoyce, for this
> competition brings them faster innovation and probably more
> competitive prices.
> It is marketing's job to orchestrate the selling, and to give the
> sales force appropriate technical and commercial information to win
> any design ( if at all possible ). Nobody should criticize that
> marketing puts its best foot forward, and that marketing and sales are
> eager to point out the weak spots and flaws of the competition. You as
> a user need that information, and who else would provide it?
>
> Honesty is a separate issue. Marketing should never deliberately
> spread erroneous information about the competition. That is unethical,
> stupid, and will inevitably backfire sooner or later.
Okay, I will take back what I said previously that Xilinx guys
shouldn't criticize other firms in this newsgroup, but before calling
certain Xilinx features as "powerful unique features," you may want to
check the competition's datasheets because your competitors do add
certain features that were once thought as Xilinx original features.
Looking at several Altera datasheets, Altera has had Clock Enable since
FLEX10K, and DCI equivalent feature has been added to Stratix if I am
correct.
> Just like any
> statement that the new 3.125 gigabit transceivers in Virtex-IIPro
> "don't work" is a completely wrong fabrication. They work 100%, have
> always worked from the day we received first silicon, and we have many
> sophisticated and experienced customers who have evaluated them, and
> can testify to the robustness of the design, driving signals 50 cm
> through two connectors while maintaining an acceptable eye pattern.
>
Who said Virtex-II Pro's 3.125 gigabit transceivers don't work?
Who started such a rumor?
> End of soapbox, and thanks for all the kind support.
> And Kevin, you are once more forgiven for your hasty conclusions.
>
> Y'all have a happy and safe Fourth of July !
>
> Peter Alfke
>
>
>
I didn't ask to be forgiven, but thanks for clarifying your
position.
No, I am not mad.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44928Hi, Ben, Would you prefer the feedback to be via a E-mail to you or to the News Groups? CRS ben cohen wrote: > Am working on a paper for 2002 MAPLD conference, and would like to > hear your feedback from your experiences on "lessons learned" in you > use of HDL, tools, management(?), EDA vendors, chips, synthesis, TBs, > code reviews, etc. > I will share the results into a PPT presentation. > Thanks, > Ben > ---------------------------------------------------------------------------- > Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 > http://www.vhdlcohen.com/ vhdlcohen@aol.com > Author of following textbooks: > * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn > 0-9705394-2-8 > * Component Design by Example ", 2001 isbn 0-9705394-0-1 > * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn > 0-7923-8474-1 > * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn > 0-7923-8115 > ------------------------------------------------------------------------------Article: 44929
Well yes, but 10K in the clock enable steals one of the LUT inputs, so if
you use clock enable, your logic is reduced to a 3 input function. In the
case of arithmetic where using the carry chain breaks the LUT into a pair of
3 LUTs with one input dedicated to carry, using the clock enable reduces the
logic to a one input arithmetic function (no too usful for anything other
than increment, decrement or add a constant.
Kevin Brace wrote:
>
> Looking at several Altera datasheets, Altera has had Clock Enable since
> FLEX10K, and DCI equivalent feature has been added to Stratix if I am
> correct.
>
> > Just like any
> > statement that the new 3.125 gigabit transceivers in Virtex-IIPro
> > "don't work" is a completely wrong fabrication. They work 100%, have
> > always worked from the day we received first silicon, and we have many
> > sophisticated and experienced customers who have evaluated them, and
> > can testify to the robustness of the design, driving signals 50 cm
> > through two connectors while maintaining an acceptable eye pattern.
> >
>
> Who said Virtex-II Pro's 3.125 gigabit transceivers don't work?
> Who started such a rumor?
>
> > End of soapbox, and thanks for all the kind support.
> > And Kevin, you are once more forgiven for your hasty conclusions.
> >
> > Y'all have a happy and safe Fourth of July !
> >
> > Peter Alfke
> >
> >
> >
>
> I didn't ask to be forgiven, but thanks for clarifying your
> position.
> No, I am not mad.
>
> Kevin Brace (In general, don't respond to me directly, and respond
> within the newsgroup.)
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44930Are you sure about the reduced capability of the 10K parts when using the CE with arithmetic? I have worked with these parts and I don't remember the adders being so limited. If I remember correctly, you can use all three inputs as addend A, addend B, carry and use the fourth input for the CE. It is when you want to do two input arithmetic and have a load or reset that things get sticky. Ray Andraka wrote: > > Well yes, but 10K in the clock enable steals one of the LUT inputs, so if > you use clock enable, your logic is reduced to a 3 input function. In the > case of arithmetic where using the carry chain breaks the LUT into a pair of > 3 LUTs with one input dedicated to carry, using the clock enable reduces the > logic to a one input arithmetic function (no too usful for anything other > than increment, decrement or add a constant. > > Kevin Brace wrote: > > > > > Looking at several Altera datasheets, Altera has had Clock Enable since > > FLEX10K, and DCI equivalent feature has been added to Stratix if I am > > correct. > > > > > Just like any > > > statement that the new 3.125 gigabit transceivers in Virtex-IIPro > > > "don't work" is a completely wrong fabrication. They work 100%, have > > > always worked from the day we received first silicon, and we have many > > > sophisticated and experienced customers who have evaluated them, and > > > can testify to the robustness of the design, driving signals 50 cm > > > through two connectors while maintaining an acceptable eye pattern. > > > > > > > Who said Virtex-II Pro's 3.125 gigabit transceivers don't work? > > Who started such a rumor? > > > > > End of soapbox, and thanks for all the kind support. > > > And Kevin, you are once more forgiven for your hasty conclusions. > > > > > > Y'all have a happy and safe Fourth of July ! > > > > > > Peter Alfke > > > > > > > > > > > > > I didn't ask to be forgiven, but thanks for clarifying your > > position. > > No, I am not mad. > > > > Kevin Brace (In general, don't respond to me directly, and respond > > within the newsgroup.) > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44931
Correct. Only certain banks support 3.3v I/O. Guerre wrote: > Am I reading the data sheet correctly? Is it true that most of the pins are > not 3.3 volt tolerant on the Pro parts??!? Arrrgh! > > -- > --00-- > GuerreArticle: 44932
Yes, The CE comes off D1, which is one of the two Lut addresses left available in
arithmetic mode. D3 is used for the carry in and D4 is available for register
packing if you don't use the register for the arithmetic function. If you use the
CE, the software places the register in a different LE than the carry chain logic,
which kills the timing.
rickman wrote:
> Are you sure about the reduced capability of the 10K parts when using
> the CE with arithmetic? I have worked with these parts and I don't
> remember the adders being so limited. If I remember correctly, you can
> use all three inputs as addend A, addend B, carry and use the fourth
> input for the CE.
>
> It is when you want to do two input arithmetic and have a load or reset
> that things get sticky.
>
> Ray Andraka wrote:
> >
> > Well yes, but 10K in the clock enable steals one of the LUT inputs, so if
> > you use clock enable, your logic is reduced to a 3 input function. In the
> > case of arithmetic where using the carry chain breaks the LUT into a pair of
> > 3 LUTs with one input dedicated to carry, using the clock enable reduces the
> > logic to a one input arithmetic function (no too usful for anything other
> > than increment, decrement or add a constant.
> >
> > Kevin Brace wrote:
> >
> > >
> > > Looking at several Altera datasheets, Altera has had Clock Enable since
> > > FLEX10K, and DCI equivalent feature has been added to Stratix if I am
> > > correct.
> > >
> > > > Just like any
> > > > statement that the new 3.125 gigabit transceivers in Virtex-IIPro
> > > > "don't work" is a completely wrong fabrication. They work 100%, have
> > > > always worked from the day we received first silicon, and we have many
> > > > sophisticated and experienced customers who have evaluated them, and
> > > > can testify to the robustness of the design, driving signals 50 cm
> > > > through two connectors while maintaining an acceptable eye pattern.
> > > >
> > >
> > > Who said Virtex-II Pro's 3.125 gigabit transceivers don't work?
> > > Who started such a rumor?
> > >
> > > > End of soapbox, and thanks for all the kind support.
> > > > And Kevin, you are once more forgiven for your hasty conclusions.
> > > >
> > > > Y'all have a happy and safe Fourth of July !
> > > >
> > > > Peter Alfke
> > > >
> > > >
> > > >
> > >
> > > I didn't ask to be forgiven, but thanks for clarifying your
> > > position.
> > > No, I am not mad.
> > >
> > > Kevin Brace (In general, don't respond to me directly, and respond
> > > within the newsgroup.)
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44933
This is an old bug in Synopsys software. I would
be very suprised if it still exists. It certainly does
not exist in other commonly used synthesis software.
cfk wrote:
> According to the Xilinx website, one cannot code an N-bit, 2-input adder w/
> carry-in simply by writing:
>
> assign {Cout,SUM} = A + B + Cin;
>
> (as my partner, a very Verilog-literate person naively would), where SUM, A,
> and B are N-bit numbers, and Cin is a one-bit carry-in.
>
> Instead, they insist that one write:
>
> assign{Cout, SUM, dummy} = {A, Cin} + {B, Cin};
>
> I am told that this stems from an inability to entertain a carry-in
> properly.
>
> Question: Does this restriction apply to the ISE 4.02 / Virtex E
> 2000-6BG560 software/hardware combination , or merely
> to FPGA Express or older versions?
>
>
>
>
Article: 44934>News Groups? Newsgroup postingsArticle: 44935
Is there a good (or even jsut decent half-assed) model for virtex delay as a function of horizontal and vertical distance floating around? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 44936
Ray Andraka wrote:
>
> I don't think Peter was being malicious, rather I think there was some reading
> between the lines that is not justified.
I assumed Peter was using marketer's definition of "original,"
which I assumed meant Xilinx is the first (original) company which came
up with the concept of an FPGA.
> There are significant penalties, as
> pointed out by others, to doing a one size fits all design. The 10K has a clock
> enable, but in order to use it you have to give up a LUT input. Also, there are
> significant differences in the arithmetic implementation that may cause a design
> to take up 2x or more area in 10K than it does in Xilinx (Let's keep the
> comparison between devices of the same vintage please!). The Altera LUT is
> reduced to a pair of 3 LUTs for arithmetic (one ofr sum, one for carry), which
> limits you to a 2 input arithmetic function in one layer of LUTs. In any of
> Xilinx's parts going back to the 4K, the carry chain is added logic, so you always
> have the full 4 LUT available.
I am aware that when the CE input of a FF is used in FLEX10K
families, LE's 4-input LUT becomes a 3-input LUT, but the question I
raised was whether or not a FF with a CE input is a "powerful unique
feature" of Xilinx (The original poster was porting a design from Xilinx
to Altera.), considering that at least Altera had it since FLEX10K.
I was not discussing who has implemented it better.
> Also, the 10K IOBs can only be registered in one
> direction at a time, where any of the xilinx devices have registers in both
> directions, so bidirectional I/O favors xilinx.
There is no doubt that 3 FFs per IOB make Xilinx devices get
good bidirectional I/O performance without much effort (i.e.,
floorplanning), but I will rather see it as it takes more effort (Have
to fight with Quartus II's floorplanner/fitter.) to get good
bidirectional I/O performance with Altera.
> Altera 10K has the EAB memories,
> which the xilinx devices of the same vintage do not have (xilinx has distributed
> RAM using CLBs which can actually be more useful in many applications). Altera's
> 10K is a row/column more or less global route structure which tends to give more
> consistent timing with less physical synthesis effort at the price of performance
> for certain designs.
>
> The point is, in order to get performance or density in any family, you need to
> tailor the design toward that family. For example, in an arithemtic design in
> ALtera, you want to avoid clock enabled flip-flops like the plague, so you do the
> block diagram design in a different manner. In Xilinx, the routing favors nearest
> neighbor, so you structure the design to be linear to get the most performance.
>
>
Ray, your advise suggests that whoever targeting FLEX10K should
avoid using CE FFs, but when people use HDL, how easy is it to avoid
that considering that synthesis tool is the one who is going to
automatically infers CE FFs.
Should people targetting FLEX10K use schematics instead of HDL?
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44937
Ray Andraka wrote:
>
> Well yes, but 10K in the clock enable steals one of the LUT inputs, so if
> you use clock enable, your logic is reduced to a 3 input function. In the
> case of arithmetic where using the carry chain breaks the LUT into a pair of
> 3 LUTs with one input dedicated to carry, using the clock enable reduces the
> logic to a one input arithmetic function (no too usful for anything other
> than increment, decrement or add a constant.
>
I am aware that when the CE input of a FF is used in FLEX10K
families, LE's 4-input LUT becomes a 3-input LUT, but the question I
raised was whether or not a FF with a CE input is a "powerful unique
feature" of Xilinx (The original poster was porting a design from Xilinx
to Altera.), considering that at least Altera had it since FLEX10K.
I was not discussing who has implemented it better.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44938
I'm not advocating schematic over HDL, not any more anyway. Synthesis tools for the
most part have a switch that can enable or disable use of clock enables. In the case of
synplicity, you can use the syn_useenables attribute. Furthermore, you can easily avoid
ce's in your code. The trick i s basically one that I mentioned here a week or two ago
where you use a clock enable at the front and tail of your pipeline but not in the
middle registers (write your code so that the data always flows through those
registers). In the case of Altera, you just make sure the front and tail are not
arithmetic, and you'll do fine.
Kevin Brace wrote:
> Ray Andraka wrote:
> >
> > I don't think Peter was being malicious, rather I think there was some reading
> > between the lines that is not justified.
>
> I assumed Peter was using marketer's definition of "original,"
> which I assumed meant Xilinx is the first (original) company which came
> up with the concept of an FPGA.
>
> > There are significant penalties, as
> > pointed out by others, to doing a one size fits all design. The 10K has a clock
> > enable, but in order to use it you have to give up a LUT input. Also, there are
> > significant differences in the arithmetic implementation that may cause a design
> > to take up 2x or more area in 10K than it does in Xilinx (Let's keep the
> > comparison between devices of the same vintage please!). The Altera LUT is
> > reduced to a pair of 3 LUTs for arithmetic (one ofr sum, one for carry), which
> > limits you to a 2 input arithmetic function in one layer of LUTs. In any of
> > Xilinx's parts going back to the 4K, the carry chain is added logic, so you always
> > have the full 4 LUT available.
>
> I am aware that when the CE input of a FF is used in FLEX10K
> families, LE's 4-input LUT becomes a 3-input LUT, but the question I
> raised was whether or not a FF with a CE input is a "powerful unique
> feature" of Xilinx (The original poster was porting a design from Xilinx
> to Altera.), considering that at least Altera had it since FLEX10K.
> I was not discussing who has implemented it better.
>
> > Also, the 10K IOBs can only be registered in one
> > direction at a time, where any of the xilinx devices have registers in both
> > directions, so bidirectional I/O favors xilinx.
>
> There is no doubt that 3 FFs per IOB make Xilinx devices get
> good bidirectional I/O performance without much effort (i.e.,
> floorplanning), but I will rather see it as it takes more effort (Have
> to fight with Quartus II's floorplanner/fitter.) to get good
> bidirectional I/O performance with Altera.
>
> > Altera 10K has the EAB memories,
> > which the xilinx devices of the same vintage do not have (xilinx has distributed
> > RAM using CLBs which can actually be more useful in many applications). Altera's
> > 10K is a row/column more or less global route structure which tends to give more
> > consistent timing with less physical synthesis effort at the price of performance
> > for certain designs.
> >
> > The point is, in order to get performance or density in any family, you need to
> > tailor the design toward that family. For example, in an arithemtic design in
> > ALtera, you want to avoid clock enabled flip-flops like the plague, so you do the
> > block diagram design in a different manner. In Xilinx, the routing favors nearest
> > neighbor, so you structure the design to be linear to get the most performance.
> >
> >
>
> Ray, your advise suggests that whoever targeting FLEX10K should
> avoid using CE FFs, but when people use HDL, how easy is it to avoid
> that considering that synthesis tool is the one who is going to
> automatically infers CE FFs.
> Should people targetting FLEX10K use schematics instead of HDL?
>
> Kevin Brace (In general, don't respond to me directly, and respond
> within the newsgroup.)
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44939Kevin Brace wrote: > > I am aware that when the CE input of a FF is used in FLEX10K > families, LE's 4-input LUT becomes a 3-input LUT, but the question I > raised was whether or not a FF with a CE input is a "powerful unique > feature" of Xilinx (The original poster was porting a design from Xilinx > to Altera.), considering that at least Altera had it since FLEX10K. I doubt even the worst 'marketdroid' would claim that CE is unique, it has been around since 74161 and CD4076 days.. :) -jgArticle: 44940
Hello all -- I am embarking on a new FPGA project, and I was hoping to get some recommendations for the FPGA, prototyping board, or programming environment. Back in school I used Xilinx FPGA's with XESS prototyping boards and Xilinx Foundation software. I've liked this set-up, but from what I can tell looking at the competition, XESS's boards are pricey, aimed at the educational market, and even their latest boards use the Virtex FPGA that seems to be obsolete at this point. My new project constraints are: - ~300KB ROM - 132 Kb (16.5 KB) Block Memory or Distributed memory (I'm a bit fuzzy on which one I should be using) - ~300 KB of off-chip static RAM - 100-200k gates for logic - enough room for error in case any of the above are wrong - budget for prototype of about $1000 including software (I already have a PC) My questions are: 1) The maximum Block RAM or Distributed RAM on Xilinx's website for the Virtex-II are based on if you used the whole FPGA for RAM and not logic, right? These FPGA's don't have dedicated memory cells, do they? 2) How does one make Block RAM or Distributed RAM without using CORE Generator? I'll be programming in Verilog, but I'm not sure how to tell the compiler I want to make a Block RAM or Distrbuted RAM. I can't afford Foundation for $2500, but maybe BaseX is available for $99 on some sort of promotion (saw this earlier on the NG)? 3) What clock speeds are typical for most people using FPGA's? A few years ago I was making designs in the 25-50 MHz range on Virtex and Spartan FPGA's. I saw some people claiming 380 MHz for designs. A typical pipeline stage in my design might have a 16-bit adder. Is the -4, -5, or -6 speed rating important for me? (I'm not trying to super-optimize here... just get a workable design without spending more $ than I have to.) Along these lines, I saw people on this NG referring to hand-optimization. Does the Xilinx software let you do this? I've always just hit "implement" and not much else... I was leaning towards the 250k gate Virtex II since I could use it with Xilinx Web Pack (for free :-)) but I couldn't find a protoboard out there for this chip -- let alone one that has agreeable features and price. If I stuck with what I'm used to, I could get Xess's board based on the 300k gate Virtex for $900 with 2MB of static RAM... but something tells me I could do better for my money -- if this would even accomodate my design (I'm not sure). So I'm totally open for suggestions, advice, info, etc.... any you could give would me much appreciated. Thanks! Cheers, JohnArticle: 44941
John Hovell wrote:
> Hello all --
>
> I am embarking on a new FPGA project, and I was hoping to get some
> recommendations for the FPGA, prototyping board, or programming environment.
>
> Back in school I used Xilinx FPGA's with XESS prototyping boards and
> Xilinx Foundation software. I've liked this set-up, but from what I can
> tell looking at the competition, XESS's boards are pricey, aimed at the
> educational market, and even their latest boards use the Virtex FPGA
> that seems to be obsolete at this point.
I'm not sure they're quite obsolete, but I wouldn't use a 2.5v VIrtex for a new
design unless it is a design using a QPRO (military) version of the part. The
spartanII's still have life left, and can be had considerably cheaper than the
Virtex line.
>
>
> My new project constraints are:
> - ~300KB ROM
> - 132 Kb (16.5 KB) Block Memory or Distributed memory (I'm a bit fuzzy
> on which one I should be using)
> - ~300 KB of off-chip static RAM
> - 100-200k gates for logic
> - enough room for error in case any of the above are wrong
> - budget for prototype of about $1000 including software (I already
> have a PC)
>
> My questions are:
> 1) The maximum Block RAM or Distributed RAM on Xilinx's website for the
> Virtex-II are based on if you used the whole FPGA for RAM and not logic,
> right? These FPGA's don't have dedicated memory cells, do they?
You might peruse the data sheets. The VIrtexII has 16Kbit (18Kbit if used with
parity) block memories that can be each set up as 1,2,4,9,18 or 36 bits wide.
These are dula port memory blocks. There are 4 to 144 of them in a device
(XC2V40 - XC2V6000).
>
>
> 2) How does one make Block RAM or Distributed RAM without using CORE
> Generator? I'll be programming in Verilog, but I'm not sure how to tell
> the compiler I want to make a Block RAM or Distrbuted RAM. I can't
> afford Foundation for $2500, but maybe BaseX is available for $99 on
> some sort of promotion (saw this earlier on the NG)?
Some synthesizers will infer the memory. You can also instantiate the unisim
library primitives, and that way you are not dependent on the synthesizer and
you are able to add placement and initialization in your code..
>
>
> 3) What clock speeds are typical for most people using FPGA's? A few
> years ago I was making designs in the 25-50 MHz range on Virtex and
> Spartan FPGA's. I saw some people claiming 380 MHz for designs. A
> typical pipeline stage in my design might have a 16-bit adder. Is the
> -4, -5, or -6 speed rating important for me? (I'm not trying to
> super-optimize here... just get a workable design without spending more
> $ than I have to.) Along these lines, I saw people on this NG referring
> to hand-optimization. Does the Xilinx software let you do this? I've
> always just hit "implement" and not much else...
The 16 bit adder is going to set your upper limit in most cases. For the 2.5v
virtex-4/ spartanII-5, that is about 160 MHz tops with careful design and
placement. For the VirtexE-8, around 260 MHz, but wtch the SRL16 minimum pulse
widths...you hit that before you hit the limit on a 16 bit carry chain.
>
>
> I was leaning towards the 250k gate Virtex II since I could use it with
> Xilinx Web Pack (for free :-)) but I couldn't find a protoboard out
> there for this chip -- let alone one that has agreeable features and
> price. If I stuck with what I'm used to, I could get Xess's board based
> on the 300k gate Virtex for $900 with 2MB of static RAM... but something
> tells me I could do better for my money -- if this would even accomodate
> my design (I'm not sure).
I fyou can fit your design into a spartanII or spartanIIE, you will get into a
cheaper board. There are a number of SpartanII boards out there for quite a
bit less than the $900. Not many of the cheap boards have RAM though.
>
>
> So I'm totally open for suggestions, advice, info, etc.... any you could
> give would me much appreciated. Thanks!
>
> Cheers,
> John
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44942If you are using Matlab/Simulink, Altera DSP Builder provides a graphical library of fixed-point modules which maps to a VHDL library (dspbuilder.vhd). This library covers : Signed Integer, Unsigned Integer and Signed Binary Fractionnal types http://www.altera.com/products/software/system/dsp/dsp-builder.html Philippe "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:<RrlOrKBJCHA.4736@lucy.doulos.com>... > > -----Original Message----- > > From: John Williams [mailto:j2.williams@qut.edu.au] > > > Does anybody know of a synthesisable VHDL package/library for > > generalised fixed point arithmetic? > > > > I'm picturing a scheme whereby you specify the number of > > fractional and > > integer bits in the operands and result, and it handles the shifts and > > bit padding etc seamlessly. Supported ops would be addition, > > subtraction, multiplication, with signed and unsigned > > options, that sort > > of thing (basically an extension to the existing signed/unsigned > > support). > > Adelante (www.adelantetechnologies.com) have A/RT Library > which is a C++ fixed point package, with all the benefits (?!) > of C++ type templates, and A/RT Builder which can compile the > C++ FP descriptions into VHDL. It will cost you serious money. > > It's a bit tricky in VHDL because there is nothing like C++ > or Ada type templates. We really need a std logic vector > to carry around with it some meta-data describing its fixed > point format, but of course we don't want that meta-data > to be synthesised in any way - it should just influence > compilation. > > Hey, I have a really good idea... VHDL arrays DO carry some > meta-data round with them... in their subscript range. In > ordinary VHDL-land, an UNSIGNED(7 DOWNTO 0) is entirely > equivalent to an UNSIGNED(9 DOWNTO 2). How say we invent > a new type UFIX in which the lower (right) subscript bound > determines the position of the binary point? Here's a bit > of a package to get this idea started. Right at the end there's > also a procedure AddAndTrunc() which gives some ideas about how > the return value from the "+" operator could be processed. > I suspect a suitably creative RESIZE() function could be written > to do any re-scaling you might need. > > If I'm feeling energetic I might expand this a bit over the > weekend. I can already see some potential difficulties, but > maybe it's worth the effort nonetheless... > > -------------------------------- start code snippet -------------- > --- > --- These packages describe fixed point arithmetic based around > --- the existing numeric std package. > --- > --- You need to decide the maximum number of binary-fraction digits > --- that will be used anywhere in your design, and set up the > --- CONSTANT Point to be that number. Now if you want to set up > --- a fixed-point number with (say) five integer bits and three > --- fraction bits, you declare it like this: > --- > --- SUBTYPE UFix 5 3 IS UFix(5+Point-1 DOWNTO Point-3); > --- You can sugar the syntax of constants thus: > --- CONSTANT Hogwarts Platform: UFix 5 3 := "01001" & "110"; > --- 9 . 75 > --- > --- An N-bit whole-number (integer) should then be declared > --- as UFix(N+Point-1 DOWNTO Point). > --- > --- Any subprogram that gets one of these values as an actual > --- parameter can then look at 'LEFT and 'RIGHT and use them > --- to determine the required scaling. > --- > --- Note that the choice of value for Point doesn't constrain > --- your choice of width and precision in any way, except that > --- it limits the maximum number of fraction bits that can be > --- used anywhere in your design. > > > PACKAGE fixed point config IS > CONSTANT Point : natural; > END; > > LIBRARY ieee; > USE ieee.std logic 1164.ALL; > USE ieee.numeric std.ALL; > > PACKAGE fixed point IS > > -- Unsigned fixed point > TYPE UFix IS ARRAY (natural RANGE <>) OF std logic; > -- Signed fixed point > TYPE SFix IS ARRAY (natural RANGE <>) OF std logic; > > -- Fixed point addition, unsigned > FUNCTION "+"(L, R: UFix) RETURN UFix; > > -- ... and many more ! ... > > END; > > PACKAGE BODY fixed point IS > > -- Max and Min functions needed for some of the routines > FUNCTION max(A, B: natural) RETURN natural IS > BEGIN > IF A>B THEN > RETURN A; > ELSE > RETURN B; > END IF; > END; -- max() > > FUNCTION min(A, B: natural) RETURN natural IS > BEGIN > IF A<B THEN > RETURN A; > ELSE > RETURN B; > END IF; > END; -- max() > > -- Fixed point addition, unsigned > FUNCTION "+"(L, R: UFix) RETURN UFix IS > > -- Find how much space we need > CONSTANT L max : natural := max(L'LEFT, R'LEFT); > CONSTANT R min: natural := min(L'RIGHT, R'RIGHT); > > -- Invent a suitable subtype > SUBTYPE widest IS unsigned(L max DOWNTO R min); > > -- Variables to do the calculations > VARIABLE LL, RR, SS: widest := (OTHERS => '0'); > > BEGIN > > -- Normalise both parameters > LL(L'RANGE) := unsigned(L); > RR(R'RANGE) := unsigned(R); > > -- Generate result > RETURN UFix(LL + RR); > > END; -- UFix := UFix + UFix > > -- Example of how we could exploit this functionality... > -- > PROCEDURE AddAndTrunc(L, R: in UFix; S: out UFix) IS > -- This CONSTANT declaration lets us capture the > -- subscript range created by the "+" operator. > CONSTANT SS: UFix := L+R; > BEGIN > S := SS(S'RANGE); > END; > > END; -- PACKAGE BODY fixed point; > > --- This needs to be in a separate file, ideally. > --- > PACKAGE BODY fixed point config IS > CONSTANT Point : natural := 8; > END; > ----------------------------------- end code snippet -------------- > > -- > Jonathan Bromley > HDL Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project > Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 > 1AW, UK > Tel: +44 (0)1425 471223 mail: > jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: > http://www.doulos.com > > This e-mail and any attachments are confidential and Doulos Ltd. > reserves > all rights of privilege in respect thereof. It is intended for the use > of > the addressee only. If you are not the intended recipient please delete > it > from your system, any use, disclosure, or copying of this document > is > unauthorised. The contents of this message may contain personal views > which > are not the views of Doulos Ltd., unless specifically stated.Article: 44943
I have used this software in the past to design a 3.3 to 1.5 DC/DC converter and it worked fine, (both the software and the converter). You can get it from: http://focus.ti.com/docs/tool/toolfolder.jhtml?PartNumber=SWIFT-SW#Descripti on I is good for TI parts only but ...hey...it does the job... jakab Steve Joures <sjoures@saiman.co.uk> wrote in message news:ee77a78.-1@WebX.sUN8CHnE... > I need to power a single Virtex-II device. Can anyone recommend a small footprint 1.5V DC to DC converter ? > I would prefer 3.3V input voltage, although I could use 5V.Article: 44944
Everytime I run the simulation, the ModelSim(Free version) says that my license file is invalid, such that I could not perform the simulation. I got the license file from the Xilinx, and I installed the license successfully with the License program. I am just wondering anybody has the similar situation like mine, and how can I solve the problem. Thanks.Article: 44945
Jonathan Bromley wrote: > Hey, I have a really good idea... VHDL arrays DO carry some > meta-data round with them... in their subscript range. In > ordinary VHDL-land, an UNSIGNED(7 DOWNTO 0) is entirely > equivalent to an UNSIGNED(9 DOWNTO 2). How say we invent > a new type UFIX in which the lower (right) subscript bound > determines the position of the binary point? Here's a bit > of a package to get this idea started. Right at the end there's > also a procedure AddAndTrunc() which gives some ideas about how > the return value from the "+" operator could be processed. > I suspect a suitably creative RESIZE() function could be written > to do any re-scaling you might need. That's precisely what I was thinking - I was just being lazy to see if anyone's done it before and released it! Can you assign attributes to existing types in VHDL? Basically create a subtype of std_logic_vector, and use attributes to carry around the position of the binary point? I only had time to just glance at your code, but I'm wondering, would it support varying types within a single design? What I'm thinking is that you could declare a signal with say 3 integer and 5 frac. bits, and another signal with 2 int. and 6 frac., then add them together, multiply, whatever, and the results of those operations would be automatically created to be the appropriate type. Maybe I'm asking too much of VHDL (it's the C++ programmer in me coming out again!) Cheers, JonhArticle: 44946
Hi John, Perhaps you could consider the BurchED B5-Spartan2e+ board, with the latest XC2S300E device on it. This board is US$190. And the XC2S300E is supported by the free WebPACK software. http://www.burched.com.au/B5Spartan2.html BurchED boards use a modular plug-on system, for expanding the system resources, so you can add external fast SRAM http://www.burched.com.au/B5SRAM.html This module is 256KBytes, but you can plug on more than one, if necessary. You get 65,536 bits (64KBits) of block ram in the XC2S300E device. There are 16 "block ram cells" in this device. Each block ram cell has 4096 bits. With this device, you can implement up to 98,304 distributed ram bits also. This is in addition to the block ram. Hope that helps:) Cheers, Best regards Tony Burch http://www.BurchED.com Low cost FPGA boards, for System-On-Chip prototyping and education "John Hovell" <jhovell@yahoo.com> wrote in message news:3D27AF63.1040002@yahoo.com... > Hello all -- > > I am embarking on a new FPGA project, and I was hoping to get some > recommendations for the FPGA, prototyping board, or programming environment. > > Back in school I used Xilinx FPGA's with XESS prototyping boards and > Xilinx Foundation software. I've liked this set-up, but from what I can > tell looking at the competition, XESS's boards are pricey, aimed at the > educational market, and even their latest boards use the Virtex FPGA > that seems to be obsolete at this point. > > My new project constraints are: > - ~300KB ROM > - 132 Kb (16.5 KB) Block Memory or Distributed memory (I'm a bit fuzzy > on which one I should be using) > - ~300 KB of off-chip static RAM > - 100-200k gates for logic > - enough room for error in case any of the above are wrong > - budget for prototype of about $1000 including software (I already > have a PC) > > My questions are: > 1) The maximum Block RAM or Distributed RAM on Xilinx's website for the > Virtex-II are based on if you used the whole FPGA for RAM and not logic, > right? These FPGA's don't have dedicated memory cells, do they? > > 2) How does one make Block RAM or Distributed RAM without using CORE > Generator? I'll be programming in Verilog, but I'm not sure how to tell > the compiler I want to make a Block RAM or Distrbuted RAM. I can't > afford Foundation for $2500, but maybe BaseX is available for $99 on > some sort of promotion (saw this earlier on the NG)? > > 3) What clock speeds are typical for most people using FPGA's? A few > years ago I was making designs in the 25-50 MHz range on Virtex and > Spartan FPGA's. I saw some people claiming 380 MHz for designs. A > typical pipeline stage in my design might have a 16-bit adder. Is the > -4, -5, or -6 speed rating important for me? (I'm not trying to > super-optimize here... just get a workable design without spending more > $ than I have to.) Along these lines, I saw people on this NG referring > to hand-optimization. Does the Xilinx software let you do this? I've > always just hit "implement" and not much else... > > I was leaning towards the 250k gate Virtex II since I could use it with > Xilinx Web Pack (for free :-)) but I couldn't find a protoboard out > there for this chip -- let alone one that has agreeable features and > price. If I stuck with what I'm used to, I could get Xess's board based > on the 300k gate Virtex for $900 with 2MB of static RAM... but something > tells me I could do better for my money -- if this would even accomodate > my design (I'm not sure). > > So I'm totally open for suggestions, advice, info, etc.... any you could > give would me much appreciated. Thanks! > > Cheers, > John > >Article: 44947
Hello John, have a look at our 300k Spartan IIE Development platform. The board is based upon a 300k-gate Spartan-IIE, which is accompanied by the following peripherals: - 256k x 16 SRAM - 512k x 16 (1M x 8) Flash - 2 x 16 LC-display - USB interface - RS232 interface - VGA output - VG96 connector For a convenient desktop or laboratory setup, the board is powered and configured via USB. The Flash memory is used to store non-volatile configurations and data. The board fits into industry-standard 19" racks with VG96 connector. For easy expansion, there are up to 100 user I/Os wich may be assigned freely. For further information, refer to the following links: http://www.trenz-electronic.de/prod/proden12.htm http://www.trenz-electronic.de/prod/proden10.htm http://www.trenz-electronic.de/prod/ps-TE-XC2Se.pdf The board is in stock and may be ordered via our online shop. We offer discounts for orders of two or more boards. Contact us! best regards Thorsten -- Dipl.-Ing. Thorsten Trenz Trenz Electronic GmbH, Brendel 20, 32257 Buende, Germany Tel.: +49 (0) 5223 41652, Fax.: +49 (0) 5223 48945 Mailto:t.trenz@trenz-electronic.de, http://www.trenz-electronic.de Amtsgericht Bünde, HR B 1747, Geschäftsführer/CEO: Thorsten TrenzArticle: 44948
Ray Andraka <ray@andraka.com> writes: > Martin Thompson wrote: > > > Just a small hobby horse of mine, as I see too much code written in a > > strongly typed language which doesn't take advantage of the types, so > > std_logic(_vector) is used for almost everything, except constants for > > some reason... > > > > All IMHO of course! > > Martin > > Internally, that is fine, but at your component ports, you should use > std_logic and std_logic_vector for compatibility. > Do you mean at the borders of the physical FPGA, or on internal components? For the FPGA I/Os I agree, but internally, I still feel you should use a type that matches what you want to do with it. For example, a filter: the input and output values are always going to be numbers, so a numerical type should be used on the port, rather than translating to and fro. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 44949
Derrick Cheng <cdcheng@uiuc.edu> wrote: > Everytime I run the simulation, the ModelSim(Free version) says that my > license file is > invalid, such that I could not perform the simulation. > I got the license file from the Xilinx, and I installed the license > successfully with the License program. > > I am just wondering anybody has the similar situation like mine, and how can > I solve the problem. > Thanks. Did it ever work? When I first ran modelsim, it complained about a missing license file. I then registered and submitted the complete e-mail file to the license manager which picked out the part it needed. After that the complaint is gone. If you now have the problem that simulation does not work then probably you have requested a simulator feature you don't have enabled (IIRC, the starter license only allows XILINX gate level simulations). Holger -- Please update your tables to my new e-mail address: holger.veit$ais.fhg.de (replace the '$' with '@' -- spam-protection)
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