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Messages from 46650

Article: 46650
Subject: Re: Hardware Code Morphing?
From: Thomas Maslen <maslen@pobox.com>
Date: 5 Sep 02 02:18:46 GMT
Links: << >>  << T >>  << A >>
In <cd714c44.0209020625.5b892675@posting.google.com> kundi_forever@yahoo.com (Kunal) writes:
[...]
>Ok here's an idea... how about code-morphing HARDWARE? 

e.g.

	http://www.parthus.com/platforms/parthus_machstream/

It's a chunk of silicon IP for embedded devices that is used to munge (morph, 
whatever) from one data format to another.  One of the applications is JIT
compilation from Java bytecode to your main CPU's native code.  They reckon
that you get better embedded performance per Watt by putting this stuff in
silicon rather than in software.  (TransMeta might argue the opposite).

Thomas Maslen
maslen@pobox.com

Article: 46651
Subject: Re: What's wrong with clearLogic?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 05 Sep 2002 14:20:10 +1200
Links: << >>  << T >>  << A >>
rickman wrote:
> 
> Pete Ormsby wrote:
> >
> > http://www.altera.com/corporate/news_room/releases/corporate/nr-clearlogic.h
> > tml
> >
> > Leon Qin <lyqin@cti.com.cn> wrote in message
> > news:23c59085.0208210006.3cb6905a@posting.google.com...
> > > http://www.clear-logic.com/
> 
> I guess I never realized that you did not own full rights to the bit
> stream from your design...  amazing.
> 
> Does Xilinx also have that restriction?  If I want to use my bitstream
> to program an ASIC, am I prohibited?

 The FPGA industry is a little ambivalent wrt ASICs - they get
a sizeable chunk of revenue from 'ASIC development' usage, but when
that step is actually taken, they are less than comfortable with it.
 
 However, indications are that the Altera move has backfired, and 
they have annoyed users, and lost more revenue that way, than they 
were ever 'loosing' to ClearLogic.

 - jg

Article: 46652
Subject: Re: What's wrong with clearLogic?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 05 Sep 2002 14:27:34 +1200
Links: << >>  << T >>  << A >>
Kevin Brace wrote:
> 
> rickman wrote:
> >
> >
> > I guess I never realized that you did not own full rights to the bit
> > stream from your design...  amazing.
> >
> 
>   I see why you are disgusted with the ruling, and while I, too,
> don't agree with the ruling, let's say if you were an IP core vendor who
> is trying to collect royalty payment for each chip (or board) sold.
> If the licensee for some reason stops paying the royalty, wouldn't you
> have the right to sue and collect royalty from the licensee because the
> licensee's design contains the licenser's IP core?
> Also, most IP cores provided by PLD vendors prohibit conversion to an
> ASIC, unless the licensee gets a special permission.

 Of course, IP is protected separately, but this ruling made no
distinction
of IP, it was a Software-License usage issue.
 So, if you create just a 16 bit counter, with zero Altera IP, that's
still
covered.

> 
> > Does Xilinx also have that restriction?  If I want to use my bitstream
> > to program an ASIC, am I prohibited?

>         As far as I know, all PLD vendors have the restriction you are
> talking about, and I personally don't know any vendor that directly does
> a conversion from Xilinx FPGA bitstream to an ASIC.
> However, it should be perfectly legal to create an ASIC from the EDIF
> netlists generated by third party synthesis tools. (Synplify,
> LeonardoSpectrum, FPGA Compiler II, etc.)

..and this should be more efficent, than via a bit-stream, as well.

There were recent posts about 'encrypted EDIF' formats in these tools...

- jg

Article: 46653
Subject: Re: Viewing Xilinx netlist
From: Kevin Brace <kevinbraceusenet.killspam@killspam.hotmail.com>
Date: Wed, 04 Sep 2002 21:29:41 -0500
Links: << >>  << T >>  << A >>
        What I don't understand about Xilinx is that, XST of ISE 4.x can
actually generate an EDIF netlist, but Xilinx refuses to let people use
it from ISE's VHDL or Verilog GUI design flow.

http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&threadm=aceeac%249fj%241%40newsreader.mailgate.org&rnum=1&prev=/groups%3Fhl%3Den%26lr%3D%26ie%3DUTF-8%26selm%3Daceeac%25249fj%25241%2540newsreader.mailgate.org


Please, Xilinx, stop spreading the lies that XST of ISE 4.x cannot
generate and EDIF netlist.


Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)



Vikram Pasham wrote:
> 
> Rajeev,
> 
> A good place to look is XST log file. XST might have given some warnings on nets
> with multiple drivers. Also, search on support.xilinx.com for answer records on
> Ngdbuild multiple driver error messages.
> 
> ISE 5.1i provides an NGC to EDIF translator to generate a readable netlist file.
> ISE5.1i also provides a RTL schematic viewer which can be used to track such
> re-named internal nets.
> 
> -Vikram
>

Article: 46654
Subject: Re: QUARTUS II V2.1 LINUX (C) ALTERA
From: Kevin Brace <kevinbraceusenet.killspam@killspam.hotmail.com>
Date: Wed, 04 Sep 2002 21:34:13 -0500
Links: << >>  << T >>  << A >>
        Regarding the new built-in HDL compiler, can it generate an EDIF
netlist?
I often have to see or edit EDIF netlists, and if it cannot do so, then
to me, the new HDL compiler is nearly useless.


Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)



ds wrote:
> 
> Quartus II 2.1 on all
> platforms (Windows, Linux, Solaris, HP)  has a much improved and very robust
> HDL (VHDL and Verilog) extractor and synthesizer.  ModelTech sells a
> Modelsim simulator that works on Linux.
> 
> -ds
>

Article: 46655
Subject: Re: What's wrong with clearLogic?
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 04 Sep 2002 22:34:36 -0400
Links: << >>  << T >>  << A >>
Kevin Brace wrote:
> 
> rickman wrote:
> >
> >
> > I guess I never realized that you did not own full rights to the bit
> > stream from your design...  amazing.
> >
> 
>         I see why you are disgusted with the ruling, and while I, too,
> don't agree with the ruling, let's say if you were an IP core vendor who
> is trying to collect royalty payment for each chip (or board) sold.
> If the licensee for some reason stops paying the royalty, wouldn't you
> have the right to sue and collect royalty from the licensee because the
> licensee's design contains the licenser's IP core?
> Also, most IP cores provided by PLD vendors prohibit conversion to an
> ASIC, unless the licensee gets a special permission.

I could have made a mistake, but I don't think the issue is with "IP
cores".  Altera doesn't want Clearlogic to make ASICs from any
bitstreams generated by their software...

"'any semiconductor device that was made, designed, configured,
programmed or otherwise manufactured through or with the aid of any
bitstream file or other output generated by' Altera's MAX+PLUSŪ II
software"

That is a whole different animal than restricting the use of "IP
cores".  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 46656
Subject: Re: What's wrong with clearLogic?
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 04 Sep 2002 22:41:51 -0400
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> 
> rickman wrote:
> >
> > Pete Ormsby wrote:
> > >
> > > http://www.altera.com/corporate/news_room/releases/corporate/nr-clearlogic.h
> > > tml
> > >
> > > Leon Qin <lyqin@cti.com.cn> wrote in message
> > > news:23c59085.0208210006.3cb6905a@posting.google.com...
> > > > http://www.clear-logic.com/
> >
> > I guess I never realized that you did not own full rights to the bit
> > stream from your design...  amazing.
> >
> > Does Xilinx also have that restriction?  If I want to use my bitstream
> > to program an ASIC, am I prohibited?
> 
>  The FPGA industry is a little ambivalent wrt ASICs - they get
> a sizeable chunk of revenue from 'ASIC development' usage, but when
> that step is actually taken, they are less than comfortable with it.
> 
>  However, indications are that the Altera move has backfired, and
> they have annoyed users, and lost more revenue that way, than they
> were ever 'loosing' to ClearLogic.
> 
>  - jg

I thought it was odd that they could sue Clearlogic over software
licensing issues unless Clearlogic used the MAX+II package to do
something with the bitstream.  I expect it would be the customers who
were in violation of the software license, not Clearlogic.  

I can only hope this does backfire for Altera.  From the lack of a web
page, I would guess the Clearlogic is now shut down???  I looked for a
stock symbol, but found none on Yahoo!  As you say, the FPGA vendors are
quick to point out that even for designs that are expected to be done in
ASICs, FPGAs give flexibilty and quick time to market in the early
stages and a more cost effective solution in the final stages with low
volume.  But if they want to make it hard to do the conversion, then I
can see many users saying, "why bother with the FPGA?"

How do you know that Altera has lost revenue by this "victory"? 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 46657
Subject: Re: What's wrong with clearLogic?
From: Kevin Brace <kevinbraceusenet.killspam@killspam.hotmail.com>
Date: Wed, 04 Sep 2002 22:09:29 -0500
Links: << >>  << T >>  << A >>


rickman wrote:
> 
> 
> 
> I can only hope this does backfire for Altera.


        I surely hope so, too.



>  From the lack of a web
> page, I would guess the Clearlogic is now shut down???  I looked for a
> stock symbol, but found none on Yahoo!


        Clearlogic never reached the IPO stage, so there is no stock for
it.
Considering how the retail (ordinary) investors got burned buying IPO
stocks, it is probably very hard to do an IPO in this bear market.
Even if Clearlogic did an IPO, I will guess that the stock could have
gotten heavily short sold.


Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 46658
Subject: Re: PPC blocks in XC2VP50
From: "Neeraj Varma" <neeraj@cg-coreel.com>
Date: Thu, 5 Sep 2002 09:40:46 +0530
Links: << >>  << T >>  << A >>
Thanks for the reply. The current speed files on support.xilinx.com are as
old as 14-June. It would be nice if this issue is clarified in answers data
base.

--Neeraj


"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3D762107.5EE09FD5@xilinx.com...
> Neeaj,
>
> The 2VP50 PPC count was reduced to 2 from 4.
>
> The largest family member still has 4 PPC.
>
> Contact the hotline or your FAE for the updates.
>
> The changes to the speeds files are very minor (the PPC is not a large
area).
>
> Austin
>
>
> Neeraj Varma wrote:
>
> > Hi,
> >
> > The Virtex-II Pro datasheet says that there are 2 PPC blocks in XC2VP50,
> > whereas in the Xilinx Floorplanner, as well as in the Synplicity Amplify
> > floorplanner, 4 PPC blocks are visible.
> >
> > Can Xilinx clarify which is correct, and if the data sheet is correct,
what
> > are the files (speed files etc.) needed to have the correct floorplan in
> > Xilinx tools? How can we get those files?
> >
> > --Neeraj
>



Article: 46659
Subject: Re: atmel CPLD documentation
From: Mike Rosing <rosing@neurophys.wisc.edu>
Date: Wed, 04 Sep 2002 23:30:43 -0500
Links: << >>  << T >>  << A >>
George Eccles wrote:
> I am considering using an Atmel ATF15xx series CPLD.  This would be my
> first PLD of any sort, and I'm a little bit floundering.  For
> instance, the part data sheet says that outputs can be configured for
> "open-collector" (open drain?) operation; but, I don't find any
> mention of that in the  "Programmer's Reference Guide".
> 
> Is there other documentation on these parts?  Or, is there a better
> way to learn this stuff?

I just looked at an ATF1500 and I don't see it as having open-collector
drivers.  I've never used these parts tho, so maybe I'm missing
something.  What tools are you going to use to program the parts with?
Can you run them now?  Can you get a demo version and try it out?
You may be able to hit the "help" button and do a search for
"open-collector" and find the right place to set your outputs up.

I think I'll read up on the data sheet some more tho - the parts
are easy to come by.

As for learning the stuff, the best thing to do is build a bunch
of simple latches and watch them work!  Once you get the idea of
reprogramming them, you can add more circuits and more complexity.
I like using the schematic entry methods for cpld's, it's just
like laying out standard ttl blocks, but instead of rewiring,
you reprogram!

Patience, persistence, truth,
Dr. mike

-- 
Mike Rosing
www.beastrider.com                   BeastRider, LLC
SHARC debug tools


Article: 46660
(removed)


Article: 46661
Subject: Xilinx's ISE 5.1i
From: muthu_nano@yahoo.co.in (Muthu)
Date: 4 Sep 2002 22:44:33 -0700
Links: << >>  << T >>  << A >>
Hi,

Is that ISE5.1i is free downloadable. If so, where can we get it. and
How to install it.. Here we are using ISE4.1i..

Thanks in advance.

Best regards,
Muthu

Article: 46662
Subject: Re: Hardware Code Morphing?
From: Robin KAY <komadori@myrealbox.com>
Date: Thu, 05 Sep 2002 07:24:46 +0100
Links: << >>  << T >>  << A >>
Robert Wessel wrote:

> Robin KAY <komadori@myrealbox.com> wrote in message news:<3D7609F0.9A7A0E6D@myrealbox.com>...
> > PALcode (Privileged Architecture Library Code) is library of horizontal microcode routines that abstract the
> > operating system from specifics of the processor implementation (i.e method for loading TLB entries, etc...). It
> > has nothing to do with x86 emulation.
>
> PALcode isn't microcode.  It's ordinary Alpha code, with access to
> whatever non-architected processor features and state needed to
> perform the various functions (atomic operations, context management,
> TLB loads, etc.) needed to run the OS.  Other than being
> non-interruptible, and having access to a privileged set of
> instructions and facilities (registers, etc.), there's not much
> special about PALcode.

Opps, I meant vertical microcode. Here's a snippet from usenet post by Dennis O'Conner. There are advocates on both
sides of the "is PALcode microcode?" debate and I don't intend to restart that flamewar.

[quote]
] - PALcode is decoded by the normal decoder, as opposed to to microcode,
]   which is often a raw mask over a processor's internal control lines.

That's what's called "horizontal" microcode. "Vertical" microcode
is often used, and is usually a minor superset of the non-microcoded
portion of the instruction set. Apparently you've never heard of it ?
[/quote]

--
Wishing you good fortune,
--Robin Kay-- (komadori)



Article: 46663
Subject: Re: Xilinx's ISE 5.1i
From: "Giuseppeģ" <gziggio.pleasedontsendmeanything@tin.it>
Date: Thu, 5 Sep 2002 08:26:10 +0200
Links: << >>  << T >>  << A >>
Xilinx newsletter says that the webpack 5.X will be dowlodable from october.

Ciao
Giuseppe

"Muthu" <muthu_nano@yahoo.co.in> ha scritto nel messaggio
news:28c66cd3.0209042144.367f0f73@posting.google.com...
> Hi,
>
> Is that ISE5.1i is free downloadable. If so, where can we get it. and
> How to install it.. Here we are using ISE4.1i..
>
> Thanks in advance.
>
> Best regards,
> Muthu



Article: 46664
Subject: Re: Hardware Code Morphing?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 05 Sep 2002 08:16:16 +0100
Links: << >>  << T >>  << A >>
"Pete Ormsby" <faepeteDELETETHIS@attbi.com> writes:

> Quartus II v2.0 AND Quartus II v2.1 were native Linux ports for the RedHat
> distribution v7.1.  Wine is NOT necessary for Quartus II.
> 
> ModelSim has a native Linux port available, 

<snip lack of same for Leonardo>

Which I don't imagine I will be getting a license of under my Altera
Edition programme, given the price differential....

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 46665
Subject: Re: QUARTUS II V2.1 LINUX (C) ALTERA
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 05 Sep 2002 00:37:13 -0700
Links: << >>  << T >>  << A >>
Kevin Brace <kevinbraceusenet.killspam@killspam.hotmail.com> writes:
>         When I see an Altera employee makes a comment about its rival's
> product, I just have to ask the intention of doing so, since the
> original poster didn't ask anything about Xilinx.

What's to question?  The intention was obviously to highlight an area
in which Altera has a lead on Xilinx.  As far as I know it was a factual
statement concerning a software feature that is actually significant to
some of us.

If representatives from company A started making false or misleading
statements about the products of company X, or criticizing them on
subjective matters, that would be inappropriate.


Article: 46666
Subject: Re: QUARTUS II V2.1 LINUX (C) ALTERA
From: "Paul Baxter" <pauljnospambaxter@hotnospammail.com>
Date: Thu, 5 Sep 2002 08:52:00 +0100
Links: << >>  << T >>  << A >>

"ds" <nospam@cwix.com> wrote in message
news:O3yd9.82$WK.23254185@newssvr17.news.prodigy.com...
> If a version of Leonardo is not available on Linux, Quartus II 2.1 on all
> platforms (Windows, Linux, Solaris, HP)  has a much improved and very
robust
> HDL (VHDL and Verilog) extractor and synthesizer.  ModelTech sells a
> Modelsim simulator that works on Linux.

Can we just get to the bottom of this claim. I really have given the native
Quartus 2 synthesiser lots of outings as the claim for improved synthesis
keeps coming in.

Lets ask some specifics:

Does it now support generics fully (not just in megafunctions)?

Has the parser been heavily updated such that it doesn't CRASH Quartus 2
when it encounters certain syntax errors?

Have you benchmarked typical designs (say a set of openly available cores
would be nice) to backup these statements?


And finally please can Altera employees PLEASE clearly state their name and
some sort of title associated with their company e.g. John Doe , Altera FAE
etc.

Regards

Paul Baxter

PS Currently my design synthesises 30% smaller and 35% faster with Leonardo
(and thats after some painful conversion of generics back to hardwired
constants for Quartus.



Article: 46667
Subject: Re: Handel-C: Undeclared identifier: take2
From: govind.kharbanda@sli-institute.ac.uk (Govind Kharbanda)
Date: 5 Sep 2002 03:49:39 -0700
Links: << >>  << T >>  << A >>
Thanks.  I had forgotten to convert those two lines in the conversion
from pointer to array notation from the original C.  I had also
forgotten that square brackets could be used for bit selection.

In this case the lines should read

  out[x + 6] = r0;
  out[x + 7] = r1;

as x is being used as the index to out.

Cheers,
Gov

"Steffan Westcott" <steffanDOTwestcott@ntlworld.com> wrote in message news:<sZsd9.1383$iS1.113717@newsfep1-gui.server.ntli.net>...
> The lines 369 - 370 read
>     x[6]  = r0;
>     x[7]  = r1;
> 
> .. but it looks like a simple typo, perhaps they should be
>     out[6]  = r0;
>     out[7]  = r1;
> 
> The compiler is complaining that x[6] is of type (unsigned 1) but r0 is of
> type (signed 32).
> 
> Cheers,
> Steffan
> 
> > However I now get a new error: 'object cannot be assigned to'.  This
> > seems to be cropping up everywhere so I guess I'll have to look at the
> > code in some depth before I try and find a suitable example.  If
> > anyone is brave enough to look at the code, I've uploaded it to
> >
> > http://www.sli-institute.ac.uk/~gk/mdct.hcc
> >
> > It will also appear at some point on my TWiki page at
> >
> http://www.sli-institute.ac.uk/project/motorola_projects/twiki/bin/view/H2/W
> ebHome
> >
> > Cheers,
> > Gov

Article: 46668
Subject: Re: Neural hardware containing many neurons but very simple computation
From: Havatcha <nospam@nospam.com>
Date: Thu, 05 Sep 2002 11:52:46 +0100
Links: << >>  << T >>  << A >>
Petres, Zoltan wrote:
> Hi!
> 
> I am looking for a hardware solution that is suitable for implementing 
> the following network:
> 
> I have a special NN with many neurons (over 1k, but if it is possible I 
> need even more, 1 million or so). The net is similar to a Hopfield net, 
> the neurons just connected with its neighbours (north, east, west, 
> south). The construction of a neuron is really simple, it makes some 
> really simple calculation (+, -) with 3-4 bit number.
> 
> Im a real newbie in hardware field, so if you have a suggested 
> architecture, please, also indicate some basic literature (best it is on 
> the internet) that describes how I can build up such a hardware.
> 
> I was told that FPGAs are a good solution for such an architecture, but 
> in this case I acually do not know, how I can count from the number of 
> system gates and logic cells the possible number of neurons.
> 
> All suggestions, literature, links and so on are really appriciated.
> 
> Zoltan
> 


You define the entire network in a hardware description language (like 
VHDL or verilog) and download this onto the FPGA, so you know implicitly 
the entire architecture of the network. Assuming you have prior 
programming experience you should be able to learn VHDL, it can be a bit 
confusing since you have to think in terms of parallel hardware but it 
is worth a go. You can download software that will do this from 
www.xilinx.com for free but you will need to buy the cable to connect 
from your PC to the FPGA board. (100 dollars)
You will also need to build the board to mount the FPGA onto so some 
electronics knowledge would be advisable.


Article: 46669
Subject: Re: why the need for HIGH speed design?
From: Rene Tschaggelar <rets@esr.phys.chem.ethz.ch>
Date: Thu, 05 Sep 2002 13:17:28 +0200
Links: << >>  << T >>  << A >>
PAL TV has the fastest signals there are ?

I made a device that can extract single laser pulses out
of a pulse train that comes at 100MHz.
This device can switch on and off with sub-ns resolution
while being clocked from the 100MHz. The output
of this device is used to drive the optical switch.
The main part of this device is an FPGA with programmanble
counters all running at 100MHz.

Rene


hristo wrote:
> in image processing and with color PAL , 33.32 Mhz is enough to do real time, 
> with less image size, the sufficient speed is much less
> so why the need for higher speed?
> 
> any practical  cases


Article: 46670
Subject: Re: Viewing Xilinx netlist
From: rrr@ieee.org (Rajeev)
Date: 5 Sep 2002 05:32:18 -0700
Links: << >>  << T >>  << A >>
Kevin,

> Hopefully, the above 2 links will solve your problem.

Thanks much !! I was able to create the EDIF netlist.

Best wishes,
-rajeev-

Article: 46671
Subject: Modular Design
From: muthu_nano@yahoo.co.in (Muthu)
Date: 5 Sep 2002 06:09:17 -0700
Links: << >>  << T >>  << A >>
Hi,

Basically the Modular design approach is to split a Big design in to
smallpieces and do the Backend design flow.

"Synplify_pro" synthesis tool has a switch as 'Modular Design'. How
the synthesis tool will split the entire design. and What change will
be there in PAR.

Is it possible to do Modular desing with the ISE4.1i ?

I heard that, "modular design" is seperate software from xilinx...

is that so?

Thanks in advance.

Best regards,
Muthu

Article: 46672
Subject: Re: QUARTUS II V2.1 LINUX (C) ALTERA
From: Kevin Brace <kevinbraceusenet.killspam@killspam.hotmail.com>
Date: Thu, 05 Sep 2002 08:54:27 -0500
Links: << >>  << T >>  << A >>
While Pete didn't make any false statements, a voluntary disclosure that
he works at Altera won't hurt I think.
He can also mention that he doesn't speak for Altera, so that the
comments he makes are interpreted as his own, and not Altera's.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)



Eric Smith wrote:
> 
> 
> What's to question?  The intention was obviously to highlight an area
> in which Altera has a lead on Xilinx.  As far as I know it was a factual
> statement concerning a software feature that is actually significant to
> some of us.
> 
> If representatives from company A started making false or misleading
> statements about the products of company X, or criticizing them on
> subjective matters, that would be inappropriate.

Article: 46673
Subject: library
From: getamit_leo@hotmail.com (Amit)
Date: 5 Sep 2002 07:04:01 -0700
Links: << >>  << T >>  << A >>
Hi All,
I am vlsi engineer and mainly deal in synthesis part. I have got a
problem ..
I am compiling a library .lib and creating it's .db but when i use for
synthesis it shows an error that either a 2 input OR or AND or NOR
gate is not available for mapping. When i read .lib there these gates
are defined.
If someone has any solution for it then please send to me.

Thanks & Regards
Amit

Article: 46674
Subject: Re: xilinx PCI prototype board
From: Kevin Brace <kevinbraceusenet.killspam@killspam.hotmail.com>
Date: Thu, 05 Sep 2002 09:12:24 -0500
Links: << >>  << T >>  << A >>
        If you are on a budget, you can try Insight Electronics
(http://www.insight-electronics.com) Spartan-II 200 PCI development
board which costs about $225 with 8MB of SDRAM on-board.
I used a older Insight Electronics Spartan-II 150 PCI development board
to test a PCI IP core I developed, and it worked fine.
Nallatech (http://www.nallatech.com/) also got a Spartan-II-based and
Virtex-based PCI development boards, but I don't know the prices.
        Whether or not the PCI board will come with a DMA engine depends
on the PCI IP core implementation.
In case you are using LogiCORE PCI, you will likely have to add the DMA
engine to the backend of the PCI IP core.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)


Hugh wrote:
> 
> Hi,
> 
>     Can someone recommend a good xilinx SpartenII based PCI proto board to me?
> Ideally it should have DMA engine on board as well.
> 
> Thanks,
> Hugh
> 
> --
> Use our news server 'news.foorum.com' from anywhere.
> More details at: http://nnrpinfo.go.foorum.com/



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