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Messages from 46375

Article: 46375
Subject: Re: Any FSM optimizer?
From: nnadal@terra.es (=?ISO-8859-1?Q?Narc=EDs_Nadal?=)
Date: 27 Aug 2002 09:57:29 -0700
Links: << >>  << T >>  << A >>
I see, nobody has done a true FSM optimizer!

Narcís Nadal


nnadal@terra.es (=?ISO-8859-1?Q?Narc=EDs_Nadal?=) wrote in message news:<4f3703fe.0208251406.72a80b3d@posting.google.com>...
> Hi all, 
> I had to make a 32 states and 20 I/Os FSM recently in ABEL, Foundation
> 2.1I for an spartan xcs05 and I realize the number of CLBs is strongly
> dependent on the state codification. That is if I numbered the states
> as 0,1,2,3...31 the resulting numer of CLBs is different than when I
> change the order.
> In the other hand I suspect there are parts of that FSM that were
> better optimized in one hot and others not, and due the speed is not
> critical I also suspect there is a lot of room for area optimisation.
> Is there any tool to optimize FSMs across huffman encoding to minimize
> CLBs?
> or other method less optimum?
> Thanks
> 
> Narcís Nadal

Article: 46376
Subject: Re: Any FSM optimizer?
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 27 Aug 2002 10:30:14 -0700
Links: << >>  << T >>  << A >>
Here is an idea:
You can implement your state machine ( and even a much bigger one ) in one BlockRAM in Virtex or Spartan-II devices. It takes
exactly one blockRAM and nothing more ( up to a certain complexity of the control inputs). It's very fast (>100 MHz, and very
easy to understand. But I have no software support, so you would have to figure out the ROM content, which is a direct map of
your output requirements and tour bubble diagram..
If this interests you or anyone else, I can give you more details. This is one of my pet subjects...
The concept is very simple, it divides the dual-port BlockRAM into two single-port RAMs and takes advantage of the fact that
our BlockRAM can be used as a synchronous ROM.
Any takers?
Peter Alfke, Xilinx Applications

Narcís Nadal wrote:

> I see, nobody has done a true FSM optimizer!
>
> Narcís Nadal
>
> nnadal@terra.es (=?ISO-8859-1?Q?Narc=EDs_Nadal?=) wrote in message news:<4f3703fe.0208251406.72a80b3d@posting.google.com>...
> > Hi all,
> > I had to make a 32 states and 20 I/Os FSM recently in ABEL, Foundation
> > 2.1I for an spartan xcs05 and I realize the number of CLBs is strongly
> > dependent on the state codification. That is if I numbered the states
> > as 0,1,2,3...31 the resulting numer of CLBs is different than when I
> > change the order.
> > In the other hand I suspect there are parts of that FSM that were
> > better optimized in one hot and others not, and due the speed is not
> > critical I also suspect there is a lot of room for area optimisation.
> > Is there any tool to optimize FSMs across huffman encoding to minimize
> > CLBs?
> > or other method less optimum?
> > Thanks
> >
> > Narcís Nadal


Article: 46377
Subject: Re: Any FSM optimizer?
From: Dennis McCrohan <mccrohan@xilinx.com>
Date: Tue, 27 Aug 2002 10:51:17 -0700
Links: << >>  << T >>  << A >>

--------------C04D32CD60E8E04E4E11E6FE
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit

Narcís Nadal wrote:

> I see, nobody has done a true FSM optimizer!
>
> Narcís Nadal
>
> nnadal@terra.es (=?ISO-8859-1?Q?Narc=EDs_Nadal?=) wrote in message news:<4f3703fe.0208251406.72a80b3d@posting.google.com>...
> > Hi all,
> > I had to make a 32 states and 20 I/Os FSM recently in ABEL, Foundation
> > 2.1I for an spartan xcs05 and I realize the number of CLBs is strongly
> > dependent on the state codification. That is if I numbered the states
> > as 0,1,2,3...31 the resulting numer of CLBs is different than when I
> > change the order.
> > In the other hand I suspect there are parts of that FSM that were
> > better optimized in one hot and others not, and due the speed is not
> > critical I also suspect there is a lot of room for area optimisation.
> > Is there any tool to optimize FSMs across huffman encoding to minimize
> > CLBs?
> > or other method less optimum?
> > Thanks
> >
> > Narcís Nadal

Sounds like you are using symbolic state machines in Abel. Until very recently, these always encoded as one-hot, which is not
usually optimal in a CPLD (unlike a FPGA).

Recently we added support for symbolic FSM extraction and optimization in Abel for both iSE and Webpack. What happens is that
the logic for the Abel State_Diagram is actually extracted and put in a separate file, which in turn is passed to the XST
synthesis program. This should all happen pretty much automatically if you are using iSE or Webpack 4.1i or later. Assuming the
following line in a Abel source file:

my_fsm      STATE_REGISTER istype 'reg_D';

If you run the "Implement Design" process for an Abel design you should see something like:

Started process "FSM Extraction".

Reading Open-ABEL 2 file fsm_ex1.bl0...
Attempting to extract FSM: my_fsm
Writing Open-ABEL 2 (BLIF) file fsm_ex1.bl1...

appear in the transcript right after the Abel compiler runs.

And in the XST synthesis report you should see something like:

Optimizing FSM <AIM_fsm_ex1_my_fsm> with Gray encoding and D flip-flops.

The encoding can be controlled either by a PROPERTY statement in the Abel source, like:

XILINX PROPERTY 'ENUM_ENCODING my_fsm=gray';

or by setting the "Compile Design" Process property called "FSM Encoding Algorithm" (under the "Special Optimization" tab).
Unless you are particular, the best choice probably is "Auto", which allows XST to make the choice.

Hope this helps,

-Dennis McCrohan
Xilinx CPLD S/W Development





--------------C04D32CD60E8E04E4E11E6FE
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

Narc`s Nadal wrote:
<blockquote TYPE=CITE>I see, nobody has done a true FSM optimizer!

Narc`s Nadal

nnadal@terra.es (=?ISO-8859-1?Q?Narc=EDs_Nadal?=) wrote in message news:&lt;4f3703fe.0208251406.72a80b3d@posting.google.com>...
<br>> Hi all,
<br>> I had to make a 32 states and 20 I/Os FSM recently in ABEL, Foundation
<br>> 2.1I for an spartan xcs05 and I realize the number of CLBs is strongly
<br>> dependent on the state codification. That is if I numbered the states
<br>> as 0,1,2,3...31 the resulting numer of CLBs is different than when
I
<br>> change the order.
<br>> In the other hand I suspect there are parts of that FSM that were
<br>> better optimized in one hot and others not, and due the speed is
not
<br>> critical I also suspect there is a lot of room for area optimisation.
<br>> Is there any tool to optimize FSMs across huffman encoding to minimize
<br>> CLBs?
<br>> or other method less optimum?
<br>> Thanks
<br>>
<br>> Narc`s Nadal</blockquote>


<br>Sounds like you are using symbolic state machines in Abel. Until
very recently, these always encoded as one-hot, which is not usually optimal
in a CPLD (unlike a FPGA).

Recently we added support for symbolic FSM extraction and optimization
in Abel for both iSE and Webpack. What happens is that the logic for the
Abel State_Diagram is actually extracted and put in a separate file, which
in turn is passed to the XST synthesis program. This should all happen
pretty much automatically if you are using iSE or Webpack 4.1i or later.
Assuming the following line in a Abel source file:

<tt>my_fsm&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; STATE_REGISTER istype 'reg_D';</tt>

If you run the "Implement Design" process for an Abel design you should
see something like:

<tt>Started process "FSM Extraction".</tt><tt></tt>

<tt>Reading Open-ABEL 2 file fsm_ex1.bl0...</tt>
<br><tt>Attempting to extract FSM: my_fsm</tt>
<br><tt>Writing Open-ABEL 2 (BLIF) file fsm_ex1.bl1...</tt>

appear in the transcript right after the Abel compiler runs.

And in the XST synthesis report you should see something like:

<tt>Optimizing FSM &lt;AIM_fsm_ex1_my_fsm> with Gray encoding and D
flip-flops.</tt><tt></tt>

The encoding can be controlled either by a PROPERTY statement in the
Abel source, like:

<tt>XILINX PROPERTY 'ENUM_ENCODING my_fsm=gray';</tt>

or by setting the "Compile Design" Process property called "FSM Encoding
Algorithm" (under the "Special Optimization" tab). Unless you are particular,
the best choice probably is "Auto", which allows XST to make the choice.

Hope this helps,

-Dennis McCrohan
<br>Xilinx CPLD S/W Development
<br>&nbsp;
<br>&nbsp;
<br>&nbsp;
<br>&nbsp;</html>

--------------C04D32CD60E8E04E4E11E6FE--


Article: 46378
Subject: Re: Evaluation board recommendation?
From: hdlman@hotmail.com (Tom Loftus)
Date: 27 Aug 2002 11:26:40 -0700
Links: << >>  << T >>  << A >>
jetmarc@hotmail.com (jetmarc) wrote in message news:<af3f5bb5.0208260853.31ba7649@posting.google.com>...
> Hi.  
> 
> For a future project, I plan to use a XILINX FPGA with ~1M Gates and
> DES encrypted bitstream.  Is Virtex-II is the only appropriate family?
> 
> Can you recommend an evaluation board?  It should be affordable. I don't
> need external stuff like LCD etc, just the FPGA (already fitted),
> configurator, download cable, and all I/Os available on 2.54mm pins.
> 

This is probably overkill, but I came across it when looking for some
low end evaluation boards:

http://www.cilicon.com/em/en/evk/home/0,1729,NAT%3DALL%26SID%3D100%26TTL%3D%26SRT%3DlaunchDate%26MID%3D%26CID%3D35461%26RID%3D0%26PID%3D%26LID%3D4%26CTP%3DEVK,00.html

If the link doesn't work, go to the Avnet Cilicon website and look
under
evaluation kits.  I can't vouch for it in any way, but it seems like
it
would meet your needs.

> What's the pricing for 1M gates Virtex-II slowest speed grade, at
> quantities of 100?  What price can be expected in -say- 18 months from
> now?
> 

Contact your local distributor.

Tom

Article: 46379
Subject: Re: Altera Quartus II problems
From: edaudio2000@yahoo.co.uk (ted)
Date: 27 Aug 2002 11:36:18 -0700
Links: << >>  << T >>  << A >>
Horst Trattnig <9714trho@edu.fh-kaernten.ac.at> wrote in message news:<3D6B4B78.3000500@edu.fh-kaernten.ac.at>...
> Hi Ted,
> 
> Well, I use Quartus II since about 8 month and it works fine. If you use
> Quartus II, do'nt use it to compile your VHDL or Verilog File. Use 
> Alteras Leonardo OEM , it's free to get at www.altera.com
> 
> Your Problem could be based on the Pin Assignment. If you have not done, 
> Quartus could not finish your compilation.
> 
> If this does'nt works send me a test design and I'll compile it and send 
> you the result.
> 
> regards,
> Horst
> 
Thanks Horst,
But I think the problem has nothing to do with the source files, as I
get exactly the same error no matter what file or design I use as
source, even a
one line do-nothing file. I am also setting the pins to automatic, or
even make my own selection, same results.

I should say, the software is Quartus II V2.1 Web (the latest version)
from the CD disk I just received. I understand there is a patch file,
but it
only applies to the pay-up version. 

Any ideas anybody?

Article: 46380
Subject: Re: Virtex-IIpro Demo-Boards
From: hdlman@hotmail.com (Tom Loftus)
Date: 27 Aug 2002 11:43:47 -0700
Links: << >>  << T >>  << A >>
> 
> I'm looking for Virtex-IIpro Demo-Boards.
> Any hints would be highly appreciated.
> 
How about this one available from Insight Electronics?

http://www.insight-electronics.com/cgi-bin/bvutf8/memec/scripts/local/mc_loc_b.jsp?Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN&EDOID=194160&Manu=XILINX

Article: 46381
Subject: Re: Any FSM optimizer?
From: John_H <johnhandwork@mail.com>
Date: Tue, 27 Aug 2002 19:34:00 GMT
Links: << >>  << T >>  << A >>
I went looking for information on "StateCad" just now to try and point you to a product with focus explicitly on state machine
design.

Xilinx bought StateCad!

I don't know where within my own suite of tools to find the StateCad application, but the redirection from www.statecad.com to
Xilinx.com suggests the application is now part of the Xilinx tools.  Maybe you can figure out what remains of StateCad there.



Narcís Nadal wrote:

> I see, nobody has done a true FSM optimizer!
>
> Narcís Nadal
>
> nnadal@terra.es (=?ISO-8859-1?Q?Narc=EDs_Nadal?=) wrote in message news:<4f3703fe.0208251406.72a80b3d@posting.google.com>...
> > Hi all,
> > I had to make a 32 states and 20 I/Os FSM recently in ABEL, Foundation
> > 2.1I for an spartan xcs05 and I realize the number of CLBs is strongly
> > dependent on the state codification. That is if I numbered the states
> > as 0,1,2,3...31 the resulting numer of CLBs is different than when I
> > change the order.
> > In the other hand I suspect there are parts of that FSM that were
> > better optimized in one hot and others not, and due the speed is not
> > critical I also suspect there is a lot of room for area optimisation.
> > Is there any tool to optimize FSMs across huffman encoding to minimize
> > CLBs?
> > or other method less optimum?
> > Thanks
> >
> > Narcís Nadal


Article: 46382
Subject: Re: Anyone already on QUARTUS II V2.1 ?
From: "ds" <nospam@cwix.com>
Date: Tue, 27 Aug 2002 19:35:01 GMT
Links: << >>  << T >>  << A >>
It is patch for the Win98 issue, not a service pack. It is installed for
Quartus II 2.1, and is for Win98 users only. The hotline will be able to
provide you the patch.


"Kevin Brace" <kevinbraceusenet.killspam@killspam.hotmail.com> wrote in
message news:akf5g6$79h$1@newsreader.mailgate.org...
>
>
> ds wrote:
> >
> > A patch is available from Altera for QII 2.1 Web Edition.
> > - Subroto
> >
>
>
>         I checked Altera website, but all I found was the Service Pack
> for QII 1.1 and 2.0.
> The QII 2.1 Service Pack doesn't seem to be available yet.
>
>
>
> Kevin Brace (In general, don't respond to me directly, and respond
> within the newsgroup.)



Article: 46383
Subject: Re: Any FSM optimizer?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 28 Aug 2002 10:43:49 +1200
Links: << >>  << T >>  << A >>
Dennis McCrohan wrote:
> 
<snip> 
> 
> Recently we added support for symbolic FSM extraction and optimization
> in Abel for both iSE and Webpack. What happens is that the logic for
> the Abel State_Diagram is actually extracted and put in a separate
> file, which in turn is passed to the XST synthesis program. This
> should all happen pretty much automatically if you are using iSE or
> Webpack 4.1i or later. 
<snip>
> The encoding can be controlled either by a PROPERTY statement in the
> Abel source, like:
> 
> XILINX PROPERTY 'ENUM_ENCODING my_fsm=gray';
> 
> or by setting the "Compile Design" Process property called "FSM
> Encoding Algorithm" (under the "Special Optimization" tab). Unless you
> are particular, the best choice probably is "Auto", which allows XST
> to make the choice.

Sounds interesting ..

 What are the other possible choices, besides gray mentioned 
here ( binary and one-hot ? )

 What controls / handling options exist for illegal state coverage
recovery ? 

- jg

Article: 46384
Subject: Re: Anyone already on QUARTUS II V2.1 ?
From: "Jim Patterson" <jpatters@stny.rr.com>
Date: Wed, 28 Aug 2002 00:32:13 GMT
Links: << >>  << T >>  << A >>
The software has a few settings in it that might help.  One is timing
optimizations and another is I/O optimizations.  Another thing you might try
is different seeds.  You might need to see your local FAE to get the seed
sweeper TCL file to make this easier.

"Sven Tejcka" <Sven.Tejcka@vector-informatik.de> wrote in message
news:3D6A1CE2.D3ECC0F@vector-informatik.de...
> Hi there.
> Has anyone already V2.1 of ALTERA´s QUARTUS II ?
>
> I hope that with 2.1 my design becomes better (timing problems).....
>
> Has anyone experiences if 2.1 does a better job with ACEX 1k devices ?
>
> I have problems with slack times.
> I thought that QUARTUS tries to meet the timings but it seems as if
> QUARTUS uses the first successfull fit and does not try again if timings
> are not met.
> Or is this a thing of settings and I can set an option so that QUARTUS
> tries again ?
>
> Thanks in advance
> Sven
>
>



Article: 46385
Subject: Re: Stratix Experience
From: "Jim Patterson" <jpatters@stny.rr.com>
Date: Wed, 28 Aug 2002 00:34:18 GMT
Links: << >>  << T >>  << A >>
Not yet, but we are considering it also.  I am doing some performance
evaluations on Stratix vs. V2 and V2Pro.

"Terry Herter" <tlh10@cornell.edu> wrote in message
news:3D614457.A6D5F60A@cornell.edu...
> Has anyone had any Stratix experience?  Problems?  Bugs? Availability?
>
> Starting a new project....Stratix looks nice...
>
> Thanks,
> Bruce
>



Article: 46386
Subject: Re: Any FSM optimizer?
From: nospam <nospam@please.com>
Date: Wed, 28 Aug 2002 01:43:55 +0100
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote:

>If this interests you or anyone else, I can give you more details.
>This is one of my pet subjects...

Is there something novel about the design (state machines built from a
clocked latch and PROM were used years ago) or is it just an efficient fit
in Virtex/Spartan-II parts?

There was a software package called Log/IC (or maybe and add on for Log/IC)
by Isdata which would design FSMs with an option for implementation in a
PROM. 

Searching for Log/IC and Isdata doesn't turn up much after 1995 - anyone
know what happened to it/them? 




Article: 46387
Subject: Re: Any FSM optimizer?
From: Peter Alfke <palfke@earthlink.net>
Date: Wed, 28 Aug 2002 03:11:40 GMT
Links: << >>  << T >>  << A >>
If you design the synchronous state machine "my way" in a BlockRAM, the
difference between coding styles becomes irrelevant, and recovery from
illegal states is automatic and also freely programmable.

Peter Alfke
========================
Jim Granville wrote:

> Dennis McCrohan wrote:
> >
> <snip>
> >
> > Recently we added support for symbolic FSM extraction and optimization
> > in Abel for both iSE and Webpack. What happens is that the logic for
> > the Abel State_Diagram is actually extracted and put in a separate
> > file, which in turn is passed to the XST synthesis program. This
> > should all happen pretty much automatically if you are using iSE or
> > Webpack 4.1i or later.
> <snip>
> > The encoding can be controlled either by a PROPERTY statement in the
> > Abel source, like:
> >
> > XILINX PROPERTY 'ENUM_ENCODING my_fsm=gray';
> >
> > or by setting the "Compile Design" Process property called "FSM
> > Encoding Algorithm" (under the "Special Optimization" tab). Unless you
> > are particular, the best choice probably is "Auto", which allows XST
> > to make the choice.
>
> Sounds interesting ..
>
>  What are the other possible choices, besides gray mentioned
> here ( binary and one-hot ? )
>
>  What controls / handling options exist for illegal state coverage
> recovery ?
>
> - jg


Article: 46388
Subject: Re: Any FSM optimizer?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 28 Aug 2002 15:23:25 +1200
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> If you design the synchronous state machine "my way" in a BlockRAM, the
> difference between coding styles becomes irrelevant, and recovery from
> illegal states is automatic and also freely programmable.
> 
> Peter Alfke

Of course, but there are minor hiccups like
- few devices have BlockRAM. 
  ( last time I used a 16V8, I'm sure it was not in the data :)
- SW support for the BlockRAM state engine ?
  Whilst not rocket science, it still needs to be done...

 The ability Dennis mentioned of select the encoding used within 
the state engine sounded usefull.

-jg

Article: 46389
Subject: Re: Any FSM optimizer?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 28 Aug 2002 03:26:53 GMT
Links: << >>  << T >>  << A >>
Somewhere around here I do have an DOS FSM compiler to make microcoded state machines that I wrote about 25 years ago.  Of course
I'd have to find a machine that can read a 5/25" floppy (I don't think I ever transferred it to diskette).  Nevertheless, It seems
to be the rare design where there is enough extra block rams laying around to use it for a state machine.  I think I've done it in
2 out of about the last 50 or so designs.  We usually get a little more bang for the buck by adding a condition mux controlled by
some of the ROM bits to keep the width of the address reasonable.

Peter Alfke wrote:

> Here is an idea:
> You can implement your state machine ( and even a much bigger one ) in one BlockRAM in Virtex or Spartan-II devices. It takes
> exactly one blockRAM and nothing more ( up to a certain complexity of the control inputs). It's very fast (>100 MHz, and very
> easy to understand. But I have no software support, so you would have to figure out the ROM content, which is a direct map of
> your output requirements and tour bubble diagram..
> If this interests you or anyone else, I can give you more details. This is one of my pet subjects...
> The concept is very simple, it divides the dual-port BlockRAM into two single-port RAMs and takes advantage of the fact that
> our BlockRAM can be used as a synchronous ROM.
> Any takers?
> Peter Alfke, Xilinx Applications
>
> Narcís Nadal wrote:
>
> > I see, nobody has done a true FSM optimizer!
> >
> > Narcís Nadal
> >
> > nnadal@terra.es (=?ISO-8859-1?Q?Narc=EDs_Nadal?=) wrote in message news:<4f3703fe.0208251406.72a80b3d@posting.google.com>...
> > > Hi all,
> > > I had to make a 32 states and 20 I/Os FSM recently in ABEL, Foundation
> > > 2.1I for an spartan xcs05 and I realize the number of CLBs is strongly
> > > dependent on the state codification. That is if I numbered the states
> > > as 0,1,2,3...31 the resulting numer of CLBs is different than when I
> > > change the order.
> > > In the other hand I suspect there are parts of that FSM that were
> > > better optimized in one hot and others not, and due the speed is not
> > > critical I also suspect there is a lot of room for area optimisation.
> > > Is there any tool to optimize FSMs across huffman encoding to minimize
> > > CLBs?
> > > or other method less optimum?
> > > Thanks
> > >
> > > Narcís Nadal

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 46390
Subject: Re: Stratix Experience
From: Ray Andraka <ray@andraka.com>
Date: Wed, 28 Aug 2002 03:30:19 GMT
Links: << >>  << T >>  << A >>
Well,  if the stratix numbers stand up to production, it looks like it will
quite well against V2/V2 Pro for DSP.

Jim Patterson wrote:

> Not yet, but we are considering it also.  I am doing some performance
> evaluations on Stratix vs. V2 and V2Pro.
>
> "Terry Herter" <tlh10@cornell.edu> wrote in message
> news:3D614457.A6D5F60A@cornell.edu...
> > Has anyone had any Stratix experience?  Problems?  Bugs? Availability?
> >
> > Starting a new project....Stratix looks nice...
> >
> > Thanks,
> > Bruce
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 46391
Subject: Re: Any FSM optimizer?
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 28 Aug 2002 05:15:48 -0000
Links: << >>  << T >>  << A >>
> Here is an idea:
> You can implement your state machine ( and even a much bigger one )
> in one BlockRAM in Virtex or Spartan-II devices. It takes
> exactly one blockRAM and nothing more ( up to a certain complexity
> of the control inputs). It's very fast (>100 MHz, and very
> easy to understand. But I have no software support, so you would
> have to figure out the ROM content, which is a direct map of
> your output requirements and tour bubble diagram..

A registered ROM was standard procedure for state machines about 15
years ago.  Pick the address size to cover the number of inputs
(including state) you need.  Add more ROMs in parallel if you need
more output bits.

Registerd 256 by 8 bit ROMs were a real breakthrough!

One neat thing about using a ROM is that you know it will fit.
(assuming you allocated enough state bits)  You don't have to
worry about running out of product terms or things like that.


I know of two ways to work out the contents of the ROM.

One is to write a program that will write out the ROM contents.
The general procedure is roughly:
  loop over all possible address inputs
  convert the address/index into convenient symbols
    things like state, and input bits like "full" or "ready"
     fixing up the polarity as needed.
  setup the default output variables (clear?)
  write a big case statement with one branch for each state
    within each branch, write code to fill in output variables
      things like "next_state", "enable_foo"
    inspect input variables as needed
      if (xx) {enable_foo = 1; next_state = xx}
      else { xxx }
  pack the output variables into a ROM word
    (or several words if using multiple ROMs)
  write out the ROM info for this address


The other approach is to turn things inside out and treat the
problem as software.  For this, you have to write an assembler,
but that can be pretty simple, at least after you have one
to copy/hack.  It's just standard old-fart microcode.  For
some types of problems, this makes things much easier to
understand.

  Each line is one instruction and also one state.

  Add "tag:" labels if you want to jump to a line.

  A token corresponding to an output bit just ORs that
  bit into the instruction.

  Input bits get used for conditional branches.
  This is the only complicated syntax.  Try something like:
    full? yes-tag, no-tag

  Instructions without explicit branches are assumed to jump to
  the next location.

The assembler has to assign values to states (or you can tell
the assmebler) and then replicate the instruction to fill
all combinitations of non-state input bits, adjusting the
next-state slot per the conditional branching.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 46392
Subject: Re: Altera Quartus II problems
From: karlIGNORETHISPART@chello.nl (Karl)
Date: 27 Aug 2002 23:53:52 -0700
Links: << >>  << T >>  << A >>
edaudio2000@yahoo.co.uk (ted) wrote in message news:<c54bf83f.0208271036.3900471e@posting.google.com>...
> Horst Trattnig <9714trho@edu.fh-kaernten.ac.at> wrote in message news:<3D6B4B78.3000500@edu.fh-kaernten.ac.at>...
> > Hi Ted,
> > 
> > Well, I use Quartus II since about 8 month and it works fine. If you use
> > Quartus II, do'nt use it to compile your VHDL or Verilog File. Use 
> > Alteras Leonardo OEM , it's free to get at www.altera.com
> > 
> > Your Problem could be based on the Pin Assignment. If you have not done, 
> > Quartus could not finish your compilation.
> > 
> > If this does'nt works send me a test design and I'll compile it and send 
> > you the result.
> > 
> > regards,
> > Horst
> > 
> Thanks Horst,
> But I think the problem has nothing to do with the source files, as I
> get exactly the same error no matter what file or design I use as
> source, even a
> one line do-nothing file. I am also setting the pins to automatic, or
> even make my own selection, same results.
> 
> I should say, the software is Quartus II V2.1 Web (the latest version)
> from the CD disk I just received. I understand there is a patch file,
> but it
> only applies to the pay-up version. 
> 
> Any ideas anybody?


What does the message window (ALT+4) and the status window (ALT+6) tell you ?

Article: 46393
(removed)


Article: 46394
Subject: Re: Virtex-IIpro Demo-Boards
From: Udo Weik <weik@imtek.de>
Date: Wed, 28 Aug 2002 10:15:13 +0200
Links: << >>  << T >>  << A >>
Hello Tom,

thank you for that link!


Kind regards
Udo


Tom Loftus wrote:

>>I'm looking for Virtex-IIpro Demo-Boards.
>>Any hints would be highly appreciated.
>>
>>
> How about this one available from Insight Electronics?
> 
> http://www.insight-electronics.com/cgi-bin/bvutf8/memec/scripts/local/mc_loc_b.jsp?Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN&EDOID=194160&Manu=XILINX
> 


Article: 46395
Subject: My SpartanII thinks it's a Virtex??
From: "Grog" <shem_an_na@_SPAMMENOT_hotmail.com>
Date: Wed, 28 Aug 2002 08:36:58 GMT
Links: << >>  << T >>  << A >>
Greetings all,
Must be Weird Wednesday today..
Just got around to stuffing a board with what is supposed to be a SpartanII.
The writing on the outside says XC2S150 but the JTAG ID is saying XCV150.
I tried it on two different computers, one 3.3.08i and 'tother' 4.2.03i,
same result..
Grabbed an older/different board and it's XC2S150 JTAG ID and Package Label
are correct.  (different batch number)
So I don't think it's a computer/cable/ISE problem...

Some test code seems to be running ok, the mandatory flashing LED is doing
the business..
Verify fails by some 233bits...

Guess I had better have a look at the pin compatability in the PQ208 package
for these devices.
Shouldn't I have had smoke by now if it were really the wrong device.??
(i.e. nothing is hot.... yet..)

I'll write it of as weird shit for now, until next week when a multiplier or
two just might be handy..  :-)

Anyone had anything similar to this happen to them??
suggestions welcome..   Is the Spartan II damaged or have we got a tray full
of "Virti" in disguise.?

Fuzzy Logic at it's best, a big chunk of logic sending my brains fuzzy
allright.
Be well,

Greg the Grog



Article: 46396
Subject: ISE 5.1 Linux?
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 28 Aug 2002 11:59:47 +0200
Links: << >>  << T >>  << A >>

Is ISE 5.1 a native Linux port or does it run under Wine like 4.2?

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 46397
Subject: Neural hardware containing many neurons but very simple computation
From: "Petres, Zoltan" <petres@peaktopeak.hu>
Date: Wed, 28 Aug 2002 13:22:09 +0200
Links: << >>  << T >>  << A >>
Hi!

I am looking for a hardware solution that is suitable for implementing 
the following network:

I have a special NN with many neurons (over 1k, but if it is possible I 
need even more, 1 million or so). The net is similar to a Hopfield net, 
the neurons just connected with its neighbours (north, east, west, 
south). The construction of a neuron is really simple, it makes some 
really simple calculation (+, -) with 3-4 bit number.

Im a real newbie in hardware field, so if you have a suggested 
architecture, please, also indicate some basic literature (best it is on 
the internet) that describes how I can build up such a hardware.

I was told that FPGAs are a good solution for such an architecture, but 
in this case I acually do not know, how I can count from the number of 
system gates and logic cells the possible number of neurons.

All suggestions, literature, links and so on are really appriciated.

Zoltan


Article: 46398
Subject: Re: Altera Quartus II problems
From: edaudio2000@yahoo.co.uk (ted)
Date: 28 Aug 2002 04:55:32 -0700
Links: << >>  << T >>  << A >>
> 
> 
> What does the message window (ALT+4) and the status window (ALT+6) tell you ?

The message window has a red circoe with a white cross saying Design myprog.
Full compilation was unsuccessful. 1 error, 0 warnings

The status window has two lines:
Processing total [2%] (in grey box)
Initialisation [100%] (in blue box)

I wonder if it is a licencing problem..Can you do me a favour?
From the main menu Tools/Options/Licence Setup. There will be a dialog 
coming up with licence setup information. There is a large white edit box 
in the middle titled "Licensed AMPP/MegaCore Functions". Mine is blank
i.e. it has nothing on it. Is this right? does yours say anything?

Thanks 
ted

Article: 46399
Subject: Re: Altera Quartus II problems
From: Horst Trattnig <9714trho@edu.fh-kaernten.ac.at>
Date: Wed, 28 Aug 2002 14:59:32 +0200
Links: << >>  << T >>  << A >>
ted wrote:

>>
>>What does the message window (ALT+4) and the status window (ALT+6) tell you ?
>>
> 
> The message window has a red circoe with a white cross saying Design myprog.
> Full compilation was unsuccessful. 1 error, 0 warnings
> 
> The status window has two lines:
> Processing total [2%] (in grey box)
> Initialisation [100%] (in blue box)
> 
> I wonder if it is a licencing problem..Can you do me a favour?
> From the main menu Tools/Options/Licence Setup. There will be a dialog 
> coming up with licence setup information. There is a large white edit box 
> in the middle titled "Licensed AMPP/MegaCore Functions". Mine is blank
> i.e. it has nothing on it. Is this right? does yours say anything?


Mine is blank to. There are only some informations above:

License: Quartus II Limited Edition

License Type: NIC ID

Host ID: 000244.....

Bolow is a field, System Information. Did this Information matched your 
selected host ID?

regards Horst

ps: I erased my licence path at quartus and it stoped at the same 
possition like in your case.
 > Processing total [2%] (in grey box)
 > Initialisation [100%] (in blue box)


> 
> Thanks 
> ted
> 




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