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Use the free Leonardo synthesis instead of the built in synthesis in Quartus, it will do what you need. Regards "Rob Finch" <robfinch@sympatico.ca> wrote in message news:<FEgU8.2354$aJ4.728017@news20.bellglobal.com>... > I thought I would try converting a design developed using free Xilinx web > tools to one based on free Altera web tools (QuartusII). When I try to > compile the design I get errors about unsupported features of the compiler. > Is there a way around this ? Am I using the right version of the tools ? > It'd be nice if I could have designs that would work with either toolset. > What I've found missing so far is parameterized modules and non-constant bit > selects. It's easy enough to work around these things, but it is annoying to > have to. Is there an alternative ? > > Thanks > RobArticle: 44851
Try www.datel.com "Steve Joures" <sjoures@saiman.co.uk> wrote in message news:<ee77a78.-1@WebX.sUN8CHnE>... > I need to power a single Virtex-II device. Can anyone recommend a small footprint 1.5V DC to DC converter ? > I would prefer 3.3V input voltage, although I could use 5V.Article: 44852
*** post for FREE via your newsreader at post.newsfeed.com ***
Why is my "Run" button disabled?
I have:
- created a project
- inserted my VHDL files
- ensured that the last one in the list is the main one
- setup my implementation options
Am I missing something?
Perhaps there is a simple tutorial I could find online somewhere?
Cheers.
Nathan Baulch
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Article: 44853In article <afslf0$89e$3@newsreader.mailgate.org>, ihatespam99kevinbraceusenet@ihatespam99hotmail.com says... > Peter, I feel like you 56k modem's calculation is somewhat too > optimistic. > When I do downloads with a 56k modem, I don't get anymore than 4k > bytes/s. That is the reality. My cable modem often isn't any better! Servers are often worse. It's the *new* Internet! Huh? Make money?? Sheesh, profit/expense/loss, what's the difference, it's all $$. It looks better green than red though. "We'll mark it green." ---- KeithArticle: 44854
I believe only MAX+PLUS-II supports FLEX10KA (Quartus II supports FLEX10KE though.). If you need a synthesis tool for FLEX10KA, you should be able to use LeonardoSpectrum-Altera Level 1 for free. LeonardoSpectrum's QoR (Quality of Results) is a lot better than Altera's in-house synthesis tool. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Salman Sheikh wrote: > > Hello, > > I am converting a design from gdf maxplus II format to vhdl to better > control synthesis. What place and route tools target the Flex 10K30A for > synthesis? I tried Quartus but it does not seem to support the Flex > 10K30A. > > SalmanArticle: 44855
Kevin Brace wrote: > > Peter, I feel like you 56k modem's calculation is somewhat too > optimistic. > When I do downloads with a 56k modem, I don't get anymore than 4k > bytes/s. > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) The exact speed is not the issue. The other poster was complaining about the time estimate posted on the Xilinx web site of 56 minutes for 142 MB download with a 56Kbps modem. The exact speed always varies. My modem never connects at over 28.8kbps and the measured transfer rate is never over 2.5 KBytes/s. Seems my phone line goes through a pair gain box which is a digital link and drops your modem rate dramatically. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44856
Peter, when I see Xilinx employees making comments about Altera,
it always tends to get nasty and unprofessional (That's how I feel
like.), so perhaps Xilinx employees may want to refrain themselves from
doing that.
A few months ago, I saw several postings by a guy making very biased
comments about Altera who didn't want to disclose that he worked at
Altera because he wasn't necessarily representing Altera and he was
doing on his free time.
But at the same time, I am not terribly impressed when Xilinx employees
badmouth Altera products in this newsgroup.
Let people who don't have any financial connections to either companies
do the commentary here.
Looking at FLEX10K and APEX20K datasheet, FLEX10K and APEX20K
both have Clock Enable (CE) FFs.
I believe it was FLEX8000 that didn't have CE FFs.
Regarding other features, I believe Stratix has got a feature similar to
DCI of Virtex-II, but I don't know much about it, so I won't go into
details.
That being said, I have a PCI IP core which met timing
requirements (Tsu < 7ns, Th <= 0ns, and Tval (Tco) < 11ns) in
Spartan-II-5 with automatic P&R doesn't meet timing requirements in
FLEX10KE-1 also with automatic fitting.
One of the reason it doesn't meet timings in FLEX10KE-1 I noticed was
because FLEX10KE IOE has only one FF per IOE whereas Spartan-II has
three FFs per IOB, which makes it easy to meet PCI's Th <= 0 ns and Tval
< 11ns requirements.
Plus FLEX10KE IOE cannot accommodate FFs that need asynchronous preset
(PCI control signals use asynchronous preset.), so I will get less
predictable Tval.
Because FLEX10KE has only one FF per IOE, Quartus II's fitter has to use
regular FFs, but it tends to do a poor job placing those FFs.
I have seen the fitter place some FFs sooooo far away from the pin that
it sometimes took 5 or 6 ns to get from the FF to the pin, missing Tval
< 11ns requirement.
Even when I don't use IOB FFs of Spartan-II, I have never seen that kind
of delay.
Some may argue I should use the floorplanner to constrain the placement
of those FFs connecting to the pins, but when trying to do so, I have
seen Quartus II's fitter complain that it could not place 4 FFs I tried
to constrain to a certain LAB near some pins although a LAB has 8
entries, and that should not normally happen.
So, based on this episode, I am not too happy with Altera, and I prefer
Xilinx.
Kevin Brace (In general, don't respond to me directly,
and respond within the newsgroup.)
Peter Alfke wrote:
>
> Converting between allegedly similar architectures is always sub-optimal.
> If you use the powerful unique features of the original architecture ( in your
> case the Clock Enable, distributed RAM, dual-port BlockRAM, SRL16, DCM and
> perhaps the DCI of the Xilinx architecture), you have to give those up, but you
> get no benefit from the advantages (whatever they are) of the Altera
> architecture. So you end up with the worst of both worlds, a bland design that
> is inferior to any design optimized for either of the two architectures.
> Synthesis can patch over some of these issues, but never give you the true
> optimum.
>
> Peter Alfke, obviously biased, but trying to be fair.
Article: 44857Kevin Brace wrote: > > Peter, when I see Xilinx employees making comments about Altera, > it always tends to get nasty and unprofessional (That's how I feel > like.), so perhaps Xilinx employees may want to refrain themselves from > doing that. > A few months ago, I saw several postings by a guy making very biased > comments about Altera who didn't want to disclose that he worked at > Altera because he wasn't necessarily representing Altera and he was > doing on his free time. > But at the same time, I am not terribly impressed when Xilinx employees > badmouth Altera products in this newsgroup. > Let people who don't have any financial connections to either companies > do the commentary here. I did not have any problems with Peter's comments, and the significant downside with 100% exclusion, is it degrades the knowledge base. I would rather have an expert opinion ( I can add the 'grain of salt' myself! ) > Looking at FLEX10K and APEX20K datasheet, FLEX10K and APEX20K > both have Clock Enable (CE) FFs. > I believe it was FLEX8000 that didn't have CE FFs. > Regarding other features, I believe Stratix has got a feature similar to > DCI of Virtex-II, but I don't know much about it, so I won't go into > details. > That being said, I have a PCI IP core which met timing > requirements (Tsu < 7ns, Th <= 0ns, and Tval (Tco) < 11ns) in > Spartan-II-5 with automatic P&R doesn't meet timing requirements in > FLEX10KE-1 also with automatic fitting. > One of the reason it doesn't meet timings in FLEX10KE-1 I noticed was > because FLEX10KE IOE has only one FF per IOE whereas Spartan-II has > three FFs per IOB, which makes it easy to meet PCI's Th <= 0 ns and Tval > < 11ns requirements. > Plus FLEX10KE IOE cannot accommodate FFs that need asynchronous preset > (PCI control signals use asynchronous preset.), so I will get less > predictable Tval. > Because FLEX10KE has only one FF per IOE, Quartus II's fitter has to use > regular FFs, but it tends to do a poor job placing those FFs. > I have seen the fitter place some FFs sooooo far away from the pin that > it sometimes took 5 or 6 ns to get from the FF to the pin, missing Tval > < 11ns requirement. > Even when I don't use IOB FFs of Spartan-II, I have never seen that kind > of delay. > Some may argue I should use the floorplanner to constrain the placement > of those FFs connecting to the pins, but when trying to do so, I have > seen Quartus II's fitter complain that it could not place 4 FFs I tried > to constrain to a certain LAB near some pins although a LAB has 8 > entries, and that should not normally happen. > So, based on this episode, I am not too happy with Altera, and I prefer > Xilinx. This sounds like a reasonable criticism of Alteras flows ? > Peter Alfke wrote: > > > > Converting between allegedly similar architectures is always sub-optimal. > > If you use the powerful unique features of the original architecture ( in your > > case the Clock Enable, distributed RAM, dual-port BlockRAM, SRL16, DCM and > > perhaps the DCI of the Xilinx architecture), you have to give those up, but you > > get no benefit from the advantages (whatever they are) of the Altera > > architecture. So you end up with the worst of both worlds, a bland design that > > is inferior to any design optimized for either of the two architectures. > > Synthesis can patch over some of these issues, but never give you the true > > optimum. > > > > Peter Alfke, obviously biased, but trying to be fair. I missed the 'badmouth Altera' context here, mostly I saw that if you want to target TWO vendors, you have to accept a sub-optimal lowest common denominator system design. Sounds credible to me, and many would do that visibly during the 'bid process' to keep both suppliers sharp :) 'Vendor tune' will improve performance, but at the expense of portability - it's an age-old trade off. -jgArticle: 44858
Okay, even if the original poster was complaining about the website (It wasn't the original poster who was complaining about the website. The original poster wanted to know how to update WebPACK.), does it really matter what the website says about how long it takes to download ISE WebPACK? (Sorry, I don't sound sympathetic. I just feel like a it is a minor problem, and there are many many more important things to worry in life.) Anyone who has downloaded a large file knows that it takes long time to download two files totaling 150MB. Not a big deal at all since some people already have cable modems, but I always can to connect to the Internet with my 56K modem for about 44K bps, which equates to about 5.5K bytes/s. Since there is some command overhead, 4K bytes/s sustained sounds reasonable (My ISP can seem to sustain 4K bytes/s.). I am absolutely willing to switch to DSL if someone can offer a service for $20 or even $30 a month (Without a DSL modem lease.), since I am already paying $13 or so for a second phone line. Does anyone have a clue when that will ever happen? Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) rickman wrote: > > > The exact speed is not the issue. The other poster was complaining > about the time estimate posted on the Xilinx web site of 56 minutes for > 142 MB download with a 56Kbps modem. > > The exact speed always varies. My modem never connects at over 28.8kbps > and the measured transfer rate is never over 2.5 KBytes/s. Seems my > phone line goes through a pair gain box which is a digital link and > drops your modem rate dramatically. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44859
To keep a design portable between Xilinx and Altera, one thing
you should be aware is that while Xilinx IOB tri-state buffer is active
low Output Enable (Or active high tri-state.), Altera IOE tri-state
buffer is active high Output Enable (Or active low tri-state.).
Not sure which language you are using, but to keep a design portable,
you should use compiler directives from day one for tri-state buffers,
so that you won't have to modify the design later.
In case you are using Verilog,
_____________________________________________________
/* Comment out one of them */
// For Altera
`define Active_High_OE 0
// For Xilinx
// `define Active_Low_OE 0
/* Comment out one of them */
reg My_OE;
`ifdef Active_High_OE
assign My_Output = My_OE ? My_Output_FF : 1'bz;
`else
ifdef Active_Low_OE
assign My_Output = My_OE ? 1'bz : My_Output_FF;
`endif
`endif
always @ (posedge CLK or negedge RST) begin
if (RST == 1'b0) begin
`ifdef Active_High_OE
My_OE <= 1'b0;
`else
`ifdef Active_Low_OE
My_OE <= 1'b1;
`endif
`endif
end
else begin
if (Input_1 == 1'b1) begin
`ifdef Active_High_OE
My_OE <= 1'b1;
`else
`ifdef Active_Low_OE
My_OE <= 1'b0;
`endif
`endif
end
else begin
`ifdef Active_High_OE
My_OE <= 1'b0;
`else
`ifdef Active_Low_OE
My_OE <= 1'b10;
`endif
`endif
end
end
end
_________________________________________________________________
By commenting out Active_High_OE or Active_Low_OE, you can
target Xilinx or Altera in matter or minutes, assuming that you don't
use any vendor specific features . . .
I did this for my PCI IP core, which initially targeted Spartan-II,
therefore supported active low tri-state buffers only, but I wanted to
keep my design vendor independent, so I used compiler directives for
tri-state buffers and OE FFs.
When I retargeted a design that worked fine in Spartan-II to FLEX10KE,
all I did was I commented out Active_Low_OE, and uncomment
Active_High_OE.
The retargeted design synthesized for FLEX10KE worked correctly on a
simulator I used.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Rob Finch wrote:
>
> I thought I would try converting a design developed using free Xilinx web
> tools to one based on free Altera web tools (QuartusII). When I try to
> compile the design I get errors about unsupported features of the compiler.
> Is there a way around this ? Am I using the right version of the tools ?
> It'd be nice if I could have designs that would work with either toolset.
> What I've found missing so far is parameterized modules and non-constant bit
> selects. It's easy enough to work around these things, but it is annoying to
> have to. Is there an alternative ?
>
> Thanks
> Rob
Article: 44860> -----Original Message----- > From: Steve Joures [mailto:sjoures@saiman.co.uk] > > I need to power a single Virtex-II device. Can anyone > recommend a small footprint 1.5V DC to DC converter ? > I would prefer 3.3V input voltage, although I could use 5V. Maxim, Micrel and Linear Technology are among the usual suspects. They have all been active in developing low voltage versions of their classic buck regulator chips. Depending on how big the V-II is, you may need one of the really macho regulators intended for Pentiums and the like. Read, with very great care, their appnotes about PCB layout. Accept, gratefully and with relief, their advice about magnetics - they often recommend specific components that are designed to go with their parts, and Maxim even include a few inductors in their product lineup. Swallow your pride and shell out for the expensive but effective recommended electrolytics, with very low ESR. -- Jonathan Bromley HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project = Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 = 1AW, UK Tel: +44 (0)1425 471223 mail: = jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: = http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. = reserves all rights of privilege in respect thereof. It is intended for the use = of the addressee only. If you are not the intended recipient please delete = it from your system, any use, disclosure, or copying of this document = is unauthorised. The contents of this message may contain personal views = which are not the views of Doulos Ltd., unless specifically stated.Article: 44861
"Sandeep Unni" <sandeepmec@hotmail.com> wrote in message news:<yjbU8.10481$DB.139224@news1.east.cox.net>... > i am using the Synario 4.1 compiler for a target GAL chip > in VHDL code. I am > facing a rather strange problem. > > Synaio does not seem to recognise the std_logic_unsigned > package. Try rewriting the code for numeric_std or std_logic_arith? Ideally you should be trying to move to numeric_std in any case. > it keeps > giving a 'the following variable has not been declared' > compilation error. That doesn't sound like "not recognising a package". Try posting a more detailed query to comp.lang.vhdl, with some appropriate code fragments and detailed error messages. -- Jonathan Bromley HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project = Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 = 1AW, UK Tel: +44 (0)1425 471223 mail: = jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: = http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. = reserves all rights of privilege in respect thereof. It is intended for the use = of the addressee only. If you are not the intended recipient please delete = it from your system, any use, disclosure, or copying of this document = is unauthorised. The contents of this message may contain personal views = which are not the views of Doulos Ltd., unless specifically stated.Article: 44862
Martin Thompson wrote:
>
>
> Peter's inital comment was simply that taking a design optimised for
> one architecture (and he cited some examples of capabilities of the
> architecture he knows) and 'porting' it to another (which has other
> capabilties) is going to be sub-optimal.
> Obviously the two
> architectures being compared were X and A, but that's what the OP
> asked for.
>
Use of languages like "powerful unique features" and "original
architecture" to me sounds like Peter is trying to imply that Altera is
an inferior copycat manufacturer.
Again, I don't care who got a feature first as long as the competitor
gets it at some point when I need it.
Yes, I do agree that when vendor specific features are used, it does
improve speed/density.
I assume you are referring to the original poster when you wrote
"but that's what the OP asked for," but I believe the original poster
was asking for how to keep the code portable, and didn't ask for the
comparison between A and X.
That's what Peter started, not the original poster.
Sure, when vendor specific features are used, it does improve
speed/density, but I rather not have to use them if I don't have to.
It sounded like the original poster didn't want to use vendor specific
features.
> > Looking at FLEX10K and APEX20K datasheet, FLEX10K and APEX20K
> > both have Clock Enable (CE) FFs.
> > I believe it was FLEX8000 that didn't have CE FFs.
>
> 10K (and 1K) doesn't have a dedicated CE (page 7 of datasheet), it
> uses one of the LUT inputs, which means that 4-inputs + CE means you
> have to use the cascade chain. The 20K does have a dedicated CE input.
>
I was originally going to mention that FLEX10K's data 1 LUT
input is shared with FF's ENA (CE) input, but didn't erased it because
the question here was that Peter was claiming CE is "the powerful unique
features of the original architecture," and all I was going to say was
that Altera has had it for a long time.
I also see that APEX20K has a dedicated CE input per LE. (I checked both
datasheets.)
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44863Hello folks, I use Active-HDL 5.1, Synplify 7.x and Xilinx ISE 4.x. At the moment I do my HDL entry and simulation in Active-HDL, then use Synplify (creating a new project in Synplify manually) to synthesise and then invoke ISE from Synplify to implement designs. I know Active-HDL 5.1 offers the full flow from its frontend and I was wondering if anyone is/has using/used it and if it is any good? If it works - I guess it would make doing things like back annoted simulation really easy? So - what do you guys do for the flow? Thanks for your time, KenArticle: 44864
Kevin Brace wrote: <snip> > > > > Converting between allegedly similar architectures is always sub-optimal. > > > > If you use the powerful unique features of the original architecture ( in your > > > > case the Clock Enable, distributed RAM, dual-port BlockRAM, SRL16, DCM and > > > > perhaps the DCI of the Xilinx architecture), you have to give those up, but you > > > > get no benefit from the advantages (whatever they are) of the Altera > > > > architecture. So you end up with the worst of both worlds, a bland design that > > > > is inferior to any design optimized for either of the two architectures. > > > > Synthesis can patch over some of these issues, but never give you the true > > > > optimum. <snip> > Use of languages like "powerful unique features" and "original > architecture" to me sounds like Peter is trying to imply that Altera is > an inferior copycat manufacturer. > Again, I don't care who got a feature first as long as the competitor > gets it at some point when I need it. I'll agree that 20 readers will have 20 slants, but try re-reading this without any author tag. I took 'original' to mean 'starting/beginning' wrt the design : this is about design conversion, and can apply in either direction. If the 'original architecture' started as an Altera design, then any silicon specific, unique feature will also have porting problems. ( see other posts about differences in OE, and RAM latency .... ) -jgArticle: 44865
"Ken Mac" <aeu96186@yahoo.co.uk> wrote > I use Active-HDL 5.1, Synplify 7.x and Xilinx ISE 4.x. > > At the moment I do my HDL entry and simulation in Active-HDL, then use > Synplify (creating a new project in Synplify manually) to synthesise and > then invoke ISE from Synplify to implement designs. > > I know Active-HDL 5.1 offers the full flow from its frontend and I was > wondering if anyone is/has using/used it and if it is any good? > > If it works - I guess it would make doing things like back annoted > simulation really easy? > > So - what do you guys do for the flow? I use AHDL 5.1 with Altera Quartus 2 and Leonardo for synthesis. I have found that while the approach does work (well currently it doesn't work with VHDL and generics in Leonardo but thats a bug), the amount of optimisation may not be as good as tailoring synthesis options yourself. I tested my results by taking a design and synthesising/PAR outside AHDL using Leonardo's GUI and then comparing with the same design passed through Aldec. Since Aldec do have a tailored solution for Xilinx/Synplify these minor issues may well be all sorted for your particular flow. I suggest you do a side-by-side comparison. Aldec make it very simple to try. For my own projects I have modified the AHDL tcl scripts to use my own Leonardo batch file rather than the pre-built non-optimal one and this now lets me do more of what I want. There's no point in doing timing simulations on a non-optimal synthesis run. Another possibility is to keep synthesis/PAR outside AHDL with a standard directory structure. You can then use the timing/functional/post-synthesis simulations by specifying the correct external files (e.g. sdo or vho etc. in my case). AHDL will complain that synthesis is not up to date but as long as you tell it not to rerun synthesis/PAR it will use your externally generated files. Not as nice as a fully integrated flow, but usable and still allows the file browsing benefits etc. PaulArticle: 44866
Thank you, i think that might help! ThomasArticle: 44867
I don't think Peter was being malicious, rather I think there was some reading
between the lines that is not justified. There are significant penalties, as
pointed out by others, to doing a one size fits all design. The 10K has a clock
enable, but in order to use it you have to give up a LUT input. Also, there are
significant differences in the arithmetic implementation that may cause a design
to take up 2x or more area in 10K than it does in Xilinx (Let's keep the
comparison between devices of the same vintage please!). The Altera LUT is
reduced to a pair of 3 LUTs for arithmetic (one ofr sum, one for carry), which
limits you to a 2 input arithmetic function in one layer of LUTs. In any of
Xilinx's parts going back to the 4K, the carry chain is added logic, so you always
have the full 4 LUT available. Also, the 10K IOBs can only be registered in one
direction at a time, where any of the xilinx devices have registers in both
directions, so bidirectional I/O favors xilinx. Altera 10K has the EAB memories,
which the xilinx devices of the same vintage do not have (xilinx has distributed
RAM using CLBs which can actually be more useful in many applications). Altera's
10K is a row/column more or less global route structure which tends to give more
consistent timing with less physical synthesis effort at the price of performance
for certain designs.
The point is, in order to get performance or density in any family, you need to
tailor the design toward that family. For example, in an arithemtic design in
ALtera, you want to avoid clock enabled flip-flops like the plague, so you do the
block diagram design in a different manner. In Xilinx, the routing favors nearest
neighbor, so you structure the design to be linear to get the most performance.
Kevin Brace wrote:
> To keep a design portable between Xilinx and Altera, one thing
> you should be aware is that while Xilinx IOB tri-state buffer is active
> low Output Enable (Or active high tri-state.), Altera IOE tri-state
> buffer is active high Output Enable (Or active low tri-state.).
> Not sure which language you are using, but to keep a design portable,
> you should use compiler directives from day one for tri-state buffers,
> so that you won't have to modify the design later.
> In case you are using Verilog,
>
> _____________________________________________________
>
> /* Comment out one of them */
>
> // For Altera
> `define Active_High_OE 0
>
> // For Xilinx
> // `define Active_Low_OE 0
>
> /* Comment out one of them */
>
> reg My_OE;
>
> `ifdef Active_High_OE
> assign My_Output = My_OE ? My_Output_FF : 1'bz;
>
> `else
> ifdef Active_Low_OE
> assign My_Output = My_OE ? 1'bz : My_Output_FF;
>
> `endif
> `endif
>
> always @ (posedge CLK or negedge RST) begin
>
> if (RST == 1'b0) begin
> `ifdef Active_High_OE
> My_OE <= 1'b0;
>
> `else
> `ifdef Active_Low_OE
> My_OE <= 1'b1;
>
> `endif
> `endif
> end
> else begin
> if (Input_1 == 1'b1) begin
> `ifdef Active_High_OE
> My_OE <= 1'b1;
>
> `else
> `ifdef Active_Low_OE
> My_OE <= 1'b0;
>
> `endif
> `endif
> end
> else begin
> `ifdef Active_High_OE
> My_OE <= 1'b0;
>
> `else
> `ifdef Active_Low_OE
> My_OE <= 1'b10;
>
> `endif
> `endif
> end
> end
> end
>
> _________________________________________________________________
>
> By commenting out Active_High_OE or Active_Low_OE, you can
> target Xilinx or Altera in matter or minutes, assuming that you don't
> use any vendor specific features . . .
> I did this for my PCI IP core, which initially targeted Spartan-II,
> therefore supported active low tri-state buffers only, but I wanted to
> keep my design vendor independent, so I used compiler directives for
> tri-state buffers and OE FFs.
> When I retargeted a design that worked fine in Spartan-II to FLEX10KE,
> all I did was I commented out Active_Low_OE, and uncomment
> Active_High_OE.
> The retargeted design synthesized for FLEX10KE worked correctly on a
> simulator I used.
>
> Kevin Brace (In general, don't respond to me directly, and respond
> within the newsgroup.)
>
> Rob Finch wrote:
> >
> > I thought I would try converting a design developed using free Xilinx web
> > tools to one based on free Altera web tools (QuartusII). When I try to
> > compile the design I get errors about unsupported features of the compiler.
> > Is there a way around this ? Am I using the right version of the tools ?
> > It'd be nice if I could have designs that would work with either toolset.
> > What I've found missing so far is parameterized modules and non-constant bit
> > selects. It's easy enough to work around these things, but it is annoying to
> > have to. Is there an alternative ?
> >
> > Thanks
> > Rob
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44868Hi, thank you all for answers. It looks like a good stuff for experiments... Actually after more detailed analysis I must use in my design also an low cost MCU because of price difference to next bigger CPLD chip. Best regards, AndrejArticle: 44869
> -----Original Message----- > From: Ray Andraka [mailto:ray@andraka.com] > Jonathan Bromley wrote: <...> > > Depending on how big the V-II is, you may need one of the > > really macho regulators intended for Pentiums and the like. > > Good point. It is very easy to get into 20+ Watt designs in > a V6000. Too many > of the prototype boards do not take into consideration the > potential power > dissipation of designs targeted to the devices. We are > dealing with those > issues on 3 different designs using 3 different off-the-shelf > boards right now. For Pentiums and other big CPUs. it isn't just the power consumption that causes trouble; it's the very rapid changes of supply current, which place extreme demands on the transient behaviour of the power supply. The CPUs notoriously can switch between milliamps and many amps of supply current within a few microseconds as they come in and out of standby. On an FPGA, I suppose, this is less likely to be an issue as all the clocks are probably running all the time and so the current consumption will fluctuate much less than for a CPU or a big ASIC. Never let it be said that analog design is dead :-) -- Jonathan Bromley HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project = Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 = 1AW, UK Tel: +44 (0)1425 471223 mail: = jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: = http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. = reserves all rights of privilege in respect thereof. It is intended for the use = of the addressee only. If you are not the intended recipient please delete = it from your system, any use, disclosure, or copying of this document = is unauthorised. The contents of this message may contain personal views = which are not the views of Doulos Ltd., unless specifically stated.Article: 44870
<Martin> wrote in message news:ee77a64.1@WebX.sUN8CHnE... > Hello Arash, > > the tool which functionality you describe is available. It's called XPower and takes in the implemented design and if you want a *.vcs-file (I think that's the extension) with simulation data from e.g. Modelsim. With that tool you can very accurately predict how much power your design is going to use. > > The tool comes as part of ISE and WebPack and you'll find it in the P&R section of the 'Implement Design' Part in the Project Navigator. > Thanks all for your answers. Well, VCD and Xpower.... I don't know exactly how Xpower works as I've never used it before, but I "guess" it takes the output of the simulation through VCD files, and then gives you an average power consumption over the simulation time; rigth? Well, this approach is certainly enough for many cases... Yet in my application I have a complex design that consists of multiple functional units inside the FPGA, each get active at certain times and after a while get disactivated (clock enable goes to 0) to decrease power consumtion. The problem is that the power consumption is high and the system will be used in a closed box, with no air flow. I'm made a simple estimation of the power consumtion and have found that the temprature of the chip can go up, near the maximum recommended value. Now, as the nature of the processing is very dynamic, I need a way to calculate dynamic power consumtion and even consider effects of heat transfer from die to case of the FPGA and then to PCB and ... to see how hot the device actually gets. I think it's a very difficult task and finally I may reach a point that I conclude the only way is going to lab and see all this in action. Yet, with such a long delay in feed-back loop, the design optimization process would take eons.... Regards ArashArticle: 44871
Unfortunately, I have to use some low level JBITS.set to make PIP
connections.
But I am wondering whether it's enough to apply some mechanism such as lookup
table
to check whether one routing wire has been drived before.I am not sure what's
in Xilinx's
checking process.
Weifeng
Neil Franklin wrote:
> Weifeng Xu <wxu@ecs.umass.edu> writes:
>
> > I am developping a Java program based on JBITS which can generate a
> > bitstream to configure the Xilinx Virtex FPGA directly. But I don't know
> > whether there's some kind of tools can help check whether this bitstream
> > can actually work on FPGA instead of burnning it.
>
> The generation process of JBits should ensure that, as long as you use
> the automatic routing. If you set individual PIPs, all bets are off.
>
> > I know there's Virtex Device Simulator can do some simulation on
> > bitstream, will the simulator check the bitstream and give some warning
> > if there're two dirvers for one line?
>
> Do not know that one. I would doubt it.
>
> --
> Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
> Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer
> - Make your code truely free: put it into the public domain
Article: 44872Arash, I would simulate each functional block alone, with the best vectors I can. I would then modify the vectors to see how sensitive the power is to data in the vectors. If I see a 40% change with data I would then know that my results may vary quite a bit. If I see a smaller change, I would have more confidence. You may try using scrambling techniques to make the data have a nominal 50% density of transitions in order to smooth out your thermal behaviour. Scramble data before flowing through multiplexers or switch matrices, and unscramble it upon leaving. (This also increases power dissipation by adding more logic). This sounds like the satellite work I have done, where heat balance is very delicate, and you would almost rather have a constant heat source, than one that can vary by a large amount. Austin Arash Salarian wrote: > <Martin> wrote in message news:ee77a64.1@WebX.sUN8CHnE... > > Hello Arash, > > > > the tool which functionality you describe is available. It's called XPower > and takes in the implemented design and if you want a *.vcs-file (I think > that's the extension) with simulation data from e.g. Modelsim. With that > tool you can very accurately predict how much power your design is going to > use. > > > > The tool comes as part of ISE and WebPack and you'll find it in the P&R > section of the 'Implement Design' Part in the Project Navigator. > > > > Thanks all for your answers. Well, VCD and Xpower.... I don't know exactly > how Xpower works as I've never used it before, but I "guess" it takes the > output of the simulation through VCD files, and then gives you an average > power consumption over the simulation time; rigth? > > Well, this approach is certainly enough for many cases... Yet in my > application I have a complex design that consists of multiple functional > units inside the FPGA, each get active at certain times and after a while > get disactivated (clock enable goes to 0) to decrease power consumtion. The > problem is that the power consumption is high and the system will be used in > a closed box, with no air flow. I'm made a simple estimation of the power > consumtion and have found that the temprature of the chip can go up, near > the maximum recommended value. Now, as the nature of the processing is very > dynamic, I need a way to calculate dynamic power consumtion and even > consider effects of heat transfer from die to case of the FPGA and then to > PCB and ... to see how hot the device actually gets. > > I think it's a very difficult task and finally I may reach a point that I > conclude the only way is going to lab and see all this in action. Yet, with > such a long delay in feed-back loop, the design optimization process would > take eons.... > > Regards > ArashArticle: 44873
In article <3D231D2C.9E97BD3E@ecs.umass.edu>, Weifeng Xu <wxu@ecs.umass.edu> wrote: > Unfortunately, I have to use some low level JBITS.set to make PIP >connections. But I am wondering whether it's enough to apply some >mechanism such as lookup table to check whether one routing wire has >been drived before.I am not sure what's in Xilinx's checking process. What are you trying to accomplish? An upstream-independant toolflow, or slightly higher level work? IF the later, you might consider outputting xdl instead, converting it to ncd, and pushing it throuh the xilinx router/static timing analysis/ and bitfile generator. I was going down the Jbits route myself for a while, and am now much happier using XDL. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 44874
Hi all,
When I try to execute Modelsim 5.6a (vsim) under Linux (I have Suse
7.3) I always receive the same error message: Error in startup script:
> unknown encoding "iso8859-1"unknown encoding "iso8859-1"
> while executing
> "encoding system iso8859-1"
> invoked from within
> "vsim_kernel encoding system iso8859-1"
> ("eval" body line 1)
> invoked from within
> "eval vsim_kernel encoding $cmd $args"
> (procedure "encoding" line 8)
> invoked from within
> "encoding system $current_encoding"
> invoked from within
> "ncFyP12 "
> (file "/home/jmoreno/modeltech/linux/../tcl/vsim/vsim.op_" line 1)
> RPC(U/I): Error executing closeProc UIQuit close {Problem with
simulator...
> vsim U/I closing. (1)}: attempt to call eval in deleted interpreter
> RPC(U/I): Error executing closeProc UIQuit close {Problem with
simulator...
> vsim U/I closing. (2)}: attempt to call eval in deleted interpreter
>
> Trouble with U/I. vsim is exiting with code 218
Can anyone help me?
Thanks.
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