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Actually we were talking about Xilinx. Unfortunately, the ROUTE constraint seems to be a dump of wire id's or switch ids known only inside of Xilinx tools and is not suitable for an external router. John_H wrote: > Apologies - your mentions were with respect to Atmel only and not about the Amplify > capabilities with Xilinx? > > The Xilinx ROUTE constraint came as a complete surprise to me and I'm very happy to > have found it. I figured even the industry best have probably had this information > slip by. > > > > Ken McElvain wrote: > > >>Ray Andraka wrote: >> >> >>>Arash Salarian wrote: >>> >>> >>> >>>>"jetmarc" <jetmarc@hotmail.com> wrote in message >>>>news:af3f5bb5.0207161704.2f82f19f@posting.google.com... >>>> >>>> >>>>>>I'm in doubt that you'd succeed to find such a tool. Generally as the >>>>>> >>>>>> >>>>exact >>>> >>>> >>>>>>configuration of the LUTs and switch boxes inside a FPGA device is kept >>>>>>secret; there is no 3rd party place and route tool for any FPGA family. >>>>>> >>>>>> >>>>>Atmel gives away this type of information under NDA, even when you're not >>>>>a tool maker. >>>>> >>>>> >>>>Yet I don't think such information is enough to write a Place and route >>>>software. As you see, there is no such tool as a 3rd party Place and route >>>>in the market at all (yeah, but maybe for very old devices like MAX5000....) >>>> >>>> >>>Atmel does give you enough info to route the design under the NDA. We used it a >>>while back for the 6K devices to do some generators for some placed and routed >>>DSP macros. For a general purpose router, there is so much more architecture >>>specific stuff than just the bitstream coding to concern yourself with. It is >>>not a trivial effort by any stretch of the imagination. For that reason, you >>>are not likely to find 3rd party routers for devices that are not really >>>mainstream to begin with. >>> >>>Amplify is not a router, It does placement using the mechanisms for externally >>>applied floorplanning provided by the FPGA tools. You still need to run the >>>design through the tool to get the full placement as well as the route and >>>bitstream. >>> >>Sorry Ray, old data. The more recent versions of Amplify perform a full >>placement for all instances in the regions you make as part of the >>optimization flow. We also do detailed estimation of the routing as >>part of the placement so we get the timing right. There is no current >>interface to pass routing forward. You are correct about having to run >>the design through the Xilinx P&R tools to finish the placement of >>instances outside of the regions and to do routing. >> >> >>> >>>>Amplify, as reffered to by Ken is not a place and route tool, but rather a >>>>"physical optimizer" as it calls itself. It helps the vendors place and >>>>route tool a lot in terms of finding much better placement but has nothing >>>>to do with routing phase (but maybe just to ensure a routing is possible >>>>...). Again in this case I doubt that Synplicity has ever had access to all >>>>detials of Virtex series configuration internals... >>>> >>>>Best Regards >>>>Arash >>>> >>>> >>>-- >>>--Ray Andraka, P.E. >>>President, the Andraka Consulting Group, Inc. >>>401/884-7930 Fax 401/884-7950 >>>email ray@andraka.com >>>http://www.andraka.com >>> >>> "They that give up essential liberty to obtain a little >>> temporary safety deserve neither liberty nor safety." >>> -Benjamin Franklin, 1759 >>> >>> >>> >>> >Article: 45276
venkat <nvk16@hotmail.com> wrote in message news:3f8414df.0207170853.76ad59a4@posting.google.com... > 3. The most commonly used industry FPGAs. I have been browsing the > threads in the newsgroup and have noticed that the Spartan II and the > Virtex family are the most popular. Is that the case? or is that only > because they are supported on Xilinx tools? In Xilinx's annual report they quote Dataquest: 2001 PLD market share: Xilinx 44% Altera 32% Lattice 11% Actel 6% other 7% -JCCArticle: 45277
Why do you say the Synplify will not infer it? From Arash's description it should work fine. Jay wrote: > The distributed ram can be sync write and async read. So it'll cost > ya 512 LUTs to make that ram portable to your previous design. You'll > have to use Coregen to build that ram, Synplicity will not infer it. > > Regards > > "Arash Salarian" <arash.salarian@epfl.ch> wrote in message news:<3d3435b9$1@epflnews.epfl.ch>... > >>Hello, >> >>In my design, there is a FPGA to perform a large number of DSP functions. A >>CPU will finally read the results from the FPGA. The problem is that FPGA's >>output will be a frame of data with the size of 1024Kbytes. Now as the clock >>of the CPU and FPGA are totally independent, in the previous version of the >>design I used an Altera device and used a block of RAM, with synchronous >>write (as the FPGA only needs to write the data) and asynchronous read (as >>CPU only reads the data). >>The problem is this approach is not portable to Xilinx devices as they do >>not feature asynchronous RAM (as far as I know...) >>So what's your suggestion to make this architecture portable? What should I >>use instead of that block of RAM with sync. write and async. read? >>(as the size of the RAM is not small, it's not wise to waste lots of CLBs in >>a Xilinx device to emulate it....) >> >>Regards >>Arash >>Article: 45278
On 17 Jul 2002 07:08:51 -0700, jpnicholls@pwav.com (JP Nicholls) wrote: I'm using the AMP 557100-9 which is the 50 pin version. I'm using much slower LVDS signals, only 220 MHz, but I've tested with as much as 1 meter of plain unshielded ribbon cable and everything works fine. I'd say you would be fine with the connector and just a .025 ribbon cable. If money isn't an issue, go with the individually shielded impedance controlled pairs cable you linked too and you should be golden. Isn't this the connector used for one of the flat panel interface standards? Joey >Thanks for your many replies - all very informative > >Does anyone have any experience with the AMP Champ range of >interconnect? > >Product page: http://catalog.tycoelectronics.com/TE/bin/TE.Connect?C=10493&F=0&M=CINF&N=0&LG=1&I=42&RQS=C~10493^M~FEAT^G~G > >The PCB connector: http://catalog.tycoelectronics.com/TE/docs/pdf/6/49/158946.pdf > >The Cable (05m): http://catalog.tycoelectronics.com/TE/docs/pdf/6/88/174886.pdf > >With correct termination, how would this fare at 622Mbps? How would >it compare to Mictor?Article: 45279
Jay, Maybe you need to include an explicit write enable in your inference... Rather than: always @(posedge clock) MemArr[in] <= inword; assign outword = MemOut[out]; maybe you need: wire we /* synthesis syn_keep = 1 */; assign we = 1'b1; always @(posedge clock) if( we ) MemArr[in] <= inword; assign outword = MemOut[out]; It was an issue before, perhaps it still is. - John_H Jay wrote: > The distributed ram can be sync write and async read. So it'll cost > ya 512 LUTs to make that ram portable to your previous design. You'll > have to use Coregen to build that ram, Synplicity will not infer it. > > Regards > > "Arash Salarian" <arash.salarian@epfl.ch> wrote in message news:<3d3435b9$1@epflnews.epfl.ch>... > > Hello, > > > > In my design, there is a FPGA to perform a large number of DSP functions. A > > CPU will finally read the results from the FPGA. The problem is that FPGA's > > output will be a frame of data with the size of 1024Kbytes. Now as the clock > > of the CPU and FPGA are totally independent, in the previous version of the > > design I used an Altera device and used a block of RAM, with synchronous > > write (as the FPGA only needs to write the data) and asynchronous read (as > > CPU only reads the data). > > The problem is this approach is not portable to Xilinx devices as they do > > not feature asynchronous RAM (as far as I know...) > > So what's your suggestion to make this architecture portable? What should I > > use instead of that block of RAM with sync. write and async. read? > > (as the size of the RAM is not small, it's not wise to waste lots of CLBs in > > a Xilinx device to emulate it....) > > > > Regards > > ArashArticle: 45280
Jeff Cunningham wrote: > In Xilinx's annual report they quote Dataquest: > > 2001 PLD market share: > > Xilinx 44% > Altera 32% > Lattice 11% > Actel 6% > other 7% I think this refers to all Programmable Logic, i.e.CPLDs and FPGAs. My guess is that for FPGAs alone, the Xilinx number is well above 50%, and Actel is higher than 6%, since they make FPGAs only. Altera and Lattice are heavy CPLD suppliers and obviously rank significantly lower in the FPGA statistics. Peter AlfkeArticle: 45281
Dear emanual, Thank you for you help. Reala "emanuel stiebler" <emu@ecubics.com> wrote in message news:3D35860D.66699CCB@ecubics.com... > Reala wrote: > > I would like to know the procedure of developing a simple MCU. > > Any website talk about this? I would like to develop the chip by verilog and > > implement by FPGA. Any suggestion for me? which free tools in good for me? > > Please have a look at www.fpgacpu.org > > There you find more information about fpga-cpus > then you probably ever asked for ;-) > > Have funArticle: 45282
Dear Laurent, Thank for you help. Let me check this in Xilinx 's website. Reala "Laurent Gauch" <laurent.gauch@amontec.com> wrote in message news:3D355431.7050709@amontec.com... > A great one for educative projects : PicoBlaze form Xilinx. I use it > with my students, all is fine ... can be implemented with the free > webpack ... (but no C, only asm language) > > Laurent Gauch > for Amontec.com / Hevs.ch > > Reala wrote: > > > Dear all, > > > > I would like to know the procedure of developing a simple MCU. > > Any website talk about this? I would like to develop the chip by verilog and > > implement by FPGA. Any suggestion for me? which free tools in good for me? > > Thank a lot. > > > > Reala > > > > > > > > > > >Article: 45283
http://www.eedesign.com/story/OEG20020715S0056Article: 45284
Ken, I think we might both saying the same thing, but perhaps not clearly. As I
understand Amplify, it essentially puts RLOCs and BELs on the instances to create a
placement, which is then passed into the tools to direct the placement of the
primitives on the FPGA. As far as I know, Amplify is not producing an NCD file, so in
order to get from the Amplify output to a state where the design can be routed, it
first has to pass through the xilinx placer. The xilinx placer has an easy job in
this case, since all it has to do with a fully RLOC'd design is to put all the BELs
where the constraints say they belong. Nevertheless, you still need to run the xilinx
tool flow from the beginning to take care of all the translations. Please correct me
if I am wrong. This is basically the same mechanism we use for our placed macros and
a good deal of our high performance/high density work.
It would be nice if there were real hooks to direct routing too. I am aware (thanks
to Philip) now of the wire numbering constraints for route, but like you (Ken)
mentioned in another post, it is not general enough to make a router out of it, at
least as far as I can tell.
Ken McElvain wrote:
>
> > Amplify is not a router, It does placement using the mechanisms for externally
> > applied floorplanning provided by the FPGA tools. You still need to run the
> > design through the tool to get the full placement as well as the route and
> > bitstream.
>
> Sorry Ray, old data. The more recent versions of Amplify perform a full
> placement for all instances in the regions you make as part of the
> optimization flow. We also do detailed estimation of the routing as
> part of the placement so we get the timing right. There is no current
> interface to pass routing forward. You are correct about having to run
> the design through the Xilinx P&R tools to finish the placement of
> instances outside of the regions and to do routing.
>
> >
> >
> >>
> >>Amplify, as reffered to by Ken is not a place and route tool, but rather a
> >>"physical optimizer" as it calls itself. It helps the vendors place and
> >>route tool a lot in terms of finding much better placement but has nothing
> >>to do with routing phase (but maybe just to ensure a routing is possible
> >>...). Again in this case I doubt that Synplicity has ever had access to all
> >>detials of Virtex series configuration internals...
> >>
> >>Best Regards
> >>Arash
> >>
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45285Hi all, I've downloaded the OpenCore's PCI IP Core. I'm working with WebPack 4.2.03 and I've got problem when I want synthetize the project. XST (the compiler) doesn't understand the `undef directive. When I remove this directive, I've got multisource in signal xyz. Therefore, I've downloaded WebPack 3.8 to have the "Resolution Style" option. With this version, I can begin to compile the PCI Bridge, but 12 hours after beginning, it's no yet finish. So, do you know how can I should synthetize this project ? Thanks a lot, LaurentArticle: 45286
Anyone know of a good book to program FPGA's with VHDL... I have Ashenden's book on "The Designer's Guide to VHDL" which is great for learning VHDL, but doesn't help if you want to use FPGA's. Things like instantiating BUFG's and FF's in VHDL for use in FPGA's just doesn't seem to appear in the book...hence, all my design's so far have been via schematic entry, which is great, however I think it may be a hindrance to me one day if I don't start designing in VHDL. Thanks AdrianArticle: 45287
BROTO Laurent wrote: > > Hi all, > > I've downloaded the OpenCore's PCI IP Core. > I'm working with WebPack 4.2.03 and I've got problem when I want > synthetize the project. [...] > So, do you know how can I should synthetize this project ? Hi Have you tried the associated forum/mailing list? http://www.opencores.org/forums/pci -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 02 http://www.IPricot.com/Article: 45288
> Since 5V PCI is not intended to run above 33MHz, I will guess > that most cards will likely fail at 50MHz. > Also you should be aware that Virtex/Spartan-II's 5V PCI I/O pads are a > lot slower than their 3.3V 66MHz PCI I/O pads. > I just wondered what kind of PCI is used on PC motherboard?Article: 45289
Yes, but my messages aren't posted on OpenCore's forums. I'll tried to repost this day, I think I must to subscribe to OpenCore's mailing list. But have you ever try this core ? with or without problem ? BROTO Laurent Fime Multimedia 3, rue de Chevilly 94262 Fresnes "Nicolas Matringe" <nicolas.matringe@ipricot.com> a écrit dans le message news: 3D367C91.55DD735C@ipricot.com... > BROTO Laurent wrote: > > > > Hi all, > > > > I've downloaded the OpenCore's PCI IP Core. > > I'm working with WebPack 4.2.03 and I've got problem when I want > > synthetize the project. > [...] > > So, do you know how can I should synthetize this project ? > > Hi > Have you tried the associated forum/mailing list? > http://www.opencores.org/forums/pci > > -- > Nicolas MATRINGE IPricot European Headquarters > Conception electronique 10-12 Avenue de Verdun > Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE > Fax +33 1 46 52 53 02 http://www.IPricot.com/Article: 45290
Hi, I'm trying to simulate a verilog netlist generated by Leonardo using MTI. The problem I am having is that some of the IBUFs on incoming clocks are not functioning correctly. The output of the IBUF is x for a valid input. Has anyone experienced anything similar? Shareef.Article: 45292
John_H <johnhandwork@mail.com> wrote in message news:<3D358AEB.7FC2ABC4@mail.com>... > I was happy to see the note about the "shielded twisted pairs" in the cable > drawing. I cringed whenever I saw a suggestion > for micro-coax (single signal) instead of some form of twisted pair > (differential). Not a good cringe. Twisted pair is dispersive, coax much less so. It isn't an issue in this application, where the cable length is less than a wavelength. More important, coax cables reject external fields a whole lot better than twisted pair, and routing a differential pair of signals along physically coupled pair of coax cables will do a better job than routing the same signal along a shielded twisted pair. At a much higher price .... ---- Bill Sloman, NijmegenArticle: 45293
Klaus Vestergaard Kragelund wrote:
> Hi
>
> I'm beginning on my first CPLD/FPGA design with the Xilinx products. I
> allready have the Foundation Series 1.3 Software with the associated
> Parallel Cable III. I wonder if any of you experts can answer theese
> questions:
>
> 1. I actually have a copy of the "Active HDL 3.5" software - what would you
> use: Active HDL, Foundation Series or the WebPack? Moreover if one uses the
> Active HDL package is the link to the programming via the Parallel Cable
> simple/doable?
Active HDL is a simulator with a design entry tool only. You will need a
synthesizer and the xilinx PAR software as well. v3.5 is old news now (current
version is 5.1); there have been many fixes, improvements, and added features.
Even so, v3.5 was a solid product. Foundation is also old. In your shoes, you
are prbably best off using the webpack, possibly with the Aldec as a design
entry and simulator.
>
>
> 2. I checked the Xilinx website with regards to the cost of the XC9500
> versus the XC9500XL and the XL version was very much cheaper (1$ as opposed
> to 3$ for the simplest chip). Is the only difference just that the XL is a
> 3.3V version - or is the XC9500 being outfaced?
It is a dies shrink. Yields are better, so the device is cheaper to
manufacture.
>
>
> 3. My first circuit is going to consist of a 32bit adder (for a DDS circuit)
> and a 4digit 7-segment display driver. The display driver can easily fit in
> a XC9536XL chip and is simple (I don't even need driver BJTs because the
> XC9500 can drive 20mA LEDs directly) but I'm not sure how large a device is
> needed for the 32bit adder. As 4-5 XC9536XL chips is nearing the cost of a
> XC5200 chip (with 256 registers) would I be better off with the XC5200. As
> for programming I have a microcontroller that can program the XC5200 at
> power-up - so I guess that is not a problem). More to the point - what are
> the major differences of the XC9500 series versus the XC5200 (is the XC5200
> more optimal for complex designs? Arithmetics?)
The 5200 is a dead line, and there is good reason for it not surviving. It is
poor for arithmetic. It is also not supported in the current tools. The 9500
series is not really designed for arithmetic, but it is certainly doable. For
the 32 bit adder, look at the structures of the old cascadable TTL adders.
>
>
> Thanks
>
> Klaus
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45294Normally it's just 5V 33MHz. "Deli Geng (David)" <deli.geng@ncl.ac.uk> wrote in message news:ah646i$h15$1@ucsnew1.ncl.ac.uk... > > Since 5V PCI is not intended to run above 33MHz, I will guess > > that most cards will likely fail at 50MHz. > > Also you should be aware that Virtex/Spartan-II's 5V PCI I/O pads are a > > lot slower than their 3.3V 66MHz PCI I/O pads. > > > > I just wondered what kind of PCI is used on PC motherboard? > >Article: 45295
Hi, Can somebody out there kind enough to help me, a newbie to all this... I have really run out of ideas what could be done in the follwing problem: During mapping in the Design Manager, the following error has occurred: "FATAL_ERROR:Ncd:basncsignal.c:249:1.15.22.3 - Could not find a bel for a signal on pin BX of comp thinwflash_554_W291246. Its current programmed state is : CYSELF:F XUSED:0 XBUSED:0 CYINIT:CIN CY0F:F1 F:#LUT:D=A2 BXMUX:BX FXMUX:FXOR Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com" Thanks in advance. Warmest Regards, lktanArticle: 45296
Hi, I'm currently working on an asic prototype in a Virtex2, alot of clock gating is used in the design, but I can get around most of that be cause it it only for power saving, but in one place gating is used to generate 4MHz from the 24 MHz system clock. Simple I thought I'll just replace the asic gating cell with a bufgce (they should work the same), but it doesn't work! I do get a 4MHz clock but it's as if it doesn't get onto a global clock net, so I get skew and everything is messed up i.e. e counter doesn't count right because some of the bits are clocked from a different net than the rest (in the constraints editor the 4MHz doesn't even show up as a clk?) If I just use the enable signal, sampled once to put the edge the same place, through a bufg and use that as my 4MHz clk everything works perfectly. (in the constraints editor the 4MHz now shows up as a clk) Is there a trick to using the bufgce, that I don't know of? thanks, -LasseArticle: 45297
Hi Adrian,
Try:
Vhdl for Programmable Logic
by Kevin Skahill, Jay Legenhausen (Contributor), Ron Wade, Corey Wilner, bl
Wilson
http://www.amazon.com/exec/obidos/ISBN%3D0201895730/102-1400382-0404964
I have this book and found it very interesting and understandable (though it
is for VHDL beginners - i.e. it doesn't cover full VHDL, unlike Ashenden)
HTH,
Srinivasan
--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India
I don't speak for Intel
"Noddy" <g9731642@campus.ru.ac.za> wrote in message
news:1026980324.607885@turtle.ru.ac.za...
> Anyone know of a good book to program FPGA's with VHDL... I have
Ashenden's
> book on "The Designer's Guide to VHDL" which is great for learning VHDL,
but
> doesn't help if you want to use FPGA's. Things like instantiating BUFG's
and
> FF's in VHDL for use in FPGA's just doesn't seem to appear in the
> book...hence, all my design's so far have been via schematic entry, which
is
> great, however I think it may be a hindrance to me one day if I don't
start
> designing in VHDL.
>
> Thanks
>
> Adrian
>
>
>
Article: 45298
Hi,
I had a trouble with programming NIOS ISR.
More precisely, I tried to synchronise a hardware device
with software using ISR.
That for, I used a software which is made of three pieces :
- a context
stores the context of hardware in a software point of view
- an ISR
modifies the context each time the hardware emit an IRQ
- an API
communicate to hardware and eventually locks until
the context allows it.
I used the following code in the API
char read_data(...)
{
...
while (context->ready==0);
...
}
But it doesn't work because the compiler generates
a code that causes the read of context->ready to
be read from memory only once. The boolean equation
is then evaluated but context->ready is not actualised.
So, even if the ISR modifies the variable context->ready,
it stills keep locks.
Note : I saw his phenomenom thanks to modelsim simulation...
I had to do :
char is_ready(void)
{
return context->ready;
}
char read_data(...)
{
...
while (is_ready()==0)
...
}
This works fine but is a little bit heavy. The produced code is quit
big and introduces an hoverhead.
So, does anybody knows how to manage this ? How to force the real read of the
variable used for the lock ?
Note : in a future version, the lock would be replaced by an OS
semaphore...
Thanks a lot for your responses.
Stephane Mancini
Article: 45299In article <1026991754.214885@aknx2.orcon.net.nz>, kaizen__@hotmail.NOSPAMcom says... > Normally it's just 5V 33MHz. Yes, in all but some "server" models of PCs and Apples. One can tell the difference between the various PCI connectors by looking at them. If the key is away from the rear of the PC (positions 50-51) it is 5V PCI. If the key is towards the rear of the PC (positions 12-13) it's 3.3V. A universal card will have a slot in both positions. 32-bit slots are 62 positions "long" (60 "pins" + 2 key) on each side. 64-bit PCI slot will have two keys, one at the nominal 3.3V/5V position and one at the end of the normal 32-bit slot (32-bit cards may be plugged into 64bit slots). There will be an additional 32 "pins" on each side of a 64bit slot. IIRC a 66MHz PCI slot must be 3.3V and there will be fewer of them without repeaters. ---- Keith
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