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Hi All, I have a design based around a PPC. The problem I have is that I would like to change the default setting for XST when running platgen. Platgen will generate a default synthesis project file which in my case I would like to change. To be specific I don't want XST to use SRL rather I would like to have Flip-Flops instead. In this way I assume that it will mitigate timing, it can place the Flip-Flops apart rather than "having them" all in one component (SRL). Is it possible to change the default? Has any body come across a similar problem? Regards, /RNArticle: 116576
On Mar 12, 6:27 pm, "Bhanu Chandra" <vbh...@gmail.com> wrote: > Hi all, > > I have a peripheral written in verlog, this is getting synthesized by > ISE but then when I generate netlist using XPS it fails to resolve a > function symbol. Could someone please explain what could be wrong > here? > > Thanks, > Bhanu I was making a mistake in the verilog code. I had written a function which obviously had to return something but I was not receiving it into some register. Regards, BhanuArticle: 116577
"Andy Peters" <google@latke.net> writes: > Xilinx' notion of "what's a Warning, what's an Info, and what should > be ignored" is often perverse. Here's an example (and I've opened a > support case about it): > Agreed - and the RAM simulation libraries have the marvellous feature of checking for a read on one port with a write on the other to the same address. This would be OK, but they report it as an *error*! So my TB "fails". Surely that's a warning - there's lots of times I don't care that I've done that! Anyway, I just turn them all off in modelsim by overriding a generic on them! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 116578
Hi, I am using Modelsim to simulate placed-and-routed Xilinx design described in VHDL. I have noticed that in some cases iopath from sdf is being treated as a transport delay and in some other as inertial delay, although the type of the cell is the same (for example, x_buf_pp). Could someone tell me why is this happening and is there a way to change it? Thanks in advance!Article: 116579
We have done before on Virtex-2. It's very good handle to remove the top case of the FPGA if you have a desire to look inside so if you can do have mechanical mounts to the pcb. John Adair Enterpoint Ltd. On 12 Mar, 17:04, jean-baptiste.nou...@jdsu.com wrote: > Hi, > > Anybody has experience with heatsinks on FPGAs? > > In the V5 documentation, Xilinx says the heatsink can be glued to the > FPGA but that it > is safer to screw it to the board to avoid mechanical contraints to > the FPGA > ball when under vibrations. > > But then the screws take some space on the board that we can't really > afford... > This would be at the expense of signal integrity (longer PCB > tracks...). > > Any feedback welcome :o) > > Many thanks, > Jean-Baptiste.Article: 116580
Hi John, yes, your proposal seems to be a good approach. Setting a timing constraint to achieve setup time margin when changing the clock domain is the point which should be kept clearly in mind. Thank you for your opinion. Rgds Andre - Wouldn't it be nice to read serious answers consisting of more then just snatches of sudden inspirations ? Usenet is sometimes poor in respect thereof.Article: 116581
"KJ" <kkjennings@sbcglobal.net> wrote in message news:QPcHh.3095$iw4.17@newssvr23.news.prodigy.net... > > If FPGA/CPLDs cobbled together LUTs to create flip flops the same argument > could be made for not using flip flops. But since FPGA/CPLD/ASICs all > have flip flops implemented as hard logic you don't have this issue. > Also, if the target device does have a hard latch as a resource that can > be used then the use of latches is just fine also. > So, just making sure I understand this. The synthesis tool may or may not choose to generate a "latch inference" warning, depending on whether a latch is natively supported by the target device. And the reason for this warning is that it is not possible to reliably implement a latch, unless the target device has built-in support for it. Is the above correct? -Michael.Article: 116582
Hi Andy and all the nice guys who answered
I cought a bad cold and was mainly listening to my pillow. Sorry for this
delay, i really appreaciate this feedback!
> a) don't do this as a state machine -- you need to make the write
> process(es) separate from the read process(es) (or at least keep the
> read logic in a process separate from the write logic). One important
> point is that an FPGA's "single-port RAM" still has separate data-in
> and data-out ports (unlike a regular RAM chip, which has one
> bidirectional data port). This means that you don't have to worry
> about bus contention, etc., and you don't need a read enable. The read
> side code is simply
I am aiming for the synthesis of dual-ported block ram. Am i right that your
comments aim at single ported ram?
> b) The read has to be synchronous; otherwise it won't use block RAMs.
But in my book the read is synchronous?
I have rewritten the stuff with your suggestions, still no success. Any more
ideeas, why the code below is not synthesized as block ram from xilinx xst
but as distributed ram?
Thanks
ST
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity BRAM_test is
port (CLOCK : in std_logic;
reset : in std_logic;
di : in std_logic_vector(15 downto 0);
do : out std_logic_vector(15 downto 0));
end BRAM_test;
architecture syn of BRAM_test is
type ram_type is array (1023 downto 0) of std_logic_vector (15 downto 0);
signal RAM : ram_type;
attribute ram_style : string;
attribute ram_style of RAM: signal is "block";
type STATE_TYPE is (P1, P2, P3 );
signal STATE : STATE_TYPE;
signal we: std_logic;
signal re: std_logic;
signal addr : std_logic_vector(9 downto 0);
begin
main : process (CLOCK, reset)
begin
if (CLOCK'event and CLOCK = '1') then
if (RESET = '1') then
STATE <= P1;
addr <= (others => '0');
we <= '0';
re <= '0';
else
case STATE is
when P1 =>
we<='1';
STATE <= P2;
when P2 =>
we<='0';
re<='1';
STATE <= P3;
when P3 =>
re<='0';
addr <= addr + '1';
STATE <= P1;
end case;
end if;
end if;
end process main;
ram_write: process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if(we='1') then
RAM(conv_integer(addr)) <= di;
end if;
end if;
end process ram_write;
ram_read: process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if(re='1') then
do <= RAM(conv_integer(addr));
end if;
end if;
end process ram_read;
end syn;
Article: 116583hi every body , please please how to calculate the sum of an array ( for example an array of std_logic_vector(3 downto 0) ) thank youArticle: 116584
Perfect! Thanks for your help.Article: 116585
Venu wrote: > As suggested by John, I replaced the BRAM generated by Xilinx Core > Generator with a Xilinx Primitive RAMB16_S9_S36. I did not change any > logic surrounding the memory modules. Now my memory is being addressed > in the ROW ORDER fashion. ( i.e. as expected from the Xilinx > Documentation ) > > I am not sure if the problem is with the address bit ordering , > because then the error should have shown up in both the > implementations . i.e. with the Core Generator as well as with the > Primitve. > > The only problem with using the primitive is that now I am using a > memory block of 1024 x 8 as opposed to the 128 x 8. That is eating up > a lot of the resources which I need in other modules. > > Thanks > Venu Sounds like the Coregen needs a webcase filed against it. Memories are pretty easy to infer; if you want dual-port distributed CLB SelectRAM, you should be able to get a 160 LUT solution instead without using Coregen. Do you use XST? Synplify? Other? Synplify has their own memory generator wizard these days, too. Are you Verilog? VHDL? it should be quick for someone to give you a module that compiles to LUTs rather than BlockRAM if you are tight on your system memory.Article: 116586
Grant Likely wrote: > On Feb 24, 6:22 pm, Michael Gernoth <m...@gernoth.net> wrote: >> Hello, >> Please report back if this library is useful and works for you. >> Maybe this helpsXILINXto decide that they do not need to use windrvr >> for easy USB access, as most parts of my library are only there to >> provide a compatible replacement for windrvr functions and are not >> needed when directly accessing libusb from within an application >> program. > Hey Grant, seems we hang out at the same spots ;) > Brilliant! Seems to work for me. > I wasn't able to get it to work on an x86_64 system, but in a i386 > chroot I had no problems. Yes this tool is _great_ It works fine for me with ISE9.1 x86_64. I decided to install the .hex in /usr/share/usb instead of /usr/share but Impact seemed to look for it in /usr/share so I just needed to add a hook to redirect the "open" to the right place. Again, Nice work ;) SylvainArticle: 116587
ALuPin@web.de wrote: <snip> > Wouldn't it be nice to read serious answers consisting of more then > just snatches of sudden inspirations ? Usenet is sometimes poor > in respect thereof. Sounds like a job for TechXclusives! Or XAPPs for that matter. I was impressed with how some of my more unusual work already had a couple of application notes dealing with the techniques I was developing.Article: 116588
ST, Since you want a dual-port rather than a single port, try defining two addresses (I'd use syn_keep attributes in Synplify) rather than using "addr" for both the read and the write. I would hardly be surprised to find the synthesizer seeing a single port design is appropriate but then discovering that the write and read enables don't fit the "ENA" and "WE" scheme of a single port BlockRAM. Also, is ramstyle "block" as opposed to "BlockRAM"? - John_H S.T. wrote: > Hi Andy and all the nice guys who answered > > I cought a bad cold and was mainly listening to my pillow. Sorry for this > delay, i really appreaciate this feedback! > >> a) don't do this as a state machine -- you need to make the write >> process(es) separate from the read process(es) (or at least keep the >> read logic in a process separate from the write logic). One important >> point is that an FPGA's "single-port RAM" still has separate data-in >> and data-out ports (unlike a regular RAM chip, which has one >> bidirectional data port). This means that you don't have to worry >> about bus contention, etc., and you don't need a read enable. The read >> side code is simply > > I am aiming for the synthesis of dual-ported block ram. Am i right that your > comments aim at single ported ram? > >> b) The read has to be synchronous; otherwise it won't use block RAMs. > But in my book the read is synchronous? > > I have rewritten the stuff with your suggestions, still no success. Any more > ideeas, why the code below is not synthesized as block ram from xilinx xst > but as distributed ram? > > Thanks > ST > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_unsigned.all; > > entity BRAM_test is > port (CLOCK : in std_logic; > reset : in std_logic; > di : in std_logic_vector(15 downto 0); > do : out std_logic_vector(15 downto 0)); > end BRAM_test; > > architecture syn of BRAM_test is > > type ram_type is array (1023 downto 0) of std_logic_vector (15 downto 0); > signal RAM : ram_type; > attribute ram_style : string; > attribute ram_style of RAM: signal is "block"; > > type STATE_TYPE is (P1, P2, P3 ); > signal STATE : STATE_TYPE; > signal we: std_logic; > signal re: std_logic; > > signal addr : std_logic_vector(9 downto 0); > > begin > main : process (CLOCK, reset) > begin > if (CLOCK'event and CLOCK = '1') then > if (RESET = '1') then > STATE <= P1; > addr <= (others => '0'); > we <= '0'; > re <= '0'; > else > case STATE is > when P1 => > we<='1'; > STATE <= P2; > when P2 => > we<='0'; > re<='1'; > STATE <= P3; > when P3 => > re<='0'; > addr <= addr + '1'; > STATE <= P1; > end case; > end if; > end if; > end process main; > > ram_write: process (CLOCK) > begin > if (CLOCK'event and CLOCK='1') then > if(we='1') then > RAM(conv_integer(addr)) <= di; > end if; > end if; > end process ram_write; > > ram_read: process (CLOCK) > begin > if (CLOCK'event and CLOCK='1') then > if(re='1') then > do <= RAM(conv_integer(addr)); > end if; > end if; > end process ram_read; > end syn;Article: 116589
Venu, when you implement your memory in BlockRAM (as you stated), then there are no fractional BRAMs. You use up one BRAM, whether it is 128 x 8 or 1k x 8. So you are really not wasting anything, Peter Alfke On Mar 12, 11:02 pm, "Venu" <get2v...@gmail.com> wrote: > As suggested by John, I replaced the BRAM generated by Xilinx Core > Generator with a Xilinx Primitive RAMB16_S9_S36. I did not change any > logic surrounding the memory modules. Now my memory is being addressed > in the ROW ORDER fashion. ( i.e. as expected from the Xilinx > Documentation ) > > I am not sure if the problem is with the address bit ordering , > because then the error should have shown up in both the > implementations . i.e. with the Core Generator as well as with the > Primitve. > > The only problem with using the primitive is that now I am using a > memory block of 1024 x 8 as opposed to the 128 x 8. That is eating up > a lot of the resources which I need in other modules. > > Thanks > VenuArticle: 116590
I looked at Xilinx' sysnthesis template for double-registering asynchronous signals to avoid metastability problems. They explicitly state that an SRL primitive should NOT be extracted. Why is this? I have used basically the same Verilog construct in my designs (having not looked at Xilinx' template first) and am fairly certain that SRL primitives ARE used. Is there a problem with this? Is it not advidsable to use SRL primitives as synchronization flops?Article: 116591
Andre, be happy that you got all these answers. (Remember we are all here as volunteers). I kind of complained that you presented your design in a format that I find very difficult to analyze, while a schematic would have been a snap, for me. Not everybody will agree. Cheers Peter Alfke On Mar 13, 5:01 am, "ALu...@web.de" <ALu...@web.de> wrote: > Hi John, > > yes, your proposal seems to be a good approach. Setting a timing > constraint to achieve setup time margin when changing the clock domain > is the point which should be kept clearly in mind. > > Thank you for your opinion. > > Rgds > Andre > - > > Wouldn't it be nice to read serious answers consisting of more then > just snatches of sudden inspirations ? Usenet is sometimes poor > in respect thereof.Article: 116592
motty, The SRL16 is not a master/slave flip flop, so as such, it is not well suited to be used as a synchronizer between an asynchronous domain and a synchronous one. Basically, for synchronization, you want a master slave FF, and you want it to be incredibly fast. In V5, the SRL32 (or SRL16 is a master slave design, and this restriction should be removed (IMO). AustinArticle: 116593
Hi i'm outraged! Those guys from the X* company STOPPED DELIVERING printed manuals with their boards!!!! This is not right. For $149 plus international shipping rates, I demand a printed manual as well!!! What is your opinion? Does this happen for all (after mid 2006) Xilinx boards?Article: 116594
I have a V4FX12 application that could potentially benefit from having Gbytes of ROM data storage easily changeable through a CF card, so the system ACE CF thing looks sort of interesting. We are trying to put together SW on a ML403 board based on xilkernel and the lwip ethernet stack. I am wondering how hard it would be to give the app access to a big table of data on the CF card. Maybe I'm not looking in the right place, but I've seen no example designs or drivers for accessing the system ACE short of MontaVista Linux. I've read the white paper and system ACE FAQ and skimmed the datasheet. They don't come right out and say it, but give the impression that the app must have FAT file system awareness to use the CF card. It would be great if there were some simple way of accessing big table of read-only data (as the configuration functionality obviously does). Has anyone here used the system ACE for generic storage? How was the experience? thanks, JeffArticle: 116595
On 12 Mar 2007 10:04:30 -0700, jean-baptiste.nouvel@jdsu.com wrote: >Hi, > >Anybody has experience with heatsinks on FPGAs? > >In the V5 documentation, Xilinx says the heatsink can be glued to the >FPGA but that it >is safer to screw it to the board to avoid mechanical contraints to >the FPGA >ball when under vibrations. > >But then the screws take some space on the board that we can't really >afford... >This would be at the expense of signal integrity (longer PCB >tracks...). > >Any feedback welcome :o) > >Many thanks, >Jean-Baptiste. This is a non-trivial problem. What is the environment? Will it be subject to shock and vibration? What is the board orientation? In our experience the only thing that works reliably is to screw it down. Our applications are ground-mobile military and passenger rail vehicles. The forces have to be carefully controlled so that you don't deform the BGA solder balls. You will have to check with Xilinx to see what compression forces are acceptable for each package. To control this we use spacers between the PCB and the heat sink, and a Bergquist ultra-soft thermal gap pad between the heat sink and the BGA package. You have to adjust the spacer height to get the right amount of compression of the pad. We have found that the PCB is not stiff enough and will bow under the pressure. So, on the bottom of the PCB we add a thin FR4 insulating spacer and then a stainless-steel stiffener plate. The plate has countersunk holes, and we use flat-head screws from the bottom and lock nuts at the top (heat sink). We have been using Radian 'Icicle' series half-brick DC-DC converter heat sinks. We have not yet had to do this with Xilinx devices, but we have been doing this with Freescale PowerPC processors (up to 480 pin BGAs). ================================ Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com -- Posted via a free Usenet account from http://www.teranews.comArticle: 116596
Add them together? Your problem is not clear. Do you have an array in memory that you need to cycle through the elements one-by-one through an accumulator? Do you have an array of registers that needs a sum through a simple adder tree? Do you need to add two arrays held in memory to get a third array? Please clarify the help you would like. "VHDL_HELP" <abaidik@gmail.com> wrote in message news:1173792287.141073.35720@t69g2000cwt.googlegroups.com... > hi every body , > > please please how to calculate the sum of an array ( for example an > array of std_logic_vector(3 downto 0) ) > > thank youArticle: 116597
ALuPin@web.de wrote: > Hi John, > > yes, your proposal seems to be a good approach. Setting a timing > constraint to achieve setup time margin when changing the clock domain > is the point which should be kept clearly in mind. As long as you are using just different edges of the same clock, a period timing constraint will automatically take into consideration that you have changed clock edges.Article: 116598
"Uncle Noah" <nkavv@skiathos.physics.auth.gr> wrote in message news:1173797433.592515.263610@j27g2000cwj.googlegroups.com... > Hi > > i'm outraged! Those guys from the X* company STOPPED DELIVERING > printed manuals with their boards!!!! > > This is not right. For $149 plus international shipping rates, I > demand a printed manual as well!!! > > What is your opinion? Does this happen for all (after mid 2006) Xilinx > boards? But a printed manual wouldn't have any of the fancy hyperlinks that let you cruise around the board with the click of a mouse! You have to use the computer to work with the board - designing, programming - why not use it to bounce around the .pdf to your heart's content? I, for one, sincerely appreciated the ease of getting around the manual with the help of the hyper-linked image and other internal cross-references. A decent manual all around.Article: 116599
On 13 mar, 07:41, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > On 2007-03-12, Pablo <pbantu...@gmail.com> wrote: > > > Thanks so much for your help, but I have not understood some answers: > > > - First of all. I have EDK in a lot of versions so I don`t need to buy > > it again. The problem is that my board doesn`t belong to Xilinx, so I > > can`t use EDK. I have a Virtex II Pro (from Xilinx) pluged in a > > Sundance Board (SMT338:http://www.sundance.com/web/files/productpage.asp?STRFilter=SMT338-VP...). > > That is the reason because I don`t use EDK. Correct me please. > > > - Second. I am very grateful if you could tell me some thing to begin > > learning, because I have no idea of how can I program a simple "hello > > world", or something in C (if I could with Power PC). > > Ah, now I understand what you are getting at. > > It is possible to use the EDK with this FPGA board but you will have > to do some more work yourself. I have not done so myself however so > I'm not sure of exactly how to do it. However, the documentation at > for example the following page talks about using a custom board: > > http://toolbox.xilinx.com/docsan/xilinx8/help/platform_studio/html/ps... > > As a first try I would create a system that only has a serial > port for I/O to minimize the UCF-file editing. (Well, a clock > and a reset signal is good to have as well :)) > > Or you could ask sundance if they have a board definition file for the > EDK so that you don't need to worry about it. > > Good luck! > > /Andreas thanks again. I am trying to define a minimal system with a "led". Regards Pablo
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