Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0411110711.72227d89@posting.google.com>...
> suntthekid@gmail.com (suntthekid) wrote in message news:<9f23080e.0411102312.20a1dc2d@posting.google.com>...
> > I simulate vhdl code in modelsim and then it is correct. but, when i
> > burn this code into FPGA chip (Stratix S25F672C6) it's wrong (i saw a
> > signal in signaltap and found it 's wrong)
> > so i want everybody who know this problem help me to solve this
> > problem
>
> This happens all to often.
>
> First thing to check is that you don't have any timing violations.
> Check the STA report. Next, is it possible that you have a problem
> with data crossing between clock domains (i.e. could be a problem that
> means your code is incorrect, but it just doesn't show in the
> simulation because of the way the clocks are generated. More details
> on your exact problem would help)?
>
> If you are convinced that it's the synthesis or P&R tools that have
> got it wrong, then you should try running simultions on the
> post-synthesis and post-P&R netlists. Alternatively, if you have a
> equivalence checking tool, you can compare the next lists
> automatically. You can try synthesizing the design with different
> optimisation settings to see if the bug changes / disappears. That's
> quite a good sign that something is wrong with the tools.
>
> Cheers,
> Jon
Hello, Jon
From timing analysis in Quartus (my circuit have 2 clock) Fmax of
first clock that the code can run about 75 MHz and another clock(clk2)
can run about 120MHz. the first clock we run at 33.33 MHz (I use this
clock to system clock) and the other clk is used for receive external
signal. and the recieve frequency i try fist is 50 MHz and found
incorrect in the circuit so i decrease recive frequency to 4 MHz and
it is still incorrect. (note: clk2 is use to write signal into RAM and
Clk1 is used to read signal from RAM). before I ask you i simulate
only functional and i will try to simulate follow your suggestion.
when i change option to synthesis the result is different. (i.e.
sometimes state is not change to correct state, some signal is not
change follow i write the code)
Thank you for your sugestion before. and hope to recieve your
next sugestion. thank you very much.
Cheers,
Sunt and Akaporn
Article: 75676On 11 Nov 2004 17:32:15 -0800, suntthekid@gmail.com (suntthekid) wrote: >Hello, > I have a problem about set up inout port when i simulate vhdl code It >is not work > so i want to know how to write vhdl code ( set pin to inout and >it is work) also i try to use tristate but It is not work too. maybe i >miss something in the code and i don't know. help me please > thank you check out the fpga faq and specifically this link http://www.8ung.at/raimy/study/vhdl/FAQ1.html#driversArticle: 75677
One technique is to have an N-to-1 Mux with the output selected by address lines, and a decode of a tristate output enable off of appropriate signals. Key is that this is all done without a clock ... which is okay since it sounds like the read is not doing anything like advancing internal address pointers ... as in a FIFO. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. email : jretta@rtc-inc.com web : www.rtc-inc.com "Jason Berringer" <jberringer.at@sympatico.dot.ca> wrote in message news:LoTkd.30768$Z7.1043609@news20.bellglobal.com... > Hello all, > > I have a microcontroller running at 40 MHz that performs asynchronous bus > transfers, and I have an FPGA running at 100 MHz. With talk of metastability > and all I would conclude that sending some of the control signals through > flip flops (say 2 levels) would eliminate any metastability. The question > then becomes how do I keep the bus transfers short enough without incurring > significant delays between registering a read command (for example) and then > responding to it and placing the data on the bus to be read. This would have > 2 clock cycles to eliminate the metastability on the read signal (and > address lines if I want to worry about metastability with those lines) and > then at least one more for the data to be placed on the bus, a total of > three clock cycles. That is too much time to get the data on bus (if I'm > trying to keep the bus cycles short). I would appreciate some advice on how > others have handled transferring data between an asynchronous device and an > FPGA. > > Would it not be acceptable to make an asynchronous interface block for the > FPGA, and then pull it into the synchronous world inside the chip? This > seems to go against the metastability thoughts that I've come across. > > Any and all comments would be appreciated.. > > Thanks, > > Jason > >Article: 75678
Jason Berringer wrote: > > Hello all, > > I have a microcontroller running at 40 MHz that performs asynchronous bus > transfers, and I have an FPGA running at 100 MHz. With talk of metastability > and all I would conclude that sending some of the control signals through > flip flops (say 2 levels) would eliminate any metastability. The question > then becomes how do I keep the bus transfers short enough without incurring > significant delays between registering a read command (for example) and then > responding to it and placing the data on the bus to be read. This would have > 2 clock cycles to eliminate the metastability on the read signal (and > address lines if I want to worry about metastability with those lines) and > then at least one more for the data to be placed on the bus, a total of > three clock cycles. That is too much time to get the data on bus (if I'm > trying to keep the bus cycles short). I would appreciate some advice on how > others have handled transferring data between an asynchronous device and an > FPGA. > > Would it not be acceptable to make an asynchronous interface block for the > FPGA, and then pull it into the synchronous world inside the chip? This > seems to go against the metastability thoughts that I've come across. I designed something similar and found it was not a big problem. You don't have to worry about metastability on the read as long as you are not doing anything else with the strobe internally. Even though the read enable or address may be changing on a clock edge, that first cycle will be ignored by the CPU and 10 ns later the second clock cycle will read valid data from the RAM in the FPGA. On the write you should use a register to hold the data when the write strobe is asserted. The stabilized (and delayed) write strobe can write the data into your RAM. If your data is not stable on the leading edge of the write strobe, you can use one of the delayed strobes to as your data register enable. That will help you meet both setup and hold. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75679
suntthekid wrote: > > Hello, > I have a problem about set up inout port when i simulate vhdl code It > is not work > so i want to know how to write vhdl code ( set pin to inout and > it is work) also i try to use tristate but It is not work too. maybe i > miss something in the code and i don't know. help me please You might also try posting this to comp.lang.vhdl. What the heck, I'll do it for you... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75680
Is it possible to configure a DualPartRAM in an Altera APEX20KE (using Quartus II 4.1) to write serial to the RAM (1 Bit) and read parallel from the RAM (16 Bit)? Thanks, ManfredArticle: 75681
Hendra wrote: > How did you get the T-Shirt? I would like to get one! >=20 > Hendra me too 8-) --=20 ----------------------------------------------- Johan Bernsp=E5ng, xjohbex@xfoix.se Research engineer, embedded systems Totalf=F6rsvarets forskningsinstitut Swedish Defence Research Agency Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 75682
Thanks for your numerous answers so far. For a better understanding let me elaborate on my intention. What I want to do is to handle several outputs (with the analog representation of the digital value) with just one single D/A converter. That means: feed the digital values through a single D/A converter and switch the converter output to one analog hold circuit per channel. Therefore the goal is to hold the analog values! The analog values to be hold are DC, that's true. Again, would it be advisable to use a capacitor and op-amp? How should I dimension the capacitance and how can I affect the droop? Is it realistic to expect virtually no droop? Isn't it, that with a large time constant the charging time would be endless? Maybe the solution is nearer as I can see? Maybe there is another way to solve the problem. But this "one D/A converter for multiple output channels"-configuration should be seen as basic condition!!! Many greetings, VeronicaArticle: 75683
Francesco:
Please let me know when you have something testable. I think it could
be useful to cooperate with/add to my Picoblaze IDE too. You should
consider targeting it to the Picoblaze-3 core, which is main stream
now, I think. A variation of that core with a block ram as scratchpad
gives you 256 byte variable/data space, which can be initialized
constant area also. This allows you to work with strings etc.
Additionally, since block rams are dual ported, you can share 1
blockram between two Picoblazes. You need to be able to locate your
data/variables somewhere in blockram, to keep variables for both pB's
separated (or not, so you can use variables to communicate between the
2 pB's). Do not assume any genaral purpose memory attached to the I/O
ports.
Henk
francesco_poderico@yahoo.com (Francesco Poderico) wrote in message news:<1d6bc71.0411110829.c65c63b@posting.google.com>...
> Thank you henk for your comment,
> Yes, I'm assuming to have some external memory attached to the
> processor.
> But if you declare a variable as register you may not need any
> external ram
>
> eg.
>
> void main(){
> register char i;
> register int *p;
> p=1;
>
> for(i=0;i<100;i++){
> {
> *p=(int)i;
> }
>
> }
> In this case the compiler generate code that doesn't need any memory
> attached to PicoBlaze :-)
> If you still don't bealeve me, send me some code and I'll send you
> back the code
> generated by PicoC :-)
>
> So, it depeand from the application... you can use the external memory
> or not.
>
> The compiler also tells you how much memory you need (if you need)
>
> Unfortunatly I still have a lot work to do, but the compiler start to
> be
> working.
> The version alpha will be read in few weeks time,(I still have some
> bugs to fix)
> I hope to fix some bugs in 2 or 3 week time, after that I will
> appriciate
> anyone could help me in the testing(I won't give the source)
>
> Also, I want to say thanks to all the people that seems interested in
> this project.
>
>
>
> Francesco
Article: 75684Just to put my aim in perspective: I'm neither trying to fool you nor trying to get my homework solved (like a given individual presumed). Why I am talking about a basic condition with respect to the "one D/A converter for multiple output channels"-configuration is that this single D/A converter already exists in hardware. It is there, physical, for me to touch, already bought... And now I want to use this very D/A converter to feed several output channels. Of course I could buy a DAC for every channel but that's not my intention. The hardware setup does not allow to solder other devices on the board. So PLEASE just take it as it is! I want to solve the problem that way. So don't try to proselytize me like that jehovah's witnesses guys... ;-) Hope you come up with more constructive suggestions! VeronicaArticle: 75685
rickman wrote: > Thomas Reinemann wrote: >> >> reconfiguration. >> The communication system connects all slots of my FPGA and shall even >> work if a slot is under reconfiguration. However, if the CS signal is >> active of a Xilinx FPGA, the complete logic works. Logic under >> reconfiguration produces trashy signals, and therefore the C/S has to be >> suspended if any slot is reconfigured. But IMHO trashy signals are only >> produced by changing logic, therefore I want to fix the related logic >> (only one CLB) within each module's type, to avoid suspending of the >> C/S. And my question is, is this assumption true? > > I understand what you are saying. I know that the Virtex parts support > this, but I don't know if the software makes it very easy to do in > practice. You should contact Xilinx support about it. I asked Xilinx support already concerning partial reconf several times, usually I told them more then they me. > I assume you > have checked for an app note or similar. A little bit, but I may haven't the right keywords. One goal of this thread is to point me in the right direction, I have to look for. >> >>2. If the logic is fixed, do I need long lines and TBUFs, >> > There are no real tri-state buses current FPGAs. >> You haven't understand my question. Real tri-state behavior wasn't a >> matter. Xilinx approach needs TBUFs and long lines to provide fixed >> points within a slot to connect signals of all types of a module >> properly, since logic is changing. But now I have some fixed logic, do I >> still need fixed communication points? > > Actually, the current software requires you to use a true long line and > tbufs for each signal in the bus macro. So again, the Virtext parts > (not the Spartan parts which don't support active reconfiguration) might > support using non-tbuf signals between modules, but I don't think the > software does. Do you mean the module's types can only connect to tbufs and long lines? The xap290 says:"Each time partial reconfiguration is performed, the bus macros is used to establish unchaging routing channels between modules, guaranteeing correct connections." Furterhmore in my first partial reconf design I assumpted reset uses a dedicated net similiar to clock and didn't use a bus macros for the reset signal. The initial configuration (using TI) worked but not the reloaded different type (TII). If a reloaded the TI again it worked again. Ofcourse, the routing was broken for TII. I plan to implement my communication system alone in a first step, completely fixed, not using the partial reconfiguration design flow. This design shall be transformed in a macro. In a second step I want to apply it in kind of a bus macro. And now I'm looking for an app note how to build my communication system as a macro. Bye TomArticle: 75686
rickman wrote: > And those FPGAs without tbufs are not supported by the partial > reconfiguration design software. You can only use this with the Xilinx > parts prior to Spartan III. So be prepared to pay the higher prices for > parts that let you reconfigure on the fly which is supposed to save you > money by using smaller parts... sort of counter intuitive isn't it? > > I have been told more than once that partial reconfiguration is not a > good thing to try to use in a commercial product. I would hazzard a > guess that it is not a technolgy that is used enough (or requested > enough) to have been fully developed. Therefore we do research in this field to provide solutions for commercial products :-). > I believe they even put in an app > note that you should limit your designs to just two modules, one fixed > and one replacable. I think that was in the context of active partial > reconfiguration. You are right. But did you always do what your parrents said :-)? Bye TomArticle: 75687
Hi Austin Thanks for that -- I wasn't really sure that the Pro-X and V4 were 10Gb/s per channel (pair of differential pins), since people ofter talk about "10Gb serial I/O" when they actually mean 4 bonded 2.5Gb/s channels (or 3.2Gb/s allowing for 10B/8B encoding). Of course 10Gb/s real data rate gets you into a whole new raft of issues with PCB/connectors/sockets because the edge rates are so fast -- we've done boards with a small number of 10Gb/s channels where we had to take extreme care over things like via stubs and choice of layers. Maybe the best compromise here is 5-6Gb/s per channel, which would give half the number of channels compared to 2.5-3Gb/s, but be less critical physically than 10-12Gb/s. Cheers Ian P.S. Anybody else out there have any enlightening comments on this? Austin Lesea <austin@xilinx.com> wrote in message news:<cn0ebs$ruh2@cliff.xsj.xilinx.com>... > Ian, > > MGTs for V4 are 622 Mb/s to 10 Gb/s each. They are similar to the > already shipped and working 10 Gb/s transcievers in Virtex II Pro-X. > > They can be channel bonded together for even higher aggregate data rates. > > Austin > > Ian Dedic wrote: > > > I'm looking ahead to an application in the future which will need a > > lot of DSP power but more importantly a huge amount of I/O bandwidth > > (interfacing to multiple ultra-high-speed DAC/ADCs). Up to now we've > > used parallel LVDS buses at up to 1Gs/s for this, but this eats lots > > of pins and is a PCB nightmare, so we plan to switch to serial I/O for > > which we have on-chip transceivers available. > > > > I've been trying to work out what total serial I/O capability is > > available on the latest (and near future!) FPGAs, but it's not always > > easy. In the timescales I'm looking at I guess that the likely > > candidates are Virtex-4 (for which little information is available on > > the MGTs), and whatever the "next-generation" Altera device is > > (Stratix-II doesn't have serial I/O, Stratix GX does but may be > > lacking in processing power) -- can anyone at Altera give any clue > > about this? > > > > For Virtex-4 I'm confused about what the actual serial data rate on > > each pin pair is for the MGT -- I understand that there are up to 20 > > MGT, and that these can be "up to 12GB/s", but I assume that this is > > done by bonding together 4 physical 3Gb/s channels into 1 virtual > > 12Gb/s channel -- is this correct? > > > > In that case each block of 4 MGTs can do 12Gb/s; if not then this is > > the rate for each MGT, but I think this is extremely unlikely -- 300ps > > bit period is OK since it needs rise/fall times of about 80ps which is > > achievable in this technology, but 80ps bit period needs 20ps tr/tf > > which is not! > > > > So it seems that both Altera and Xilinx are similar here; both use > > blocks of 4 transceivers at 3.125/3.25Gb/s per channel, or 12.5/13Gb/s > > per block. Both have a maximum of 5 blocks (20 channels) per chip. > > > > Is this correct? > > > > What's coming in the next couple of years as far as serial I/O is > > concerned? > > > > Cheers > > > > Ian Dedic > > Chief Engineer > > Mixed Signal Division > > Fujitsu Microelectronics Europe > > > > P.S. If there are things which can only be revealed under NDA, please > > contact me off-list since we have NDAs with both Xilinx and Altera.Article: 75688
Why my NCVerilog fail to annotate these three timing checks? Thanks Kelvin Annotating SDF timing data: Compiled SDF file: sdm_wlan_worst_max.sdf.X Log file: Backannotation scope: tsdg.sdm_wlan Configuration file: MTM control: Scale factors: Scale type: ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (RECOVERY (posedge CL) (posedge CK) (64.11)) of instance tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20. ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (SETUP (posedge D) (posedge CK) (188.037)) of instance tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20. ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (SETUP (negedge D) (posedge CK) (187.369)) of instance tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20. ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (HOLD (posedge D) (posedge CK) (114.384)) of instance tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20. ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (HOLD (negedge D) (posedge CK) (114.766)) of instance tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20. ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (RECOVERY (posedge CL) (posedge CK) (64.11)) of instance tsdg.sdm_wlan.r_ovf3_reg of module SCJFD21S20. ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (SETUP (posedge D) (posedge CK) (189.775)) of instance tsdg.sdm_wlan.r_ovf3_reg of module SCJFD21S20. ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (SETUP (negedge D) (posedge CK) (187.682)) of instance tsdg.sdm_wlan.r_ovf3_reg of module SCJFD21S20. ...Article: 75689
"Veronica Matthews" <ikeepthespiritalive@freenet.de> wrote in message news:cmvum3$ici$1@news.cs.tu-berlin.de... > Dear newsgroup community, > > recently I came across the following challenge. There are several digital > values which I want to convert to analog signals. Ok then, no problem. > Simply D/A conversion! But after converting the signals the general set up > requires that these values should be held for about - let's say - a period > of 5 minutes with practically no droop (decay of the analog value) at > best! > The D/A conversion itself takes place in a 1 MHz period, the values to be > set have to pend for about 5 minues. I guess a hold-element (capacitor and > op-amp) would be the obvious choice. But how should I dimension the > capacitance and how can I affect the droop? Is it realistic to expect > virtually no droop assuming an optimal configuration ? Isn't it, that with > a > large time constant the charging time would be endless, too? Please help > me, > if you can. I am almost become desperate. I need this for my graduation > report. > > Thank you in advance and many greets > Veronica > I guess you agree that this is a rather strange requirment! As you said before, let's not talk WHY you need to do so in the first place, and just think of HOW you can do it. The simplest solution would be to use a sample and hold IC. These ICs include a very low drift output op-amp, a very high impedance switch and rely on an external capacitor for the "sampling" of the input voltage. As an example, you can take a look at this: http://www.national.com/pf/LF/LF198.html The critical parameter for you is deltaV / deltaT for the hold state. Typically, this value is round one milivolts per second for a good quality 1u capacitor! So for 5 minutes that would be round 0.3 volts. Maybe you can find a better part than LF198 but the big problem is to find a very high quality capacitor that it's internal impedance is actually much higher than the input impedance of the sample and hold IC. The advantage of using ICs like that is their tiny size and small board area (you just need one small IC and one capacitor). Regards Arash SalarianArticle: 75690
Hi, does "Demote assignments" mean that all back-annotated assignments are removed? Thank you for your help. Rgds AndréArticle: 75691
Does anyone have experience with Green Hills' Integrity with a Virtex-II Pro Dev Board? I'm looking for a board which must have an Ethernet PHY and should already be supported (since I don't want to write my own Board Support Package). I found out, that the Memec fg456 is already supported, but in order to use Ethernet with this board you have to use a daughter card (P160 communications module). Is this possible with the available BSP or must it be changed? I'm just beginning to start using Integrity. Thanks a lot!Article: 75692
gabor@alacron.com (Gabor Szakacs) wrote in message news:<8a436ba2.0411111318.2e00b060@posting.google.com>...
> Try the Virtex II datasheet. It shows a block diagram
> where even the two data bits don't connect to the
> "DDR MUX" so it works with no inputs!
>
> If you go into the FPGA editor you see something
> similar and while you hold your mouse over the
> mux the popup description includes the words
> black box.
>
> I think Xilinx is trying to simplify the diagram to
> reduce clutter. The mechanism must have the clocks
> because it has to switch on the rising edge of each
> input clock (after the programmable inversion). If I
> had to code this in Verilog it would look like:
>
> always @ (posedge FF1CLK) muxout <= FF1Q;
> always @ (posedge FF2CLK) muxout <= FF2Q;
>
> although I doubt the synthesizer would infer a DDR
> flop from this code.
>
> hmurray@suespammers.org (Hal Murray) wrote in message news:<WIudnfKZPqlYVQ_cRVn-vw@megapath.net>...
> > I'm looking at the IOB diagram for Spartan3. The output
> > path has a block labled "DDR MUX" that seems like it should
> > do the obvious thing.
> >
> > It's got two inputs - the data bits.
> >
> > How does it know when to switch? Does it get both clocks
> > too, through some path that isn't shown?
The component template gives some insight on the connections.
I used it to forward a clock in a VirtexII, and used the DCM phase adjust
to optimize the timing.
I was excited about using this for clock forwarding. Others did not share
my excitement. I must be a geek. Anybody got an extra Virtex-4 Xilinx
T-Shirt they are willing to part with. I don't mind if it is wrinkled :}
- Newman
----------------------------------------------------------------
component FDDRCPE
port(
-- INPUTS--
C0 : in std_logic;
C1 : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
PRE : in std_logic;
-- OUTPUTS
Q : out std_logic
);
end component FDDRCPE; -- FDDRCPE
Article: 75693Is there a way to list the unconstrained paths? The timing report with trace -u only lists the number of unconstrained paths and the maximum delay. I would like to see them to assert that I have not missed a vital path in my constraints.Article: 75694
Based on the choices made in the Demote assignments dialog box, you can convert LE assignments into LAB assignments and so on. Demote assignments would be useful if you have an overconstrained placement and would then like to relax these placement constraints. Therefore to answer your question your LE assignments would be removed and added back as LAB assignments. If you want to keep a backup of your LE assignments create a new revision using the current revision which has the LE assignments as the base. Then do a Demote assignments on the new revision. You can switchback to the old revision if needed. - Subroto "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0411120419.37c02305@posting.google.com... > Hi, > > does "Demote assignments" mean that all back-annotated assignments > are removed? > > Thank you for your help. > > Rgds > AndréArticle: 75695
Me too! Dwayne --------------------------------- Hendra wrote: > How did you get the T-Shirt? I would like to get one! > > HendraArticle: 75696
Unfortunately, I can't find the Dilbert episode, but it seems to me that Dilbert had invented a tube to stuff clothing into. He named it "dorkage" :-) Dwayne Surdu-Miller -------------------- Lasse Langwadt Christensen wrote: > John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<cmu719$av8$1@bunyip.cc.uq.edu.au>... > >>Bob, >> >>Bob Perlman wrote: >> >>>On 10 Nov 2004 13:30:48 -0800, wpiman@aol.com (MS) wrote: >>> >>>>I haven't tried washing it yet. Has anyone managed to get all the >>>>wrinkles out? >>> >>>Forgive me for asking, but if you object to wearing a free, wrinkled >>>T-shirt, are you absolutely certain you're an engineer? >> >>That's priceless - deserves to be printed and framed! >> >>John > > > reminds me of this one :)) > > http://www.dilbert.com/comics/dilbert/archive/images/dilbert200411095097.jpg > > > -LasseArticle: 75697
On Fri, 12 Nov 2004 18:14:45 +0800, "Kelvin" <thefatcat28@hotmail.com> wrote: >Why my NCVerilog fail to annotate these three timing checks? > Annotating SDF timing data: > Compiled SDF file: sdm_wlan_worst_max.sdf.X >ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check >(RECOVERY (posedge CL) (posedge CK) (64.11)) of instance Check your verilog models and you'll see that the check is from CL to posedge CK so there is really no (posedge CL) check. You need to replace (RECOVERY (posedge CL) (posedge CK) (64.11)) of instance with (RECOVERY CL (posedge CK) (64.11)) of instanceArticle: 75698
Just as a follow-up: The original question is a good one. When one sees a 2:1 mux, one may wonder if it is susceptable to static hazard one and static hazard zero glitches. I've seen that Xilinx recommends using this component for clock forwarding, which implies that it is not subject to such. When I reviewed the design in the FPGA editor, the inverter in the C1 path was apparently absorbed into the IOB. In some App note for high speed designs, it was recommended that the 180 DCM output be used for C1. Since my design was not high speed, and I was running out of clock buffers on that side of the chip, I opted for the merged inverter. Apparently the "DDR Mux" uses two clocks, and it is unclear exactly how it does that. - NewmanArticle: 75699
Ian, Well, I certainly understand that a speed bump to a 6 Gbs is more like a roadblock to a 10 Gbs signal. Until everything catches up (pcb technology, SI engineering) not going for 10 Gbs if you don't have to is probably a good idea. 6.25 Gbs is looking quite nice, as you say, given pcb and connector technologies. And, yes, I am aware that most people mean 4 X 3.125 Gbs (using 8b10b) which yields an actual total aggregate bit rate of 10 Gbs when you say "10 Gbs channel." Remember to divide by the coding scheme overhead to get the actual useful bit rate. (so even 10 Gbs using 8b/10b is less than 10 Gbs of useful data -- even though the bits do fly by at that 10 Gbs rate) There is another coding scheme that is used at the higher rates, 64b66b, which is much more efficient (more useful bits than 8b10b). We support this coding scheme, too. Austin Ian Dedic wrote: > Hi Austin > > Thanks for that -- I wasn't really sure that the Pro-X and V4 were > 10Gb/s per channel (pair of differential pins), since people ofter > talk about "10Gb serial I/O" when they actually mean 4 bonded 2.5Gb/s > channels (or 3.2Gb/s allowing for 10B/8B encoding). > > Of course 10Gb/s real data rate gets you into a whole new raft of > issues with PCB/connectors/sockets because the edge rates are so fast > -- we've done boards with a small number of 10Gb/s channels where we > had to take extreme care over things like via stubs and choice of > layers. Maybe the best compromise here is 5-6Gb/s per channel, which > would give half the number of channels compared to 2.5-3Gb/s, but be > less critical physically than 10-12Gb/s. > > Cheers > > Ian > > P.S. Anybody else out there have any enlightening comments on this? > > Austin Lesea <austin@xilinx.com> wrote in message news:<cn0ebs$ruh2@cliff.xsj.xilinx.com>... > >>Ian, >> >>MGTs for V4 are 622 Mb/s to 10 Gb/s each. They are similar to the >>already shipped and working 10 Gb/s transcievers in Virtex II Pro-X. >> >>They can be channel bonded together for even higher aggregate data rates. >> >>Austin >> >>Ian Dedic wrote: >> >> >>>I'm looking ahead to an application in the future which will need a >>>lot of DSP power but more importantly a huge amount of I/O bandwidth >>>(interfacing to multiple ultra-high-speed DAC/ADCs). Up to now we've >>>used parallel LVDS buses at up to 1Gs/s for this, but this eats lots >>>of pins and is a PCB nightmare, so we plan to switch to serial I/O for >>>which we have on-chip transceivers available. >>> >>>I've been trying to work out what total serial I/O capability is >>>available on the latest (and near future!) FPGAs, but it's not always >>>easy. In the timescales I'm looking at I guess that the likely >>>candidates are Virtex-4 (for which little information is available on >>>the MGTs), and whatever the "next-generation" Altera device is >>>(Stratix-II doesn't have serial I/O, Stratix GX does but may be >>>lacking in processing power) -- can anyone at Altera give any clue >>>about this? >>> >>>For Virtex-4 I'm confused about what the actual serial data rate on >>>each pin pair is for the MGT -- I understand that there are up to 20 >>>MGT, and that these can be "up to 12GB/s", but I assume that this is >>>done by bonding together 4 physical 3Gb/s channels into 1 virtual >>>12Gb/s channel -- is this correct? >>> >>>In that case each block of 4 MGTs can do 12Gb/s; if not then this is >>>the rate for each MGT, but I think this is extremely unlikely -- 300ps >>>bit period is OK since it needs rise/fall times of about 80ps which is >>>achievable in this technology, but 80ps bit period needs 20ps tr/tf >>>which is not! >>> >>>So it seems that both Altera and Xilinx are similar here; both use >>>blocks of 4 transceivers at 3.125/3.25Gb/s per channel, or 12.5/13Gb/s >>>per block. Both have a maximum of 5 blocks (20 channels) per chip. >>> >>>Is this correct? >>> >>>What's coming in the next couple of years as far as serial I/O is >>>concerned? >>> >>>Cheers >>> >>>Ian Dedic >>>Chief Engineer >>>Mixed Signal Division >>>Fujitsu Microelectronics Europe >>> >>>P.S. If there are things which can only be revealed under NDA, please >>>contact me off-list since we have NDAs with both Xilinx and Altera.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z