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Messages from 76375

Article: 76375
Subject: Re: Running EDK 6.2i with ISE6.3i
From: "massoud shakeri" <shakeri@no_spam_please.telus.net>
Date: Wed, 01 Dec 2004 08:19:15 GMT
Links: << >>  << T >>  << A >>
Thank you.
It solved my problem

Regards
Massoud

"Holger Nissle" <Holger.Nissle@leica-microsystems.com> wrote in message 
news:coi79t$sje$1@nella.toplink-plannet.de...
> After installation of ISE 6.3 there is a new executable in edk/bin/nt:
> _xps.exe
> This might work. Or try to invoke XPS_GUI.exe directly.
>
> Holger
>
> "massoud shakeri" <shakeri@no_spam_please.telus.net> wrote in message
> news:iTyqd.200226$df2.155920@edtnps89...
>> Hi All:
>> I have installed ISE6.3i and EDK 6.2i. When I run "platform studio" it
> show
>> the following message:
>> "$XILINX does not point to an ISE 6.2 installation"
>> and does not work.
>> I am wondering if there is any way to have EDK ruuning with ISE 6.3?
>> Thank you in advance.
>> Massoud
>>
>>
>
> 



Article: 76376
Subject: Re: 99% Utilisation !
From: jon@beniston.com (Jon Beniston)
Date: 1 Dec 2004 01:45:29 -0800
Links: << >>  << T >>  << A >>
> Reference Xcell journal Issue 50 Fall 2004
> Introduced in September 2003, ISE 6 adds a new timing driven map option that 
> helps get better design utilization for your FPGA devices, particularly if 
> the device is already 90% utilized.  Timing driven map is a next generation 
> enhancement to ISE physical synthesis placement with logic slice packing for 
> Virtex-II, Virtex-II Pro and Spartan-3 devices to improve placement quality 
> for unrelated logic.


Hmmm. Every time I've used this it's always slowed down my design.
 
Cheers,
JonB

Article: 76377
Subject: clocks switch
From: dan.costin@gmail.com (Dan)
Date: 1 Dec 2004 01:49:16 -0800
Links: << >>  << T >>  << A >>
A have 3 clocks(clk1, clk2, clk3) and I need to make a switch between
these 3 clocks. My output master clock is CLK. I have a  parameter,
let's say 1000.
I need  to make first 200 pulses of CLK with clk1, then 600 pulses of
CLK with clk2, then last 200 pulses of CLK with clk3. How can I
implement this in verilog??
  
 
  Thanks,

Article: 76378
Subject: Weird XPower results for FSMs and different FPGAs
From: "Patrick Kulle" <pkulle@gmx.de>
Date: Wed, 1 Dec 2004 11:58:09 +0100
Links: << >>  << T >>  << A >>
Hello,

I'm currently comparing different state encodings (e.g. One-Hot, Gray,
Binary) on their power consumption. The state-machine itself is
synthesized and mapped with the Xilinx WebPack tools. Then I simulate it
with a input sequence and finally check the power the state-machine used
with XPower. The state-machine is the only code placed on the chip and
simulated.

Now I face the following problem. If I do the steps described above for
a Spartan 2 I get results that show a difference of some percents which
seem to be realistic. If I do the steps above for a Virtex 2 I get the
_identical_ power consumption for all different types of encoding.

I expected that both chips would behave in the same manner. Has anybody
of you an idea what my failure is, where the problem is or why the
Virtex 2 power consumption is constant? I'm using the most recent
version of the Web-Pack and have applied the service pack 2.

Thanks in advance
Patrick


Article: 76379
Subject: Re: 99% Utilisation !
From: "newman5382" <newman5382@yahoo.com>
Date: Wed, 01 Dec 2004 12:03:29 GMT
Links: << >>  << T >>  << A >>

"Jon Beniston" <jon@beniston.com> wrote in message 
news:e87b9ce8.0412010145.4af756ec@posting.google.com...
>> Reference Xcell journal Issue 50 Fall 2004
>> Introduced in September 2003, ISE 6 adds a new timing driven map option 
>> that
>> helps get better design utilization for your FPGA devices, particularly 
>> if
>> the device is already 90% utilized.  Timing driven map is a next 
>> generation
>> enhancement to ISE physical synthesis placement with logic slice packing 
>> for
>> Virtex-II, Virtex-II Pro and Spartan-3 devices to improve placement 
>> quality
>> for unrelated logic.
>
>
> Hmmm. Every time I've used this it's always slowed down my design.
>
> Cheers,
> JonB

JonB,

It definitely takes map longer to run.  I was using XST 6_2i sp3 with a goal 
of 100 MHz (Spartan 3 - 1500).  I initially kept all the hierarchy, but when 
I went over 90%, I started to get nervous and had XST flatten the design. 
The utilization went down by 5% to 7%, but the timing deteriorated. After 
several recode attempts to speed up the critical path, only to have another 
unrelated path show a slow down, I went to timing driven map and used 
selective keep hierarchy attributes in some of the modules "perhaps a lazy 
man's floor plan".  Utilization stayed about the same, and internal timing 
was met with ease.  Perhaps I attributed too much of timing improvement to 
the timing driven map, and not enough to the selective keep hierarchy.

-Newman




Article: 76380
Subject: Re: CMOS capacitive loads, transition probabilities and FPGAs
From: "Ken" <aeu96186@NOSPAM.yahoo.co.uk>
Date: Wed, 1 Dec 2004 14:26:51 +0100
Links: << >>  << T >>  << A >>
>  I think the OP was just
> confused about the variations in the formulae.  It is just a matter of
> how you figure the constant.  Normally the constant is measured rather
> than calculated, so you just need to use the formulae that you are given
> with the constant.

On the subject of variations and locations of 0.5 and 2 factors:

if we have

C as the node capacitance
'a' as the transition density (0 to 1 and 1 to 0) at the node
then
P = 0.5aCV^2F
holds I believe?

Alternatively,

If 'a' is only counting "power consuming" 0 to 1 transitions then we have:

P = 0.5(a*2)CV^2F
= aCV^2F

Correct?

Or is the factor of 2/0.5 worked into the C constant?

Ken





Article: 76381
Subject: Re: Xilinx Virtex 4 question
From: Thomas Reinemann <thomas.reinemann@mb.uni-magdeburg.de>
Date: Wed, 01 Dec 2004 15:53:27 +0100
Links: << >>  << T >>  << A >>
Austin Lesea wrote:

> For more information, contact your local FAE.

Starting with a XAPP would be more effective, but I didn't find anything.
Particular interesting are an ucf example and something like a "bus macro".
AFAIK V4 has no TBUFs, how to establish inter module connections, which
survive reconfiguration?

Bye Tom

Article: 76382
Subject: Altera equivalent for Xilinx's "async_reg" attribute
From: Nicolas Matringe <matringe.nicolas@numeri-cable.fr>
Date: Wed, 01 Dec 2004 15:54:31 +0100
Links: << >>  << T >>  << A >>
Hello
The question is in the subject: is there such a thing?
How to make an Altera post-p&r simulation work when a setup violation 
occurs on an input register?
-- 
  ____  _  __  ___
|  _  \_)/ _|/ _ \   Adresse de retour invalide: retirez le -
| | | | | (_| |_| |  Invalid return address: remove the -
|_| |_|_|\__|\___/


Article: 76383
Subject: Re: clocks switch
From: "Matthew Plante" <maplante@iol.unh.edu>
Date: Wed, 1 Dec 2004 10:21:42 -0500
Links: << >>  << T >>  << A >>
Hi Dan,

  You can use an assignment statement to create a  input mux to switch your 
clocks.  Something like this should do the trick:

module mux3 (clk1, clk2, clk3, select, clkout);

input clk1, clk2, clk3;
input [1:0]select;
output clkout;

wire clkout;

assign clkout = select == 2'b00 ? clk1 : select == 2'b01 ? clk2 : clk3; // 
10 or 11 would select clk3

endmodule

Then all you need to do is to make a counter that's based on the selected 
clkout to change your switch signal.

Just something like   always @(posedge clkout)  counter <= counter + 1'b1;

-- Matt

"Dan" <dan.costin@gmail.com> wrote in message 
news:f4e089e0.0412010149.4168b173@posting.google.com...
>A have 3 clocks(clk1, clk2, clk3) and I need to make a switch between
> these 3 clocks. My output master clock is CLK. I have a  parameter,
> let's say 1000.
> I need  to make first 200 pulses of CLK with clk1, then 600 pulses of
> CLK with clk2, then last 200 pulses of CLK with clk3. How can I
> implement this in verilog??
>
>
>  Thanks, 



Article: 76384
Subject: Re: block ram and bmm files
From: "Matthew Plante" <maplante@iol.unh.edu>
Date: Wed, 1 Dec 2004 10:32:46 -0500
Links: << >>  << T >>  << A >>
Hi Newman,

  I am fairly new to the embedded side of the v2ps.  From what I understand, 
the typical design flow for an embedded design is as follows:

1.) Create base design in XPS (jtag, ppc, bram, c program)
2.) build libs and bsps in xps
3.) export to projnav
4.) make any hdl changes/additions you want to interface the ppc with the 
fpga
5.) make the bitstream
6.) import the updated bitstream and bmm file into xps
7.) compile your c code
8.) then run update bitstream to stick your c code in the brams
9.) download to fpga.

So step 2 creates a bmm file for you, that has all the memory locations used 
by the ppc design.  When you export that to projnav, and add in your own 
bram (or rom in this case, whatever), you need to edit the bmm file and 
specify the location of the bram?  This is what I'm unsure of: how to 
specify this.  If I try to edit it as I mentioned below, when i import it 
back to XPS, and update the bitstream, this is the error message I get:

Running Data2Mem with the following command:
data2mem -bm implementation/system_bd -bt implementation/system.bit  -bd
TestApp/executable.elf tag pattern_rom plb_bram_if_cntlr_1_bram  -o b
implementation/download.bit

WARNING:Data2MEM:80 - ADDRESS_SPACE or ADDRESS_MAP tag name 'pattern_rom' 
was
not found.
    Some data may have not been translated.

ERROR:MDT - Data2Mem generated errors during execution
make: *** [implementation/download.bit] Error 1
Done.


I've read the data2mem docs, and saw that there is some way for it to create 
the bmm file for you, but I'm not exactly sure how to do this.

--Matt


"newman5382" <newman5382@yahoo.com> wrote in message 
news:fo4rd.107164$6w6.1499@tornado.tampabay.rr.com...
> What is the motivation for exporting it back to XPS?  What is the nature 
> of the data2mem errors?
>
> Maybe I had a similar but different problem that you have.  I had code 
> located in external flash. I modified the bmm file and added some stuff 
> similar to Xilinx answer record 16577. I added the modified bmm file to 
> the ISE project, but did NOT include the elf file.  I let the tool crank 
> out a bit file, then I manually invoked data2bram using the tag option, 
> which IIRC indicates to data2ram, which block to load up. If I did not do 
> this, it would try to load up the external reference and "error out".
>
> -Newman
>
> --------------------------------------------------------------------------------------
> "Matthew Plante" <maplante@iol.unh.edu> wrote in message 
> news:coih22$k99$1@tabloid.unh.edu...
>> Hi folks,
>>
>>  I'm working on developing an embedded system with a xilinx v2pro fpga. 
>> I have all my code for the ppc (including 2 block rams, one on the plb 
>> and the other on the opb) done in xps, and exported it to the project 
>> navigator.  I am trying to add an additional block rom, but I don't want 
>> to add it in the EDK, I just want it to communicate directly with fpga 
>> fabric.  So, I used the core generator, and created a bram instance that 
>> is 70 bits wide, and 8k deep.  The core generator doesn't create a .bmm 
>> or .mem file to accompany this.  So how do I go about adding the proper 
>> lines to the current bmm file? I haven't found much for documentation on 
>> this. If I don't add any information for the new ram to the bmm file 
>> created by xps, then when I import the projnav files back into xps, and 
>> regenerate the bitstream, data2mem errors out on me.
>>  Currently, my bmm file looks like this:
>> ADDRESS_BLOCK plb_bram_if_cntlr_1_bram RAMB16 [0xffffc000:0xffffffff]
>> BUS_BLOCK
>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_0 
>> [63:56] ;
>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_1 
>> [55:48] ;
>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_2 
>> [47:40] ;
>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_3 
>> [39:32] ;
>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_4 
>> [31:24] ;
>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_5 
>> [23:16] ;
>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_6 
>> [15:8] ;
>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_7 
>> [7:0] ;
>> END_BUS_BLOCK;
>> END_ADDRESS_BLOCK;
>> ADDRESS_BLOCK opb_bram_if_cntlr_1_bram RAMB16 [0x00000000:0x00003fff]
>> BUS_BLOCK
>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0 
>> [31:28] ;
>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_1 
>> [27:24] ;
>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_2 
>> [23:20] ;
>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_3 
>> [19:16] ;
>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_4 
>> [15:12] ;
>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_5 
>> [11:8] ;
>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_6 
>> [7:4] ;
>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_7 
>> [3:0] ;
>> END_BUS_BLOCK;
>> END_ADDRESS_BLOCK;
>>
>> I'm not entirely sure how the rom needs to get assigned in the fpga.  I 
>> was thinking of adding a line such as:
>> ADDRESS BLOCK pattern_rom RAMB16 [0x00040000:0x00042000]
>> END_ADDRESS_BLOCK;
>> (where "pattern_rom" is my rom I added in the fpga from the coregen)
>> But, I'm not sure how to complete the BUS_BLOCK section.
>>
>> Any help would be appreciated!
>>
>> Thanks,
>>
>> -- Matt
>> maplante@iol.unh.edu
>>
>
> 



Article: 76385
Subject: Re: Weird XPower results for FSMs and different FPGAs
From: Mike Treseler <mike_treseler@comcast.net>
Date: Wed, 01 Dec 2004 07:51:01 -0800
Links: << >>  << T >>  << A >>
Patrick Kulle wrote:

> Now I face the following problem. If I do the steps described above for
> a Spartan 2 I get results that show a difference of some percents which
> seem to be realistic. If I do the steps above for a Virtex 2 I get the
> _identical_ power consumption for all different types of encoding.

Maybe the difference in power due to state encoding
is less than the uncertainty in the XPower measurement.
I expect that zero is closer to the right answer
than a few percent.

         -- Mike Treseler

Article: 76386
Subject: Re: block ram and bmm files
From: Sean Durkin <smd@despammed.com>
Date: Wed, 01 Dec 2004 17:10:35 +0100
Links: << >>  << T >>  << A >>
Matthew Plante wrote:
> Hi Newman,
> 
>   I am fairly new to the embedded side of the v2ps.  From what I understand, 
> the typical design flow for an embedded design is as follows:
> 
> 1.) Create base design in XPS (jtag, ppc, bram, c program)
> 2.) build libs and bsps in xps
> 3.) export to projnav
> 4.) make any hdl changes/additions you want to interface the ppc with the 
> fpga
> 5.) make the bitstream
> 6.) import the updated bitstream and bmm file into xps
> 7.) compile your c code
> 8.) then run update bitstream to stick your c code in the brams
> 9.) download to fpga.
> 
> So step 2 creates a bmm file for you, that has all the memory locations used 
> by the ppc design.  When you export that to projnav, and add in your own 
> bram (or rom in this case, whatever), you need to edit the bmm file and 
> specify the location of the bram?  This is what I'm unsure of: how to 
> specify this. 
You don't need to. When you implement the design in ProjNav, "map" and 
"par" assign the BRAMs to the various memory regions, and you get an 
additional bmm-file (that's the one with _bd added to the filename). In 
this BMM the locations are already specified, according to how the tools 
implemented everything. If you change anything here it won't work as 
expected (if at all).

So in step 6 what you need to do is import the bram_bd.bmm file, not the 
original .bmm created in step 2.

But I'm not sure how it works if you add more BRAMs in your toplevel in 
ProjNav if you have to initialize those as well...

cu,
Sean

Article: 76387
Subject: Controller Interface
From: ALuPin@web.de (ALuPin)
Date: 1 Dec 2004 08:15:45 -0800
Links: << >>  << T >>  << A >>
Hi newsgroup,

can someone tell me if an interface to a standard microcontroller
exists in order to interface a DDR SDRAM controller
to the microcontroller part which is responsible for WRITE and READ
requests ?

It could be some kind of standard microcontroller interface or DMA controller.

The problem is that I want to simulate the DDR SDRAM Controller and need
some data 'source'. 
IP cores and reference designs show how to interface directly to
the DDR SDRAM but the essential part of interfacing to the data 'source'
is missing.

Does somebody know of simple VHDL simulation models for such a microcontroller
interface? Or any papers ... ?

Thank you for your help.

Rgds
André

Article: 76388
Subject: Re: Xilinx Virtex 4 question
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 01 Dec 2004 08:28:37 -0800
Links: << >>  << T >>  << A >>
Tom,

There is a SDR project that uses partial reconfiguration to load the 
differing modulation/demodulation formats.  They use a form of file 
system to represent the FPGA (I have seen it, it is realy neat -- you 
can look at the FPGA using a browser, and it looks like a file system).

Connections to and from the reloadable modules are simply hard loc'd 
interconnect paths (each modem uses the same inputs and outputs).

Switching modems is easy, because there is nothing to do while you 
switch from one to another, except wait until data starts coming out of 
the modem.

The 405PPC (or microblaze) is used to recognize the modem that is needed 
(what format are they talking in? or what format do I want to transmit 
with? and supervise the loading).

I won't say this is an easy design task, because the tools are all still 
experimental, and they are just not 'all there' yet.

But, it does appear as if this will be used at least for the software 
defined radio case (is being used right now).

How this may be extended, and what other applications may benefit is yet 
to be determined.

My favorite example of reconfiguration is one where when you turn a knob 
on the front panel of the instrument, it then figures out what partial 
bistream to load to do what you just selected (a real application as 
well).  Again, nothing needs to be done while the bitstream is loading.

Contacting the FAE is the only way one can gain access to this work, as 
it is still specialized, and half in Xilinx Labs (the research arm of 
Xilinx), and half in the field.

Austin

Thomas Reinemann wrote:
> Austin Lesea wrote:
> 
> 
>>For more information, contact your local FAE.
> 
> 
> Starting with a XAPP would be more effective, but I didn't find anything.
> Particular interesting are an ucf example and something like a "bus macro".
> AFAIK V4 has no TBUFs, how to establish inter module connections, which
> survive reconfiguration?
> 
> Bye Tom

Article: 76389
Subject: Re: CMOS capacitive loads, transition probabilities and FPGAs
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 01 Dec 2004 08:31:02 -0800
Links: << >>  << T >>  << A >>
Rick,

Thanks for clearing that up.  Good way to think about it.  The 1/2CV^2 
comment was confusing, I agree.

Austin

rickman wrote:

> Austin Lesea wrote:
> 
>>Ken,
>>
>>A commont confusion is what dissipates power?
>>
>>When you charge a node, you waste power in the resistance of the
>>charging transistor.
>>
>>When you discharge a node, you then waste power in the resistance of the
>>discharging transistors (both generate heat).
>>
>>If both edges generate heat, then you have to count them both.
>>
>>The energy stored in a capacitor is 1/2 CV^2, but don't let that confuse
>>you:  you have to put it in, and then take it out!  The devices that do
>>the work dissipate the power.
> 
> 
> This is a bit misleading and irrelevant.  The fact that power is only
> dissipated in the resistance has nothing to do with the total amount of
> energy expended in charging and discharging a capacitor.  Regardless of
> what value resistance, even if it is not constant, the energy drawn from
> the supply is the same as long as the capacitor is charged to the same
> voltage.  The energy may be dissipated in the transistor or in the poly
> track or a metal track or the bond wire or the external pin or even in
> the wire from the power supply to the board.  But add them all up and
> you will get the same value each time you charge a capacitor to a given
> voltage.  
> 
> So the amount of power consumed is related to the frequency of
> transitions and the size of the capacitance.  Whether you calculate it
> from the rate of the rising edges or both edges is not relevant, that
> just changes the constant that you use by a factor of 2.  As the OP
> said, when you charge the cap from 0 volts to Vcc, half goes into the
> cap and half is wasted.  But the total always comes from the PSU and is
> always the same amount.  
> 
> You can't have a 0 to 1 transition without a 1 to 0 transition, so why
> is this even an issue?  
> 

Article: 76390
Subject: Re: CMOS capacitive loads, transition probabilities and FPGAs
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 01 Dec 2004 11:53:09 -0500
Links: << >>  << T >>  << A >>
Ken wrote:
> 
> >  I think the OP was just
> > confused about the variations in the formulae.  It is just a matter of
> > how you figure the constant.  Normally the constant is measured rather
> > than calculated, so you just need to use the formulae that you are given
> > with the constant.
> 
> On the subject of variations and locations of 0.5 and 2 factors:
> 
> if we have
> 
> C as the node capacitance
> 'a' as the transition density (0 to 1 and 1 to 0) at the node
> then
> P = 0.5aCV^2F
> holds I believe?
> 
> Alternatively,
> 
> If 'a' is only counting "power consuming" 0 to 1 transitions then we have:
> 
> P = 0.5(a*2)CV^2F
> = aCV^2F
> 
> Correct?
> 
> Or is the factor of 2/0.5 worked into the C constant?

Actually, I don't recall ever seeing a formula with the "a"
coefficient.  I have always just worked with a variable F to account for
differences in the number of transitions.  

The energy required to move charge onto a capacitor is Q*V.  As you move
more charge onto the capacitor the voltage rises linearly with the
amount of charge so that V = Q/C.  The total amount of energy stored on
the capacitor at any voltage is the integral of the V vs. Q curve which
is Int(V dQ) = Int(C*V dV) = 0.5 * C * V^2.  If the capacitor is charged
fully from a constant voltage source via a resistor, the curve to
integrate is just a constant Vcc vs. Q which gives you an integral of C
* Vcc^2.  If you want a power level you must multiply by F, the rate of
charging the cap (not discharging since that consumes no extra power, it
just dissapates the power stored in the cap).  That gives you P =
F*C*V^2.   So the whole "where did the 0.5 come from" question has no
answer.  There is *no* 0.5 inherent in the equation.  If someone wants
to change it by counting *both* the positive and negative transitions,
then you will have to multiply by 0.5 to compensate.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 76391
Subject: Re: Xilinx Virtex 4 question
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 01 Dec 2004 11:58:48 -0500
Links: << >>  << T >>  << A >>
Thomas Reinemann wrote:
> 
> Austin Lesea wrote:
> 
> > For more information, contact your local FAE.
> 
> Starting with a XAPP would be more effective, but I didn't find anything.
> Particular interesting are an ucf example and something like a "bus macro".
> AFAIK V4 has no TBUFs, how to establish inter module connections, which
> survive reconfiguration?

I have looked into this and both the Spartan 3 and Virtex 4 devices have
no tbufs, therefore are not currently supported in the design software
for partial reconfiguration.  I was told that the Virtex 4 would be
supported first with the next major release of the tools in Q1 of next
year and the Spartan 3 would be added when feasible.  But then I was
told that Xilinx was working toward supporting the Spartan 3 nearly a
year ago.  :)

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 76392
Subject: Compact Flash Peripheral Design with FPGA
From: gpsabove@yahoo.com (Johnson)
Date: 1 Dec 2004 09:10:47 -0800
Links: << >>  << T >>  << A >>
Hello,

I am currently involved in designing a Compact Flash Peripheral --- a
GPS Receiver for TDS Recon or PocketPC. The power consumption is very
critical. Does anybody know any xilinx parts have requirements close
to or less than 100mA?

Could anybody please let me know the advantages to use FPGA for the CF
peripheral, other than a DSP or ASIC? You know the price is quite
different.

Is it important for the CF GPS Receiver to support all three modes of
CF (Memory, I/O, and True IDE)? If we want to support all 3 modes,
which one is a better choice for the project, FPGA or DSP?

Could anybody please 

Thank you very much in advance.

Johnson

Article: 76393
Subject: Re: Xilinx Virtex 4 question
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 01 Dec 2004 12:18:52 -0500
Links: << >>  << T >>  << A >>
Andreas Schallenberg wrote:
> 
> Hi!
> 
> rickman wrote:
> > I am still waiting for MDPR support for the Spartan 3, even without the
> > rest of the chip running (which the Spartan 3 won't do).  I just want to
> > make my designs truely modular at configuration time to match the
> > hardware configuration rather than to have to produce thousands of
> > different configurations.  I am now being told they will get right on
> > that *after* they have done the Virtex 4 MDPR.
> >
> This is interesting. What general type of application are you doing?
> What are the parts you need to exchange? I'm interested in such things since
> we have a discussion on a somewhat regular basis wether reconfiguration
> (runtime or not) makes sense for what applications.

MDPR is very important for my application, so much that I am designing
in the Spartan 3 in spite of the fact that I have no firm commitment
from Xilinx that the Spartan 3 devices will ever be supported for MDPR. 
I am working on a board which accepts hardware modules as user
configurable plug ins.  Each of these modules can have a unique
interface.  The module type can be identified at boot time.  At that
time the FPGA needs to be loaded with design modules to provide the
appropriate interface.  With four module sites and potentially a dozen
different module types, you can see that the number of combinations are
enormous.  Even trying to pare this down by limiting the combinations
does not reduce the complexity to an acceptable level.  

My plan is to support this configuration problem by modularizing the
design and loading the appropriate interface in the same way that
drivers are loaded by an operating system at boot time.  I don't need
for the FPGA to be running, I just need to be able to select the modules
from a store and load them to match the hardware.  This will let me
create a fixed number of designs for each module type and combine them
at load time to create the large number of configurations that need to
be supported.  

I have already found some limitations with the approach.  A big one is
that the columns in the Xilinx FPGAs are not equivalent, but have
special configuration bits near the edges.  But this only requires that
each module have 4 varieties to fit the 4 slots.  Still nowhere near the
problem of the number of designs required without MDPR.  

Using a Virtex chip which is supported for MDPR is not an option due to
the high price relative to the application.  

I assume that this is not requested more for the low cost devices
because modularity is typically handled with standard interfaces.  But
in this case the standard interface is inside the FPGA to avoid needing
additional logic on the module.  The cost of the interface is absorbed
into the FPGA keeping the recurring module cost to a minimum.  Kindof
the ultimate low cost use of a low cost FPGA.  

But without MDPR the cost of generating the FPGA bitstreams required
will be much higher and any one flash load will only be able to host a
small fraction of the total number of combinations.  

If someone is interested in using this as an example for research, I am
happy to cooperate.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 76394
Subject: Re: block ram and bmm files
From: "newman5382" <newman5382@yahoo.com>
Date: Wed, 01 Dec 2004 17:23:32 GMT
Links: << >>  << T >>  << A >>

"Matthew Plante" <maplante@iol.unh.edu> wrote in message 
news:coko6v$68c$1@tabloid.unh.edu...
> Hi Newman,
>
>  I am fairly new to the embedded side of the v2ps.  From what I 
> understand, the typical design flow for an embedded design is as follows:
>
> 1.) Create base design in XPS (jtag, ppc, bram, c program)
> 2.) build libs and bsps in xps
> 3.) export to projnav
> 4.) make any hdl changes/additions you want to interface the ppc with the 
> fpga
> 5.) make the bitstream
> 6.) import the updated bitstream and bmm file into xps
> 7.) compile your c code
> 8.) then run update bitstream to stick your c code in the brams
> 9.) download to fpga.
>
> So step 2 creates a bmm file for you, that has all the memory locations 
> used by the ppc design.  When you export that to projnav, and add in your 
> own bram (or rom in this case, whatever), you need to edit the bmm file 
> and specify the location of the bram?  This is what I'm unsure of: how to 
> specify this.  If I try to edit it as I mentioned below, when i import it 
> back to XPS, and update the bitstream, this is the error message I get:
>
> Running Data2Mem with the following command:
> data2mem -bm implementation/system_bd -bt implementation/system.bit  -bd
> TestApp/executable.elf tag pattern_rom plb_bram_if_cntlr_1_bram  -o b
> implementation/download.bit
>
> WARNING:Data2MEM:80 - ADDRESS_SPACE or ADDRESS_MAP tag name 'pattern_rom' 
> was
> not found.
>    Some data may have not been translated.

Step 2A is build all user applications.  At this point I usually have the 
executable.elf.  I either stay in XPS, or if I go to ISE and  stay in ISE. 
You say you are rather new to XPS.  Well you are not alone because everytime 
Xilinx ups the rev of EDK, it is like starting all over again.  I'm 
currently at EDK 6.2.
If you look at system_bd.bmm, I suspect that you will find a tag named 
plb_bram_if_cntlr_1.  Do you find a tag named pattern_rom?  If not, why does 
the warning surprise you?  Is the initialization for the pattern_rom located 
in the executable.elf?  If not, what is the purpose of running data2mem with 
a tag of pattern_rom.  Is the pattern_rom accessed by the PPC, if not, then 
why go back to XPS.  Is the pattern_rom independent of the PPC, can you get 
by with the regular bram initialization style, then data2mem would seem to 
be superfluous for the pattern_rom.  I would look at the 
plb_bram_if_cntl_1_bram section of system.bmm and system_bd.bmm.  If you can 
understand the relationships between the elf, implementation, and bmm files, 
then you should be able to figure out what to do with your pattern_rom.

-- Newman

>
> ERROR:MDT - Data2Mem generated errors during execution
> make: *** [implementation/download.bit] Error 1
> Done.
>
>
> I've read the data2mem docs, and saw that there is some way for it to 
> create the bmm file for you, but I'm not exactly sure how to do this.
>
> --Matt
>
>
> "newman5382" <newman5382@yahoo.com> wrote in message 
> news:fo4rd.107164$6w6.1499@tornado.tampabay.rr.com...
>> What is the motivation for exporting it back to XPS?  What is the nature 
>> of the data2mem errors?
>>
>> Maybe I had a similar but different problem that you have.  I had code 
>> located in external flash. I modified the bmm file and added some stuff 
>> similar to Xilinx answer record 16577. I added the modified bmm file to 
>> the ISE project, but did NOT include the elf file.  I let the tool crank 
>> out a bit file, then I manually invoked data2bram using the tag option, 
>> which IIRC indicates to data2ram, which block to load up. If I did not do 
>> this, it would try to load up the external reference and "error out".
>>
>> -Newman
>>
>> --------------------------------------------------------------------------------------
>> "Matthew Plante" <maplante@iol.unh.edu> wrote in message 
>> news:coih22$k99$1@tabloid.unh.edu...
>>> Hi folks,
>>>
>>>  I'm working on developing an embedded system with a xilinx v2pro fpga. 
>>> I have all my code for the ppc (including 2 block rams, one on the plb 
>>> and the other on the opb) done in xps, and exported it to the project 
>>> navigator.  I am trying to add an additional block rom, but I don't want 
>>> to add it in the EDK, I just want it to communicate directly with fpga 
>>> fabric.  So, I used the core generator, and created a bram instance that 
>>> is 70 bits wide, and 8k deep.  The core generator doesn't create a .bmm 
>>> or .mem file to accompany this.  So how do I go about adding the proper 
>>> lines to the current bmm file? I haven't found much for documentation on 
>>> this. If I don't add any information for the new ram to the bmm file 
>>> created by xps, then when I import the projnav files back into xps, and 
>>> regenerate the bitstream, data2mem errors out on me.
>>>  Currently, my bmm file looks like this:
>>> ADDRESS_BLOCK plb_bram_if_cntlr_1_bram RAMB16 [0xffffc000:0xffffffff]
>>> BUS_BLOCK
>>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_0 
>>> [63:56] ;
>>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_1 
>>> [55:48] ;
>>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_2 
>>> [47:40] ;
>>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_3 
>>> [39:32] ;
>>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_4 
>>> [31:24] ;
>>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_5 
>>> [23:16] ;
>>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_6 
>>> [15:8] ;
>>> top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_7 
>>> [7:0] ;
>>> END_BUS_BLOCK;
>>> END_ADDRESS_BLOCK;
>>> ADDRESS_BLOCK opb_bram_if_cntlr_1_bram RAMB16 [0x00000000:0x00003fff]
>>> BUS_BLOCK
>>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0 
>>> [31:28] ;
>>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_1 
>>> [27:24] ;
>>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_2 
>>> [23:20] ;
>>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_3 
>>> [19:16] ;
>>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_4 
>>> [15:12] ;
>>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_5 
>>> [11:8] ;
>>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_6 
>>> [7:4] ;
>>> top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_7 
>>> [3:0] ;
>>> END_BUS_BLOCK;
>>> END_ADDRESS_BLOCK;
>>>
>>> I'm not entirely sure how the rom needs to get assigned in the fpga.  I 
>>> was thinking of adding a line such as:
>>> ADDRESS BLOCK pattern_rom RAMB16 [0x00040000:0x00042000]
>>> END_ADDRESS_BLOCK;
>>> (where "pattern_rom" is my rom I added in the fpga from the coregen)
>>> But, I'm not sure how to complete the BUS_BLOCK section.
>>>
>>> Any help would be appreciated!
>>>
>>> Thanks,
>>>
>>> -- Matt
>>> maplante@iol.unh.edu
>>>
>>
>>
>
> 



Article: 76395
Subject: Re: Xilinx Virtex 4 question
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 01 Dec 2004 12:24:16 -0500
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> 
> Tom,
> 
> There is a SDR project that uses partial reconfiguration to load the
> differing modulation/demodulation formats.  They use a form of file
> system to represent the FPGA (I have seen it, it is realy neat -- you
> can look at the FPGA using a browser, and it looks like a file system).
> 
> Connections to and from the reloadable modules are simply hard loc'd
> interconnect paths (each modem uses the same inputs and outputs).

Do you have any idea of where the Spartan 3 fits into the plans for
partial reconfiguration?  Is it seriously being developed or is it still
very back burner?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 76396
Subject: Re: Xilinx Virtex 4 question
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 01 Dec 2004 09:24:34 -0800
Links: << >>  << T >>  << A >>
Rick,

TBUFs are not required for partial reconfiguration.  That was just one 
approach.  We do not have real TBUFs anyway (they were really gates 
fooling everyone into thinking they are tristate busses).

As far as the tools supporting it, you are correct:  the tools do not 
support it.

However, using the tools, and hand placements, one can do it (although 
painfully) using any interconnect you like with great care (and time).

The key to this is a set of new tools that allow for replaceable modular 
design, and fixed communication pipes to be built.

Austin

Article: 76397
Subject: Re: Xilinx Virtex 4 question
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 01 Dec 2004 09:40:16 -0800
Links: << >>  << T >>  << A >>
Rick,

Frankly, the Spartan team is not all that concerned about the (partial) 
reconfiguration feature.  I understand your situation, and I can 
sympathize, but the "low cost" FPGA is diverging from the "high feature" 
FPGA.

We see more and more decisions being made that begin to seriously 
differentiate the two product lines.

Spartan 3 may be the last part that looks in large part very similar to 
a 'Virtex' part.

Is this good?  Well, all I can say is that they seem to be selling a 
hell of a lot of parts (some joke that the 'Spartan products group' is 
now the second largest FPGA vendor - by number of parts shipped - in the 
world!).

I would ask your contact at the factory about their plans in their new 
family.  They may decide to support it, or not.

Austin



rickman wrote:
> Austin Lesea wrote:
> 
>>Tom,
>>
>>There is a SDR project that uses partial reconfiguration to load the
>>differing modulation/demodulation formats.  They use a form of file
>>system to represent the FPGA (I have seen it, it is realy neat -- you
>>can look at the FPGA using a browser, and it looks like a file system).
>>
>>Connections to and from the reloadable modules are simply hard loc'd
>>interconnect paths (each modem uses the same inputs and outputs).
> 
> 
> Do you have any idea of where the Spartan 3 fits into the plans for
> partial reconfiguration?  Is it seriously being developed or is it still
> very back burner?  
> 

Article: 76398
Subject: Re: Compact Flash Peripheral Design with FPGA
From: "Amontec, Larry" <laurent.gauch@amon-tec.com>
Date: Wed, 01 Dec 2004 19:01:52 +0100
Links: << >>  << T >>  << A >>
Johnson wrote:
> Hello,
> 
> I am currently involved in designing a Compact Flash Peripheral --- a
> GPS Receiver for TDS Recon or PocketPC. The power consumption is very
> critical. Does anybody know any xilinx parts have requirements close
> to or less than 100mA?
> 
> Could anybody please let me know the advantages to use FPGA for the CF
> peripheral, other than a DSP or ASIC? You know the price is quite
> different.
> 
> Is it important for the CF GPS Receiver to support all three modes of
> CF (Memory, I/O, and True IDE)? If we want to support all 3 modes,
> which one is a better choice for the project, FPGA or DSP?
> 
> Could anybody please 
> 
> Thank you very much in advance.
> 
> Johnson

Hi Johson,

For your work, FPGA and CPLD devices are not the good choice : very 
expensive and very bad for critical consumption applications.

You have to work with a low power cpu like a simple PIC or an AVR (8 to 
16 bits).

We have done an datalogger application using a CF and a PIC cpu. This 
application emulate Memory read/write access from/to the CF via the IO 
ports of the PIC. Also, we have a file system in the PIC cpu able to 
read and to write and manage different files in the CF.

Also, you will be able to emulate TRUE IDE from the PIC IO port if it is 
needed.

The choice of the cpu will be depending about the rest of the design.

Actually, we are starting a new datalogger using a Philips ARM 7 PLC2106 
(32 bit cpu) + CF + many AD/DA. In this new project, a 32 bit cpu is 
important because we need to process many external inputs/outputs. 
(also, we are thinking to use an CPLD for accelerating some processing JOB)

For a GPS receiver application, a 8bit or 16 bit cpu will be enough -> 
low cost and low power.

NOTE: we done last year an application with GPS Receiver. Also, we may 
design your application very quickly merging our know-how from our two 
precednet projects : CF file system + GPS receiver.

Best regards,
Laurent Gauch
www.amontec.com

Article: 76399
Subject: Re: clocks switch
From: "vax, 9000" <vax9000@gmail.com>
Date: Wed, 01 Dec 2004 13:25:52 -0500
Links: << >>  << T >>  << A >>
Matthew Plante wrote:

> Hi Dan,
> 
>   You can use an assignment statement to create a  input mux to switch
>   your
> clocks.  Something like this should do the trick:
> 
> module mux3 (clk1, clk2, clk3, select, clkout);
> 
> input clk1, clk2, clk3;
> input [1:0]select;
> output clkout;
> 
> wire clkout;
> 
> assign clkout = select == 2'b00 ? clk1 : select == 2'b01 ? clk2 : clk3; //
> 10 or 11 would select clk3
> 
> endmodule
> 
> Then all you need to do is to make a counter that's based on the selected
> clkout to change your switch signal.
> 
> Just something like   always @(posedge clkout)  counter <= counter + 1'b1;
You might need to consider whether those three clocks are synchronized to on
another. If so, your scheme works. Otherwise, you might need to watch out
for possible spikes when you switch from one clock to another. You need
some circuit to surpress those possible spikes.

vax, 9000
> 
> -- Matt
> 
> "Dan" <dan.costin@gmail.com> wrote in message
> news:f4e089e0.0412010149.4168b173@posting.google.com...
>>A have 3 clocks(clk1, clk2, clk3) and I need to make a switch between
>> these 3 clocks. My output master clock is CLK. I have a  parameter,
>> let's say 1000.
>> I need  to make first 200 pulses of CLK with clk1, then 600 pulses of
>> CLK with clk2, then last 200 pulses of CLK with clk3. How can I
>> implement this in verilog??
>>
>>
>>  Thanks,




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