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salman sheikh wrote: > > Muthu wrote: > > Hi, > > How to be part of NASA as a VLSI Design engineer? > > > > Regards, > > Muthu > You must be a US citizen first. Are you sure of that? I know of non-US citizens that have worked at NASA, but that was before 9-11, so it may have changed. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76176
emrah wrote: > > Ben Twijnstra <btwijnstra@gmail.com> wrote in message news:<nZMod.8063$_u6.2552@amsnews02.chello.com>... > > > > If you are able to select the signal before compilation, either in the block > > diagram editor or in the node finder, you can tell Quartus to "Implement as > > output of Logic Cell" by using the Assignment Editor. > > > > This will make sure that the signal is always present in the design (unless > > it's unnecessary and optimized away). > > > > If you use VHDL or Verilog, look at the "keep" synthesis attribute, which > > does the same thing, but from your source code instead of from the > > Assignment Editor. > > > > Good luck with these clues. > > > > Best regards, > > > > > > > > Ben > > Hi Ben, > Thanks for your clues, but the signal I need is optimized away. Let me > explain my problem in detail: We have a memory in our design and the > inputs of this memory are optimized away. And my job is to get the > exact delay of the memory! What do you mean the inputs to the memory are optimized away? I don't know of any inputs to a memory that can be "optimized" away unless the memory is "optimized" away because the output is not driving anything. The most common reason that a signal is not visible in simulation or net list is because the signal is between gates that are in the same LUT after synthesis. The inputs to a memory can not be combined into a LUT so that they no longer appear in your design. So they only way they can be removed is if the driver or receiver of the signal is no longer in the design. If you have an error in your design that results in a driver having no receiver or a receiver being driven by no driver, the tool will optimize that signal away. If this makes the part unusable, it will be removed as well. This can in turn create other signals that have no driver or receiver and they are removed as well... you get the idea. So you need to find the net that is connected to your RAM and find out if it really is connected or not. You can find all the signals in your synthesized design by looking either at the equations or by bringing up one of the chip viewing tools. The one I use is the timing closure tool, since I am normally trying to improve timing. If you select any component and click the input net and/or output net buttons, it will show you the crow's path route. By viewing the equations window you can see the signal names on the component. If you want timing info, click on the icon for viewing timing info on the routes. This will not include the component delays, however. I normally use the timing analyzer for that. If you want timing info, you can bring up the tool and select specific components. It can give you info on clock to clock, clock to output, input to clock or input to output. I'm not sure exactly what delays you want to find, but this tool should be able to give it to you. Once you have identified a path with your route of interest, you can list it with all the detail you need to examine any part of it. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76177
darkgold@lycos.co.uk (Kotek Barajazz) wrote in message news:<8196a0da.0411270742.21b443d2@posting.google.com>... > Hi I was wondering if anyone here can help me. > > I need to infer a true dual port BRAM with seperate clk, addr, data, > en and wr lines on a Spartan-3 device but according to the XST manual > this is not supported and after googling for a couple of days I've > come to a dead end. XST can't infer it but you can instatiate the primitives instead. have a look at: http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0372_356.html -LasseArticle: 76178
"Paul Leventis (at home)" wrote: > > The Quartus II Web Edition is almost fully-featured when it comes to > push-button place & route. Web Edition provides all synthesis & fitter > options intended for optimizing design performance and/or area, with the > exception of the physical synthesis options. Physical synthesis can be a > huge boost on many designs (10-15%?), so its ommision is a bit of a downside > to using the Web Edition. It may be included in a future edition of the > product. Is physical synthesis supported for the ACEX 1K devices? I don't know if it will improve the logic synthesis since I have done a lot of hand optimization using specific 4 input equations and "keep" attributes to control the mapping to LUTs. But I find the routing is not very optimal (likely from poor placement) and I expect it could shave some 10% off my worst case paths (~20 nS) if that could be dealt with. Is physical synthesis available for the 1K50 part and will this help my design? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76179
Mike Treseler wrote: > > Kotek Barajazz wrote: > > > I need to infer a true dual port BRAM with seperate clk, addr, data, > > en and wr lines on a Spartan-3 device but according to the XST manual > > this is not supported and after googling for a couple of days I've > > come to a dead end. > > > > I need this in order to provide an external memory interface to some > > shared memory and the design is so simple and clean at the moment that > > I really want avoid having to use an async FIFO which would need alot > > of re-jigging to the upper levels and make things quite ugly. > > A fifo-like controller requires one read-only port > and one write-only port. Such a two port description > infers the "true dual port BRAM" just fine, > but with the extra read and write controls tied off. > As an added benefit, the description is portable > across vendors. Related posting: > > http://groups.google.com/groups?q=infer+RAM_B4_S16_S16 But this description only works if you have a common clock. The OP has asked for separate read/write clocks. I have never seen an example of inferrence of a dual port RAM with separate clocks. I can write a VHDL description of one by using a shared variable for the RAM. But I have not found a synthesizer that supports shared variables. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76180
Hello,
I am somewhat new to vhdl, xilinx, etc. The board I am working with
is the Spartan 2s50-pq208-6. I have created my design in VHDL and
went to assign the pins. I have a signal "reset" that I need to drive
off of one of the boards switches.
The problem is that XILINX has determined that the "reset" signal is a
global clock signal and can only use of the the 4 global clock signals
on the board.
How do I prevent this from happening.
I am using Xilinx Free Webpack 6.3.
Since I am new to all of this, I am not sure what to post. Here is my
code:
entity prj2v3 is
--d comes from MC
--p comes from peri
port(ceAL, a0, rdAL, wrAL, reset, stbAL: in STD_LOGIC; ibf, intr,
bufctrl, here: out STD_LOGIC;
d: inout STD_LOGIC_VECTOR(7 downto 0):=(others=>'Z'); p: in
STD_LOGIC_VECTOR(7 downto 0));
--attribute syn_noclockbuf of reset : signal is true;
end prj2v3;
architecture Behavioral of prj2v3 is
signal ctr: std_logic_vector(0 to 1):="00"; --ctr.0=MODE ctr.1==INTE
signal str: std_logic_vector(0 to 2):="000"; ---str.0==IBF
str.1==INTE str.2==INTR
signal data: std_logic_vector(7 downto 0):="00000000";
--signal here: std_logic:='0';
--signal here2: std_logic:='0';
begin
ctr(0)<=d(0) when(a0='1' and reset='0' and ceAL='0' and wrAL='0' and
rdAL='1') else '0' when reset='1';
ctr(1)<=d(1) when(a0='1' and reset='0' and ceAL='0' and wrAL='0' and
rdAL='1') else '0' when reset='1';
str(1) <=ctr(1);
str(0)<='1' when(ctr(0)='1' and reset='0' and stbAL='0') else '0' when
((a0='0' and ceAL='0' and reset='0' and rdAL='0' and wrAL='1' and
ctr(0)='1') or reset='1') else str(0);
str(2)<='1' when(ctr(0)='1' and reset='0' and stbAL='0' and
ctr(1)='1') else '0' when ((a0='0' and ceAL='0' and reset='0' and
rdAL='0' and wrAL='1' and ctr(0)='1') or reset='1') else str(2);
bufctrl<='0' when(ceAL='0' and a0='1' and reset='0' and wrAL='0' and
rdAL='1') else '1';
ibf<=str(0) when reset='0' else '0';
intr<=str(2) when (str(1)='1'and reset='0') else '0';
data<=p when (reset='0' and stbAL='0' and rdAL='1' and ctr(0)='1')
else data;
d<= p when(ctr(0)='0' and reset='0' and a0='0' and ceAL='0' and
rdAL='0' and wrAL='1') else
data when(ctr(0)='1' and reset='0' and a0='0' and ceAL='0' and
rdAL='0' and wrAL='1') else
"ZZZZZ" & str when(ceAL='0' and a0='1' and reset='0' and wrAL='1'
and rdAL='0') else
"00000000" when reset='1' else
"ZZZZZZZZ";
Aaron
Article: 76181The presence of the CPU in my project seems to prevent DONE going high. Nothing else in or connected to JTAG chain. CPU is 7 mA and under 2 MHz, so nothing exotic. Are flapping I/O pins likely to be disruptive? Or do RAM-based FPGA chips still draw big ICC during programming? XP / Xilinx ISE 6.2.03i bug perhaps?Article: 76182
The next version of the Quartus II Web Edition will support physical synthesis for the Stratix, Cyclone, Stratix II, Cyclone II and Max II families. Hope this helps. - Subroto Datta Altera Corp. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:41A8F514.E2E1C1BA@yahoo.com... > "Paul Leventis (at home)" wrote: >> >> The Quartus II Web Edition is almost fully-featured when it comes to >> push-button place & route. Web Edition provides all synthesis & fitter >> options intended for optimizing design performance and/or area, with the >> exception of the physical synthesis options. Physical synthesis can be a >> huge boost on many designs (10-15%?), so its ommision is a bit of a >> downside >> to using the Web Edition. It may be included in a future edition of the >> product. > > Is physical synthesis supported for the ACEX 1K devices? I don't know > if it will improve the logic synthesis since I have done a lot of hand > optimization using specific 4 input equations and "keep" attributes to > control the mapping to LUTs. But I find the routing is not very optimal > (likely from poor placement) and I expect it could shave some 10% off my > worst case paths (~20 nS) if that could be dealt with. > > Is physical synthesis available for the 1K50 part and will this help my > design? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76183
rickman wrote:
> But this description only works if you have a common clock. The OP has
> asked for separate read/write clocks.
>
> I have never seen an example of inferrence of a dual port RAM with
> separate clocks.
Try this one.
-- Mike Treseler
--_________________________________
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dual_port_ram is
generic (
WIDTH : integer := 32;
DEPTH : integer := 10
);
port (
w_clk : in std_logic;
w_en_in : in std_logic;
w_addr_in : in std_logic_vector(DEPTH-1 downto 0);
w_data_in : in std_logic_vector(WIDTH-1 downto 0);
r_clk : in std_logic;
r_addr_in : in std_logic_vector(DEPTH-1 downto 0);
r_data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end entity;
architecture xilinx of dual_port_ram is
type memory_type is array (natural range <>) of
std_logic_vector(WIDTH-1 downto 0);
signal memory : memory_type(2**DEPTH-1 downto 0);
signal r_addr_int : std_logic_vector(DEPTH-1 downto 0);
begin
write : process(w_clk)
begin
if w_clk'event and w_clk = '1' then
if w_en_in = '1' then
memory(to_integer(unsigned(w_addr_in))) <= w_data_in;
end if;
end if;
end process;
read : process(r_clk)
begin
if r_clk'event and r_clk = '1' then
r_addr_int <= r_addr_in;
end if;
end process;
r_data_out <= memory(to_integer(unsigned(r_addr_int)));
end architecture;
Article: 76184
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<30rir5F31r7kkU1@uni-berlin.de>...
> Hello everybody,
>
> Iam using ISE 6.2 with XST as synthesis tool. So far so good. But Now I have
> a design with plenty of timing margin (just 36 MHz ;-) and the goal is to
> fit it into a XC2S50E.
> At the end, it doesnt.
> So looking a little closer to the reports, I saw in the MAP report something
> like this.
>
> blabla
> 1000 LUTs used
> 300 LUTs used a s route-thru.
>
> How is this to understand? I understand it this way, that XST (and the other
> tools) use a LUT to feed data into a FF, but only 1 input is used, so the
> LUT has no real function, maybe only a inversion. Is this how it works?
> So how can I tell the software not to use LUTs as route thru, even if this
> will decrease timing performance? I mean it is tecnically possible to use th
> BY input to feed data into a FF.
>
> Regards
> Falk
Not sure if this will help, but might be worth a try out the following
MAP options -
map -cm area
or
map -k {4 5 6} (default is 4)
or
both of them together.
Article: 76185"Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote in message news:Gx8qd.3023$FT3.1627@newsfe2-gui.ntli.net... > The presence of the CPU in my project seems to prevent DONE going high. > > Nothing else in or connected to JTAG chain. > > CPU is 7 mA and under 2 MHz, so nothing exotic. > > Are flapping I/O pins likely to be disruptive? > > Or do RAM-based FPGA chips still draw big ICC during programming? > > XP / Xilinx ISE 6.2.03i bug perhaps? > there is only one catch: JTAG is accessible and you can do boundary scan, etc when PROG is low, but programming over JTAG will fail. PROG needs a pullup in order to allow DONE go high anttiArticle: 76186
Mike Treseler wrote: > > rickman wrote: > > > But this description only works if you have a common clock. The OP has > > asked for separate read/write clocks. > > > > I have never seen an example of inferrence of a dual port RAM with > > separate clocks. > > Try this one. > -- Mike Treseler > --_________________________________ > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.numeric_std.all; > > entity dual_port_ram is > generic ( > WIDTH : integer := 32; > DEPTH : integer := 10 > ); > port ( > w_clk : in std_logic; > w_en_in : in std_logic; > w_addr_in : in std_logic_vector(DEPTH-1 downto 0); > w_data_in : in std_logic_vector(WIDTH-1 downto 0); > > r_clk : in std_logic; > r_addr_in : in std_logic_vector(DEPTH-1 downto 0); > r_data_out : out std_logic_vector(WIDTH-1 downto 0) > ); > end entity; > > architecture xilinx of dual_port_ram is > > type memory_type is array (natural range <>) of > std_logic_vector(WIDTH-1 downto 0); > signal memory : memory_type(2**DEPTH-1 downto 0); > > signal r_addr_int : std_logic_vector(DEPTH-1 downto 0); > > begin > > write : process(w_clk) > begin > if w_clk'event and w_clk = '1' then > if w_en_in = '1' then > memory(to_integer(unsigned(w_addr_in))) <= w_data_in; > end if; > end if; > end process; > > read : process(r_clk) > begin > if r_clk'event and r_clk = '1' then > r_addr_int <= r_addr_in; > end if; > end process; > > r_data_out <= memory(to_integer(unsigned(r_addr_int))); > > end architecture; Ok, this is dual port, but I meant one that was fully dual port with write on both ports. The Xilinx dual port rams in the Virtex and later parts (IIRC, the Spartan3 for sure) have both read and write on each port. Being able to write to a common RAM from two processes is not supported in VHDL as far as I am aware. Using a shared variable seems to work in simulation, but is not synthesizable. Please correct me (further) if I am mistaken. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76187
> Not sure if this will help, but might be worth a try out the following
> MAP options -
>
> map -cm area
> or
> map -k {4 5 6} (default is 4)
> or
> both of them together.
I tried it before, doesnt change a bit. The number of route-thru LUTs stays.
Regards
Falk
Article: 76188"Aaron" <af@poorstudents.us> schrieb im Newsbeitrag news:a6e2e737.0411271423.74fc6af6@posting.google.com... > went to assign the pins. I have a signal "reset" that I need to drive > off of one of the boards switches. > > The problem is that XILINX has determined that the "reset" signal is a > global clock signal and can only use of the the 4 global clock signals > on the board. Hmm, you are using reset to latch data, so reset is a clock. Clock should be feed into the FPGA using the dedicated clock buffer pins (GCLK). But there are always other ways. If you want to use a normal IO, use the following lines. -- this is to be placed between architecture Behavioral of prj2v3 is component ibuf port is (I : in std_logic; O: out std_logic) end component; -- and begin label_ibuf: ibuf port map(I : reset, O: reset_int); this will do the trick. Now use reset_int for your logic. But be aware that distributing a clock on non-clock nets can play you nasty tricks. Regards FalkArticle: 76189
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:41A98900.4AF5BDDA@yahoo.com... > Ok, this is dual port, but I meant one that was fully dual port with > write on both ports. The Xilinx dual port rams in the Virtex and later > parts (IIRC, the Spartan3 for sure) have both read and write on each > port. Being able to write to a common RAM from two processes is not > supported in VHDL as far as I am aware. Using a shared variable seems > to work in simulation, but is not synthesizable. At the end, I prefer to instanciate such tings anyway. Much easier, predictable, portable. Why bother with semi-intelligent synthesis tools? Regards FalkArticle: 76190
"Hal Murray" <hmurray@suespammers.org> wrote in message
news:W6idnWZS49YksjXcRVn-jg@megapath.net...
> >So my advice to someone is write your code using no built in libraries..
> >then compile using free tools on both... look at the speeds, delays
etc...
> >is it what you want ? is it everything you need ? Do both manufacturers
> >work ?
>
> Anybody have a rule-of-thumb on how much performance you give up if
> you don't tweak your code to take advantage of a vendor's
> features/quirks? (both software and hardware)
I've never seen a performance difference... but we use synplify. There is a
unit size penalty... the hard coded routines have better optimisation. but
thats not important... Follow the software rule. Don't use machine code
until you have too. theres no point unless your running against the wire or
its a specific routine but thats what subroutines are for... even hardware
can have a 'hardware' ('vendor') abstraction layer.
> Are the free tools appropriate if we are discussing volumes big enough
> to be worth arguing about?
>
Free tools are just a place to start.. if you are considering big volume
then you will have simplify, mentor or something similar... in which case it
is the same code for both.
Article: 76191basically.. yes... The LUT as a router is the same as a via on a PCB. annoying to have.. but imposable to live without How to fit the design... first... try the optimisations others suggest... second.. check with marketing ... it may not be worth the effort when it would fit comfortably in a 100e third.. use a better tool ($$$) forth... use as many built in routines as you can find. fifth.. hand place and route the design (see second above) sixth.. your 30% over budget so throw it away and start again with a better algorithm... or see second above. seventh... just throw functionality out until it fits eighth.. ask your Xilinx reseller to give you a better price on 100e Simon "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:30rir5F31r7kkU1@uni-berlin.de... > Hello everybody, > > Iam using ISE 6.2 with XST as synthesis tool. So far so good. But Now I have > a design with plenty of timing margin (just 36 MHz ;-) and the goal is to > fit it into a XC2S50E. > At the end, it doesnt. > So looking a little closer to the reports, I saw in the MAP report something > like this. > > blabla > 1000 LUTs used > 300 LUTs used a s route-thru. > > How is this to understand? I understand it this way, that XST (and the other > tools) use a LUT to feed data into a FF, but only 1 input is used, so the > LUT has no real function, maybe only a inversion. Is this how it works? > So how can I tell the software not to use LUTs as route thru, even if this > will decrease timing performance? I mean it is tecnically possible to use th > BY input to feed data into a FF. > > Regards > Falk > > >Article: 76192
Austin Obviously if one vendor has an overriding advantage for a particular application then they'll be used -- so is somebody really needs an FPGA with 10Gb/s I/O now or in the near future they've got a choice of Brand X or Brand X...:-) But if they're already using Brand A and it suits them and their engineers are familiar with the tools and so on, I don't want to have to tell them to switch. If being the best always won we'd now be dumping Betamax video recorders for DVD rather than VHS, I'd probably be writing this on a Mac not a PC, and Bill Gates would be flipping burgers. If only... Ian austin wrote: > Ian, > > Most customers are not stupid: if they see their competition using > Xilinx, and beating them, they are unlikely to remain so fixated on a > particular vendor. > > I understand that there are Altera customers who are so committed, that > they will not consider any other solution. > > The oppsoite is true, as well. > > I don't think we need to discuss it here. More intersting are folks who > want the best features, performance, support, software, cores, and > tools. And are willing to examine all vendors. > > Those are the ones I want to reach. > > By the way, there are customers who believe that in order to keep both > vendors alive, they have to intentionally switch every so often. > > AustinArticle: 76193
rickman wrote:
> Ok, this is dual port, but I meant one that was fully dual port with
> write on both ports.
My point was that a pseudo dual port is all you
need for a fifo and that a fifo-based controller
would solve the OP's problem.
"A fifo-like controller requires one read-only port
and one write-only port. Such a two port description
infers the "true dual port BRAM" just fine,
but with the extra read and write controls tied off.
As an added benefit, the description is portable
across vendors. "
> The Xilinx dual port rams in the Virtex and later
> parts (IIRC, the Spartan3 for sure) have both read and write on each
> port.
I realize that. Reread the above.
> Being able to write to a common RAM from two processes is not
> supported in VHDL as far as I am aware. Using a shared variable seems
> to work in simulation, but is not synthesizable.
>
> Please correct me (further) if I am mistaken.
You are mistaken. I tested the two-clock version
on Leonardo for Xilinx and on modelsim Maybe you could try it
on XST and post the result.
My examples do not use a shared variable, nor did I recommend one.
-- Mike Treseler
Article: 76194
Falk Brunner wrote:
> At the end, I prefer to instanciate such tings anyway. Much easier,
> predictable, portable.
> Why bother with semi-intelligent synthesis tools?
Sorry to waste your time.
I suppose vhdl synthesis is a little off-topic for this group.
-- Mike Treseler
Article: 76195
Simon Peacock wrote:
> I've never seen a performance difference... but we use synplify.
I agree. I use mentor leonardo and quartus.
> Free tools are just a place to start.. if you are considering big volume
> then you will have simplify, mentor or something similar... in which case it
> is the same code for both.
I run a test synthesis on all brand A code with quartus.
It works quite well in recent releases.
However simplify or mentor tools make it easier to
choose devices or verify code as portable.
-- Mike Treseler
Article: 76196Mike Treseler wrote: > > rickman wrote: > > > Being able to write to a common RAM from two processes is not > > supported in VHDL as far as I am aware. Using a shared variable seems > > to work in simulation, but is not synthesizable. > > > > Please correct me (further) if I am mistaken. > > You are mistaken. I tested the two-clock version > on Leonardo for Xilinx and on modelsim Maybe you could try it > on XST and post the result. > > My examples do not use a shared variable, nor did I recommend one. But your examples do not write to the ram from both clock domains. I understand that you are referring to block ram used as a fifo, but my comments were intended for a fully dual port block ram with write capability on both ports. Assigning a value to the RAM from two processes is where the problem lies, but maybe I am mistaken. Please show me a working example that has two write ports. I have a design I would like to use it in. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76197
1076.6-2004 permits the following coding style
(hacking from Mike's previous code).
ram_access : process (clk1, clk2)
begin
if rising_edge(clk1) then
if we1 = '1' then
mem(to_integer(wr_tail_ptr1)) <= data_i; -- raw address
end if;
data_q <= mem(to_integer(rd_head_ptr1)); -- mem data after pop low
end if;
if rising_edge(clk2) then
if we2 = '1' then
mem(to_integer(wr_tail_ptr2)) <= data_i; -- raw address
end if;
data_q <= mem(to_integer(rd_head_ptr2)); -- mem data after pop low
end if;
end process ram_access;
I am not sure if any eda vendors are supporting
this or not yet. If this matches what you are
looking for, make sure to let your vendor know that
you need this supported in the near future.
The path to supporting future coding styles is always
based on demand.
Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Mike Treseler wrote:
>
>>rickman wrote:
>>
>>
>>>But this description only works if you have a common clock. The OP has
>>>asked for separate read/write clocks.
>>>
>>>I have never seen an example of inferrence of a dual port RAM with
>>>separate clocks.
>>
>>Try this one.
>> -- Mike Treseler
>>--_________________________________
>>
>>library IEEE;
>>use IEEE.std_logic_1164.all;
>>use IEEE.numeric_std.all;
>>
>>entity dual_port_ram is
>> generic (
>> WIDTH : integer := 32;
>> DEPTH : integer := 10
>> );
>> port (
>> w_clk : in std_logic;
>> w_en_in : in std_logic;
>> w_addr_in : in std_logic_vector(DEPTH-1 downto 0);
>> w_data_in : in std_logic_vector(WIDTH-1 downto 0);
>>
>> r_clk : in std_logic;
>> r_addr_in : in std_logic_vector(DEPTH-1 downto 0);
>> r_data_out : out std_logic_vector(WIDTH-1 downto 0)
>> );
>>end entity;
>>
>>architecture xilinx of dual_port_ram is
>>
>> type memory_type is array (natural range <>) of
>> std_logic_vector(WIDTH-1 downto 0);
>> signal memory : memory_type(2**DEPTH-1 downto 0);
>>
>> signal r_addr_int : std_logic_vector(DEPTH-1 downto 0);
>>
>>begin
>>
>> write : process(w_clk)
>> begin
>> if w_clk'event and w_clk = '1' then
>> if w_en_in = '1' then
>> memory(to_integer(unsigned(w_addr_in))) <= w_data_in;
>> end if;
>> end if;
>> end process;
>>
>> read : process(r_clk)
>> begin
>> if r_clk'event and r_clk = '1' then
>> r_addr_int <= r_addr_in;
>> end if;
>> end process;
>>
>> r_data_out <= memory(to_integer(unsigned(r_addr_int)));
>>
>>end architecture;
>
>
> Ok, this is dual port, but I meant one that was fully dual port with
> write on both ports. The Xilinx dual port rams in the Virtex and later
> parts (IIRC, the Spartan3 for sure) have both read and write on each
> port. Being able to write to a common RAM from two processes is not
> supported in VHDL as far as I am aware. Using a shared variable seems
> to work in simulation, but is not synthesizable.
>
> Please correct me (further) if I am mistaken.
>
Article: 76198Falk Brunner wrote: > > Hello everybody, > > Iam using ISE 6.2 with XST as synthesis tool. So far so good. But Now I have > a design with plenty of timing margin (just 36 MHz ;-) and the goal is to > fit it into a XC2S50E. > At the end, it doesnt. > So looking a little closer to the reports, I saw in the MAP report something > like this. > > blabla > 1000 LUTs used > 300 LUTs used a s route-thru. > > How is this to understand? I understand it this way, that XST (and the other > tools) use a LUT to feed data into a FF, but only 1 input is used, so the > LUT has no real function, maybe only a inversion. Is this how it works? > So how can I tell the software not to use LUTs as route thru, even if this > will decrease timing performance? I mean it is tecnically possible to use th > BY input to feed data into a FF. Are you sure this is the output from MAP? My understanding is that it is the routing tool that will add route-thru LUTs, not the mapper. There would be no point to the mapper adding them since it would have no idea of where routing is a problem. I am thinking that perhaps your synthesis tool is adding them because of some mistaken option. Or maybe your design won't fit anyway!!! I just checked and the XC2S50 only has 864 LUTs ignoring the data sheet that says 972. Does your design require 1000 *plus* 300 for routing or just 700? If it is the router that is adding the routing LUTs, then your design just won't route in the XC2S50 unless you perhaps try floorplanning the design to ease routing congestion. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76199
Falk Brunner wrote: > > "rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > news:41A98900.4AF5BDDA@yahoo.com... > > > Ok, this is dual port, but I meant one that was fully dual port with > > write on both ports. The Xilinx dual port rams in the Virtex and later > > parts (IIRC, the Spartan3 for sure) have both read and write on each > > port. Being able to write to a common RAM from two processes is not > > supported in VHDL as far as I am aware. Using a shared variable seems > > to work in simulation, but is not synthesizable. > > At the end, I prefer to instanciate such tings anyway. Much easier, > predictable, portable. > Why bother with semi-intelligent synthesis tools? I am not sure I understand. Instantiation is not portable at all... The reason that I prefer to infer logic is to increase portability. I try to use block rams in ways that will work across vendors. So if I can infer them, I don't need multiple source files for different vendors. Or when I need modes that are not compatible I use GENERATE statements to select a vendor specific version, still inferred if possible. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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