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Hi,
I have the following problem when using the Altera SignalTapII
Embedded Logic Analyzer:
When compiling my design which includes a PLL generating a 48MHz and a
90 MHz clock
out of a 30MHz clock
there is everything fine.
When including the stp-file and then compiling the design again I get
the warning:
# Critical warning: Timing requirements were not met. See Report
window for details.
I thought that the SignalTapII would not influence the timing but it
does. Why?
What can I do about that?
The timing report shows the following critical path:
Clock Setup: 'pll1:PLL1_1|altpll:altpll_component|_clk1' -0.008
ns 90.00 MHz ( period = 11.111 ns
) N/A reg_help:REG_HELP_1|lpm_counter:l_little_count_rtl_1|cntr_ia7:
auto_generated|safe_q[6]
sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[7]
pll1:PLL1_1|altpll:altpll_component|_clk0
pll1:PLL1_1|altpll:altpll_component|_clk1 2
I would appreciate your help.
Thank you in advance.
Rgds
Article: 72926Hi, When I use windpower ICE to debug my application on v2p4fg456 ,it asks for some reg and board files.What kind of information do I need to give here.I have instantiated powerpc in the design.Anybody worked on it earlier ?? Appreciate a detailed reply asap. Regards, NavyaArticle: 72927
Patrick Harold wrote: > Dear George, > > I would like to thank you for your understanding. > Unfortunatelly I'm not student. (I'm too old to be a student.. When I was > student, I was working with tubes (not even with transistors) ). > It is not so easy in my age to keep track with the all this new > technologies. I'm trying my best to follow the technology. I recently > started to study the VHDL. I'm almost on the "page one" of the VHDL study > and want to learn by implementing simple little projects. > Thank you once again for your understanding. > Regards. Sorry Patrick, I'm use to students trying to do there homework online... Search amazon (and also google) for VHDL resourses. I'd suggest you make small devices and work up (make an invertor, make a flip-flop). Doing it that way you will get use to the language and then you can focus on what you really want to build. Regards, JamieArticle: 72928
I'm trying to use the i2c-core from opencores.org.
I made a project in Altera Quartus II and added the 3 VHDL-Files.
Compiling is no problem, but I have problems with the simulation. I'm doing:
1) reseting the core
2) write clock prescaler (Addr 0 and 1)
3) enable core in control register (10000000 to Addr 2)
4) write data for writing to slave to transmit register (Addr 3)
5) start and write to command register (10010000 to Addr 4)
and nothing happens on the output-lines !!!???
Reading the status register (Addr 4) shows 'Transfer in Progress' every
time!
What i am doing wrong ???
Can someone help ?
Thanks, Manfred
Article: 72929Thank you Jamie. "jamie" <jamie@noway.com> wrote in message news:6UC%c.17219$lP4.1220919@news20.bellglobal.com... > Patrick Harold wrote: >> Dear George, >> >> I would like to thank you for your understanding. >> Unfortunatelly I'm not student. (I'm too old to be a student.. When I >> was student, I was working with tubes (not even with transistors) ). >> It is not so easy in my age to keep track with the all this new >> technologies. I'm trying my best to follow the technology. I recently >> started to study the VHDL. I'm almost on the "page one" of the VHDL study >> and want to learn by implementing simple little projects. >> Thank you once again for your understanding. >> Regards. > > > Sorry Patrick, I'm use to students trying to do there homework online... > > Search amazon (and also google) for VHDL resourses. I'd suggest you make > small devices and work up (make an invertor, make a flip-flop). Doing it > that way you will get use to the language and then you can focus on what > you really want to build. > > > Regards, > > JamieArticle: 72930
You seem to be using just one clock for the whole system. On the other hand you specify a 3:1 ratio between processor and OCM with the following settings: PARAMETER C_DSCNTLVALUE = 0x85 PARAMETER C_ISCNTLVALUE = 0x85 Try changing these values to 0x81. You might also want to consider to upgrade to the latest EDK version. - Peter Mancini Stephane wrote: > Hi, > I'm writing this newsgroup because i'm facing a stange problem while > simulating a ppc system for V2PRO generated with EDK 3.2. > Indeed, the PPC doesn't start correctly. > I've generated a behavioural simulation model with EDK wich I'm including > in a top level and then in a bench, all of them in VHDL. > modelsim seems to load correctly the swift model and the simulation starts > correctly. > After reset with a proc_sys_reset instance, the ppc model issues the > correct adress to the i-ocm at boot (FFFFFFFC translated to the iocm > adress). The ocm returns an opcode and the ppc stalls, the adress doesn't > change and the instruction doesn't seem to be executed. > > What kind of problem could it be ? > > Did I forget something in my system.mhs file ? > I've started from a generated one which I modified by hand. The original > had a system_dcm which I suppressed because I had trouble to simulate it. > Did I forget something ? > > Thanks a lot for your help > > Note : i'm using modelsim on a sun workstation > > > For your info, here is the system.mhs .... > # ############################################################################# > # Created by Base System Builder Wizard for Xilinx EDK 6.2 Build EDK_Gm.11 > # Modified by hand > # Target Board: Avnet Avnet Virtex-II Pro Development Board Rev 1.0 > # Family: virtex2p > # Device: XC2VP7 > # Package: FF896 > # Speed Grade: -5 > # Processor: PPC 405 > # Processor clock frequency: 100 MHz > # Bus clock frequency: 100 MHz > # Debug interface: No Debug > > > > PARAMETER VERSION = 2.1.0 > > > PORT RS232_TX = RS232_TX, DIR = O > PORT RS232_RX = RS232_RX, DIR = I > PORT SDRAM_RASn = SDRAM_RASn, DIR = O > PORT SDRAM_DQ = SDRAM_DQ, VEC = [0:31], DIR = IO > PORT SDRAM_Clk = SDRAM_Clk, DIR = O > PORT SDRAM_CSn = SDRAM_CSn, DIR = O > PORT SDRAM_CASn = SDRAM_CASn, DIR = O > PORT SDRAM_BankAddr = SDRAM_BankAddr, VEC = [0:1], DIR = O > PORT SDRAM_Addr = SDRAM_Addr, VEC = [0:11], DIR = O > PORT SDRAM_DQM = SDRAM_DQM, VEC = [0:3], DIR = O > PORT SDRAM_WEn = SDRAM_WEn, DIR = O > PORT SDRAM_CKE = SDRAM_CKE, DIR = O > PORT SRAM_A = SRAM_A, VEC = [0:31], DIR = O > PORT SRAM_DQ = SRAM_DQ, VEC = [0:31], DIR = IO > PORT SRAM_CEN = SRAM_CEN, VEC = [0:1], DIR = O > PORT SRAM_OEN = SRAM_OEN, VEC = [0:1], DIR = O > PORT SRAM_WEN = SRAM_WEN, DIR = O > PORT SRAM_QWEN = SRAM_QWEN, VEC = [0:3], DIR = O > PORT SRAM_BEN = SRAM_BEN, VEC = [0:3], DIR = O > PORT SRAM_RPN = SRAM_RPN, DIR = O > PORT SRAM_CE = SRAM_CE, VEC = [0:1], DIR = O > PORT SRAM_ADV_LDN = SRAM_ADV_LDN, DIR = O > PORT SRAM_LBON = SRAM_LBON, DIR = O > PORT SRAM_CKEN = SRAM_CKEN, DIR = O > PORT SRAM_RNW = SRAM_RNW, DIR = O > PORT sys_irq = sys_irq, VEC = [0:0], DIR = I, LEVEL=HIGH, SIGIS = INTERRUPT > PORT sys_clk = sys_clk_s, DIR = IN, SIGIS = CLK > PORT sys_rst = sys_rst_s, DIR = IN > PORT SDRAM_Clk_in = SDRAM_Clk_in, DIR = IN > > BEGIN ppc405 > PARAMETER INSTANCE = ppc405_0 > PARAMETER HW_VER = 2.00.c > BUS_INTERFACE DPLB = plb > BUS_INTERFACE IPLB = plb > BUS_INTERFACE DSOCM = docm > BUS_INTERFACE ISOCM = iocm > PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ > PORT CPMC405JTAGCLKEN = net_vcc > PORT MCPPCRST = net_vcc > PORT BRAMDSOCMCLK = sys_clk_s > PORT CPMC405CPUCLKEN = net_vcc > PORT PLBCLK = sys_clk_s > PORT EICC405EXTINPUTIRQ = opb_intc_0_irq > PORT EICC405CRITINPUTIRQ = net_gnd > PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ > PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ > PORT RSTC405RESETCHIP = RSTC405RESETCHIP > PORT CPMC405TIMERCLKEN = net_vcc > PORT RSTC405RESETCORE = RSTC405RESETCORE > PORT RSTC405RESETSYS = RSTC405RESETSYS > PORT CPMC405CORECLKINACTIVE = net_gnd > PORT CPMC405TIMERTICK = net_vcc > PORT BRAMISOCMCLK = sys_clk_s > PORT CPMC405CLOCK = sys_clk_s > END > > BEGIN proc_sys_reset > PARAMETER INSTANCE = reset_block > PARAMETER HW_VER = 1.00.a > PARAMETER C_EXT_RESET_HIGH = 0 > PORT Rstc405resetsys = RSTC405RESETSYS > PORT Rstc405resetcore = RSTC405RESETCORE > PORT Rstc405resetchip = RSTC405RESETCHIP > PORT Bus_Struct_Reset = sys_bus_reset > PORT Chip_Reset_Req = C405RSTCHIPRESETREQ > PORT System_Reset_Req = C405RSTSYSRESETREQ > PORT Ext_Reset_In = sys_rst_s > PORT Slowest_sync_clk = sys_clk_s > PORT Core_Reset_Req = C405RSTCORERESETREQ > PORT Dcm_locked = net_vcc > END > > BEGIN isocm_v10 > PARAMETER INSTANCE = iocm > PARAMETER HW_VER = 1.00.b > PARAMETER C_ISCNTLVALUE = 0x85 > PORT sys_rst = sys_bus_reset > PORT ISOCM_Clk = sys_clk_s > END > > BEGIN isbram_if_cntlr > PARAMETER INSTANCE = iocm_cntlr > PARAMETER HW_VER = 2.00.a > PARAMETER C_BASEADDR = 0xfffff000 > PARAMETER C_HIGHADDR = 0xffffffff > BUS_INTERFACE DCR_WRITE_PORT = isocm_porta > BUS_INTERFACE INSTRN_READ_PORT = isocm_portb > BUS_INTERFACE ISOCM = iocm > END > > BEGIN bram_block > PARAMETER INSTANCE = isocm_bram > PARAMETER HW_VER = 1.00.a > BUS_INTERFACE PORTA = isocm_porta > BUS_INTERFACE PORTB = isocm_portb > END > > BEGIN dsocm_v10 > PARAMETER INSTANCE = docm > PARAMETER HW_VER = 1.00.b > PARAMETER C_DSCNTLVALUE = 0x85 > PORT DSOCM_Clk = sys_clk_s > PORT sys_rst = sys_bus_reset > END > > BEGIN dsbram_if_cntlr > PARAMETER INSTANCE = docm_cntlr > PARAMETER HW_VER = 2.00.a > PARAMETER C_BASEADDR = 0xffff0000 > PARAMETER C_HIGHADDR = 0xffff1fff > BUS_INTERFACE PORTA = dsocm_porta > BUS_INTERFACE DSOCM = docm > END > > BEGIN bram_block > PARAMETER INSTANCE = dsocm_bram > PARAMETER HW_VER = 1.00.a > BUS_INTERFACE PORTA = dsocm_porta > END > > BEGIN plb_v34 > PARAMETER INSTANCE = plb > PARAMETER HW_VER = 1.01.a > PARAMETER C_DCR_INTFCE = 0 > PARAMETER C_EXT_RESET_HIGH = 1 > PORT SYS_Rst = sys_bus_reset > PORT PLB_Clk = sys_clk_s > END > > BEGIN opb_v20 > PARAMETER INSTANCE = opb > PARAMETER HW_VER = 1.10.b > PARAMETER C_EXT_RESET_HIGH = 1 > PORT OPB_Clk = sys_clk_s > PORT SYS_Rst = sys_bus_reset > END > > BEGIN plb2opb_bridge > PARAMETER INSTANCE = plb2opb > PARAMETER HW_VER = 1.00.b > PARAMETER C_DCR_INTFCE = 0 > PARAMETER C_NUM_ADDR_RNG = 2 > PARAMETER C_RNG0_BASEADDR = 0x00000000 > PARAMETER C_RNG0_HIGHADDR = 0x1fffffff > PARAMETER C_RNG1_BASEADDR = 0x20000000 > PARAMETER C_RNG1_HIGHADDR = 0x2000ffff > BUS_INTERFACE SPLB = plb > BUS_INTERFACE MOPB = opb > PORT OPB_Clk = sys_clk_s > PORT PLB_Clk = sys_clk_s > END > > BEGIN opb_uartlite > PARAMETER INSTANCE = RS232 > PARAMETER HW_VER = 1.00.b > PARAMETER C_BASEADDR = 0x20000000 > PARAMETER C_HIGHADDR = 0x200000ff > PARAMETER C_BAUDRATE = 115200 > PARAMETER C_DATA_BITS = 8 > PARAMETER C_ODD_PARITY = 0 > PARAMETER C_USE_PARITY = 0 > PARAMETER C_CLK_FREQ = 66000000 > BUS_INTERFACE SOPB = opb > PORT TX = RS232_TX > PORT OPB_Clk = sys_clk_s > PORT RX = RS232_RX > END > > BEGIN opb_sdram > PARAMETER INSTANCE = opb_sdram_0 > PARAMETER HW_VER = 1.00.c > PARAMETER C_BASEADDR = 0x10000000 > PARAMETER C_HIGHADDR = 0x11ffffff > PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 0 > PARAMETER C_SDRAM_TMRD = 2 > PARAMETER C_SDRAM_TCCD = 1 > PARAMETER C_SDRAM_TRAS = 50000 > PARAMETER C_SDRAM_TRC = 100000 > PARAMETER C_SDRAM_TRFC = 100000 > PARAMETER C_SDRAM_TRCD = 20000 > PARAMETER C_SDRAM_TRRD = 20000 > PARAMETER C_SDRAM_TRP = 20000 > PARAMETER C_SDRAM_TREF = 64 > PARAMETER C_SDRAM_CAS_LAT = 2 > PARAMETER C_SDRAM_COL_AWIDTH = 9 > PARAMETER C_SDRAM_BANK_AWIDTH = 2 > PARAMETER C_SDRAM_AWIDTH = 12 > PARAMETER C_SDRAM_DWIDTH = 32 > PARAMETER C_OPB_CLK_PERIOD_PS = 15000 > BUS_INTERFACE SOPB = opb > PORT SDRAM_RASn = SDRAM_RASn > PORT SDRAM_DQ = SDRAM_DQ > PORT SDRAM_Clk = SDRAM_Clk > PORT SDRAM_CSn = SDRAM_CSn > PORT SDRAM_CLK_in = sys_clk_s > PORT SDRAM_CASn = SDRAM_CASn > PORT SDRAM_BankAddr = SDRAM_BankAddr > PORT SDRAM_Addr = SDRAM_Addr > PORT SDRAM_DQM = SDRAM_DQM > PORT OPB_Clk = sys_clk_s > PORT SDRAM_WEn = SDRAM_WEn > PORT SDRAM_CKE = SDRAM_CKE > END > > BEGIN plb_bram_if_cntlr > PARAMETER INSTANCE = plb_bram_if_cntlr_1 > PARAMETER HW_VER = 1.00.a > PARAMETER c_plb_clk_period_ps = 10000 > PARAMETER c_baseaddr = 0x30010000 > PARAMETER c_highaddr = 0x30013fff > BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port > BUS_INTERFACE SPLB = plb > PORT PLB_Clk = sys_clk_s > END > > BEGIN bram_block > PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram > PARAMETER HW_VER = 1.00.a > BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port > END > > > > BEGIN opb_emc > PARAMETER INSTANCE = opb_emc_0 > PARAMETER HW_VER = 1.10.b > PARAMETER C_OPB_CLK_PERIOD_PS = 15000 > PARAMETER C_BASEADDR = 0x00000000 > PARAMETER C_HIGHADDR = 0x000001ff > PARAMETER C_NUM_BANKS_MEM = 2 > PARAMETER C_MEM0_BASEADDR = 0x00100000 > PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_1 = 0 > PARAMETER C_SYNCH_MEM_0 = 0 > PARAMETER C_SYNCH_PIPEDELAY_0 = 2 > PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 150000 > PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 55000 > PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 70000 > PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 150000 > PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 55000 > PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 15000 > PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 35000 > PARAMETER C_SYNCH_MEM_1 = 0 > PARAMETER C_SYNCH_PIPEDELAY_1 = 2 > PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_1 = 150000 > PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_1 = 55000 > PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_1 = 70000 > PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_1 = 155000 > PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_1 = 55000 > PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_1 = 15000 > PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_1 = 35000 > BUS_INTERFACE SOPB = opb > PORT Mem_A = SRAM_A > PORT Mem_DQ = SRAM_DQ > PORT Mem_CEN = SRAM_CEN > PORT Mem_OEN = SRAM_OEN > PORT Mem_WEN = SRAM_WEN > PORT Mem_QWEN = SRAM_QWEN > PORT Mem_BEN = SRAM_BEN > PORT Mem_RPN = SRAM_RPN > PORT Mem_CE = SRAM_CE > PORT Mem_ADV_LDN = SRAM_ADV_LDN > PORT Mem_LBON = SRAM_LBON > PORT Mem_CKEN = SRAM_CKEN > PORT Mem_RNW = SRAM_RNW > END > > BEGIN opb_intc > PARAMETER INSTANCE = opb_intc_0 > PARAMETER HW_VER = 1.00.c > PARAMETER C_BASEADDR = 0x03000000 > PARAMETER C_HIGHADDR = 0x030000ff > BUS_INTERFACE SOPB = opb > PORT Intr = sys_irq > PORT Irq = opb_intc_0_irq > END >Article: 72931
have some small program: use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY dek_zak2 IS PORT (Zegar,Jesli11,Jesli13: IN std_logic; Wyjscie : OUT std_logic); END; architecture Behavioral of dek_zak2 is signal wartosc : integer range -3 to 12; signal nastepny : integer range -3 to 4; begin dek_zak2 : process (Zegar,Jesli11,Jesli13) begin if Zegar'event and Zegar = '1' then if wartosc = 11 then wartosc <= nastepny; nastepny <= 0; else wartosc <= wartosc + 1; end if; else if rising_edge(Jesli11) then if wartosc < 11 then wartosc <= wartosc + 1; else nastepny <= nastepny + 1; end if; end if; if rising_edge(Jesli13) then if wartosc > 0 then wartosc <= wartosc - 1; else nastepny <= nastepny - 1; end if; end if; end if; end process dek_zak2; end architecture; Check syntax ok. but later: ERROR:Xst:827 - D:/Xilinx/mdek_zak2.vhd line 16: Signal wartosc cannot be synthesized, bad synchronous description. ?? What this error mean??? (its webpack xilinx) www.xilinx.com do not solve this problem. Any solutions?? Pozdrowienia - Greetings 5hinkaArticle: 72932
On Wed, 8 Sep 2004 20:48:14 +1000, <Patrick Harold> wrote: >Unfortunatelly I'm not student. (I'm too old to be a student.. When I was >student, I was working with tubes (not even with transistors) ). >It is not so easy in my age to keep track with the all this new >technologies. I'm trying my best to follow the technology. I recently >started to study the VHDL. I'm almost on the "page one" of the VHDL study >and want to learn by implementing simple little projects. I first learned on tube designs, as well. Transistors were the 'new fangled' thing for me, later on. My first impressions, back when I was first reading about transistors, were that tubes were quite superior, as transistors required quite a bit more feedback to remain faithful to their inputs over a range. Oh, well. Long time ago. I don't have a lot of books on VHDL, but one that really helped me when I knew nothing at all was a book by a British guy who moved to Alabama some years back called, "HDL Chip Design." It provides a nice introduction that assumes very little by way of understanding and gives you a little history. Elsewhere in the book you will see both VHDL and Verilog examples of the same designs and he covers a great many of the basics. ASICs and FPGAs are discussed, with their attendant differences in emphasis when designing, but not so much that you get overwhelmed. Examples are given to show you how changes in an approach can yield improvements. He discusses RTL and gate level optimizations in a way that a newbie can easily fathom, I believe. In short, regardless of possible errors in the book today, it made a very easy path for me to get my first VHDL designs up and running on a real FPGA board. I went from not even knowing a single keyword of VHDL to my first properly functioning 4-bit adder and 7-segment digit display driver circuit in less than a week. And the code wasn't borrowed or stolen, I'd written it from scratch by myself. Which books might speak better to you, I don't know. But that one got me started and gave me enough of the basics that I could then start reading the VHDL others have written with some understanding and also begin to understand other FPGA issues the book didn't cover, like floorplanning. (obviously, I don't care about ASICs as I'm unlikely to be designing any unless I come into some cash I don't otherwise need.) JonArticle: 72933
Dear All, I wanna generate EDIF netlist from Verilog code. I am using Xilinx ISE6.2i software, and cannot find any trace of EDIF netlist generated. PS. The code synthesizes OK.Article: 72934
Think of how you would take a positive edge triggered flip-flop and wire it up to achieve your goals. Using multiple clocks to trigger a single register isn't a good synchronous design approach. If you're trying to do an up/down counter triggered by other (slow) events, consider running your system with a master clock and provide a single up/down *enable* pulse per up/down event. "5hinka" <anonim99@poczta.wp.pl> wrote in message news:chnb7j$8o7$1@nemesis.news.tpi.pl... > have some small program: > > > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > ENTITY dek_zak2 IS > PORT (Zegar,Jesli11,Jesli13: IN std_logic; > Wyjscie : OUT std_logic); > END; > > architecture Behavioral of dek_zak2 is > signal wartosc : integer range -3 to 12; > signal nastepny : integer range -3 to 4; > begin > > dek_zak2 : process (Zegar,Jesli11,Jesli13) > > begin > if Zegar'event and Zegar = '1' then > if wartosc = 11 then > wartosc <= nastepny; > nastepny <= 0; > else wartosc <= wartosc + 1; > end if; > > else > if rising_edge(Jesli11) then > if wartosc < 11 then wartosc <= wartosc + 1; > else nastepny <= nastepny + 1; > end if; > end if; > > > if rising_edge(Jesli13) then > if wartosc > 0 then wartosc <= wartosc - 1; > else nastepny <= nastepny - 1; > end if; > end if; > end if; > > end process dek_zak2; > > end architecture; > > > Check syntax ok. > but later: > ERROR:Xst:827 - D:/Xilinx/mdek_zak2.vhd line 16: Signal wartosc cannot be > synthesized, bad synchronous description. > > ?? > What this error mean??? > (its webpack xilinx) > www.xilinx.com do not solve this problem. Any solutions?? > > Pozdrowienia - Greetings > 5hinka >Article: 72935
"Patrick Harold" wrote: > > I would like to thank you for your understanding. > Unfortunatelly I'm not student. (I'm too old to be a student.. > When I was student, I was working with tubes (not even with > transistors) ). It is not so easy in my age to keep track with > the all this new technologies. I'm trying my best to follow the > the "page one" of the VHDL study technology. I recently started > to study the VHDL. I'm almost on and want to learn by > implementing simple little projects. Thank you once again for > your understanding. Tubes are not all that different from transistors, especially MOSFETs. They are considerably bulkier, require much higher voltages, need heaters, and dissipate much more power. However they are all 'gain blocks'. However you should learn to post correctly. Your answer belongs AFTER (or intermixed with) the material to which you reply, AFTER snipping out portions irrelevant to your answer. This is known as bottom-posting, and is always acceptable. What you are doing is called top-posting, which makes articles virtually unreadable and allows them to grow indefinitely, like a cancer. -- "I'm a war president. I make decisions here in the Oval Office in foreign policy matters with war on my mind." - Bush. "If I knew then what I know today, I would still have invaded Iraq. It was the right decision" - G.W. Bush, 2004-08-02Article: 72936
HDLnewbie wrote: > Is there much difference between a spartan 2 and 3 if its for relatively > small projects? Is a virtex product a major step up? > > Secondly is 200K gates very small for a fpga? I know you could > implement alot in 200K on an ASIC - but i persume its a completely > different story with an fpga? > "Gates" is largely a meaningless number for FPGAs. A "200,000 gate" Spartan device is, however, enough to implement a pretty sophisticated project including several microcontroller cores. FPGAs range anywhere from "15,000 gates" (400-ish LUTs) to tens of millions; price varies accordingly from single to four (or five?) digit numbers in U.S. dollars. -hpaArticle: 72937
I own an original CD of Xilinx Alliance series 2.1i but lost the CD-KEY to install the CD. I need it urgently because i have to re-use old XC3000 devices. Can anyone help me ? Thx. Mike.Article: 72938
Hi, If you study the PCI specs, you will see that there is a maximum lenght specified for the pcb traces (1.5" and 2.5 " for the clock line) . This is quite important because the signals and switching points rely on the reflected wave principle of the PCI bus.!!! I suggest you obtain the PCI specs. Your io ports on your FPGA must also be pci compliant and you really should take care of the right timing constraints to and from the PCI io pads, otherwise you might experience a lot of problems on the PCI bus. regards ron proveniers "Ted" <ted@ted.com> schreef in bericht news:chf9eq$frj$1@newsg2.svr.pol.co.uk... > Hi, > > I would like to make a simple PCI device. I already own an FPGA evaluation > board and I also own a blank PCI prototyping card. I was planning on > connecting the FPGA board to the PCI prototyping card via ribbon cables. > Would this cause problems with noise? Would it help if I kept the ribbon > cables quite short. > > Thanks for any info, > >Article: 72939
A good starting point , in my opinion , to gain some insight in the matter is asking : why would _you_ think SystemC is faster or slower ? Jos singh.shailendra@gmail.com wrote: > Hi, > Can anybody elaborate on the speed of the simulation in systemC in > comparision with Verilog. In our case we have used the systemC for > the modeling of RTL design, then verified the systemC RTL models. As > a final step > systemC RTL is converted into verilog RTL(line by line translation). > we are surprised to see the both systemC models and Verilog models are > running at almost same speed. Can you through some light on it, what > went wrong in the process? > is it systemC coding is not proper or may be testbench not written > properly or > if we code systemC and Verilog at same level of abstraction we should > same speed only.Article: 72940
Okay -- I think you (and others who replied) have missed one of the main points of SystemC. One of the points of SystemC is to enable you to model and simulate things at a HIGHER level of abstraction than RTL. If you write code at the RT level -- it will probably always simulate on the same order of magnitude whether it's Verilog or SystemC -- in fact since the Verilog simulators are more mature -- Verilog may simulate faster than SystemC (though I haven't done the exact measurements myself and it is simulator dependent). The talk about SystemC being faster is making the assumption that you write SystemC at a higher level of abstraction than your RTL. Though, as a side note, there are several vendors out there who will translate Verilog to optimized C/C++ or SystemC and then get about a 10x or more improvement over Verilog (TenisonEDA and Carbon Systems come to mind). In my opinion -- writing RTL in SystemC is a waste of time since Verilog (or VHDL) is more suitable to that task (and maintaining RTL descriptions in TWO languages seems like even more of a waste of time and is asking for trouble). In any case you can always have Verilog and SystemC co-exist by interfacing SystemC to RTL through a PLI or using one of the unified SystemC/Verilog simulators. My point -- adopting a new language without also adopting a new methodology that makes use of the power of the language will only give you limited benefit (if any benefit at all). For example, when going from schematic capture to Verilog -- many people at first used Verilog just like a textual schematic capture tool. This got them using an HDL (which is a step in the write direction), but they really didn't get the full advantage of the HDL until they started writing RTL that then could then synthesized into gates (basically raising the level of abstraction at which they modeled their design). So for SystemC some of the power of the language comes in being able to do a top-down implementation where you start with a high-level architectural model and refine it down to the RTL level (or perhaps use a behavioral synthesis tool once you get down to a appropriate level of abstraction). Also the SystemC Verification extensions (SCV) is another way SystemC can be used to improve your verification effort (here again -- you will probably need to use a different verification methodology to make full use of SCVs capabilities). I'll stop there -- if you look hard enough you should be able to find other references talking about the new methodologies enabled by SystemC. I hope that helps, Russell <singh.shailendra@gmail.com> wrote in message news:ab4d6621.0409072214.6b8ae5a@posting.google.com... > Hi, > Can anybody elaborate on the speed of the simulation in systemC in > comparision with Verilog. In our case we have used the systemC for > the modeling of RTL design, then verified the systemC RTL models. As > a final step > systemC RTL is converted into verilog RTL(line by line translation). > we are surprised to see the both systemC models and Verilog models are > running at almost same speed. Can you through some light on it, what > went wrong in the process? > is it systemC coding is not proper or may be testbench not written > properly or > if we code systemC and Verilog at same level of abstraction we should > same speed only.Article: 72941
Manfred Balik wrote: >I'm trying to use the i2c-core from opencores.org. >I made a project in Altera Quartus II and added the 3 VHDL-Files. >Compiling is no problem, but I have problems with the simulation. I'm doing: > 1) reseting the core > 2) write clock prescaler (Addr 0 and 1) > 3) enable core in control register (10000000 to Addr 2) > 4) write data for writing to slave to transmit register (Addr 3) > 5) start and write to command register (10010000 to Addr 4) >and nothing happens on the output-lines !!!??? >Reading the status register (Addr 4) shows 'Transfer in Progress' every >time! >What i am doing wrong ??? >Can someone help ? >Thanks, Manfred > > > > Forgot the pull ups on the i2c lines so the controller waits for the bus to become inactive? Regards ThomasArticle: 72942
Jim Granville wrote: > Thomas Rudloff wrote: > <snip> > >> Hi, >> >> I am currently developping the oposite and came up that it might not >> be good to use an FPGA because of >> routing delays that might no be equal on all paths. My suggestion is >> to use a cypress Roboclock to get >> four phases and use a CPLD to modulate the pulse. The CPLD path >> delays are expected to be allmost >> the same as long as you take care not to use more than five PTs. > > > "almost the same" depends on what precision matters.... > I expect this within 100ps when propperly floor planed. >> >> So in my application I have a 100MHz clock with four phases (1.25ns >> increment) and the FF triggering >> at rising and falling edges giving 800MHz resolution. >> >> My interrest is to know whether I can archive the same precission >> (<100ps) in an FPGA? >> >> Regards >> Thomas >> >> PS: It is a PWM modulator for a digital amplifier. > > > It is not clear what you are trying to do. From the application, more > than your questions, it sounds like you wish to control an edge > position to a precision of ~100ps ? On what lower Frequency ? > Ok, wasn't quite clear. I want to controll the edge with a selected phase with 1.25ns increment. The error between the different phases should not be more than 100ps. So I have an effective sampling rate of 800MHz and an error of 100ps max. > You can use multiple phase clocks to improve timing precision above > 1/fclk and getting to 1ns has the consensus of do-able. > That's what it is. > If your modulator frequency is high, you can also use rate-multiplier > edge modulation, to give better audio-band precision ? > I do not think that I can get the same precision. As long as the error is predictable I can correct it (noise shaping). > To get to 100ps is going to push away from the realm of clock edges, > and into the realm of silicon delay lines. > The 100ps are not the resolution. It's the phase error. > I think there are test modes in the DLLs, and carry chains are the user > fabric with the most speed. > > Philip F. made this comment in another thread re Virtex4 > > Looks like a 32 bit counter hits 360 MHz, in a -11, with preliminary > > speed files. Gotta love the 41.5 ps/bit carry chain. > > that suggests a time granularity of sub 50ps will be doable in the next > generation devices - these delays need continuous calibration, as they > will be Vcc/Temp/Process dependant. > It's interresting. But can I keep the different on chip routing delays of the different phases within 100ps to each other? The DLL surely will give me the resolution. But if one delay is some 100ps longer than the other there will be the same difference as phase error on the output for some patterns The simpliest way is to use a SERDES but I cannot use BGA chips..And since I need multiples using externals takes too mch PCB space. This could be an option for the OP if only one is needed. Regards ThomasArticle: 72943
Użytkownik "John_H" <johnhandwork@mail.com> napisał w wiadomości news:h4H%c.9$lc3.1857@news-west.eli.net... > Think of how you would take a positive edge triggered flip-flop and wire it > up to achieve your goals. > Using multiple clocks to trigger a single register isn't a good synchronous > design approach. > If you're trying to do an up/down counter triggered by other (slow) events, > consider running your system with a master clock and provide a single > up/down *enable* pulse per up/down event. > Ygh ?? Im litle bit new to vhdl. Ive tried to test having only one 'if' with event (first one) and two "ifs" normal: if Jesli11 = '0' ... but it doesnt change anything.Article: 72944
glen herrmannsfeldt wrote: > > > Thomas Rudloff wrote: > > (snip) > > >> My suggestion is to use a cypress Roboclock to get >> four phases and use a CPLD to modulate the pulse. The CPLD path >> delays are expected to be allmost >> the same as long as you take care not to use more than five PTs. > > > I just learned about the roboclock last week. According to the > sheet I have it only goes to 80MHz. Maybe there are newer ones that > go faster. > Yup, it's the CY7C994 IIRC. I do not have the datasheets at home. There is a part that goes up to 200MHz. >> So in my application I have a 100MHz clock with four phases (1.25ns >> increment) and the FF triggering >> at rising and falling edges giving 800MHz resolution. > > >> My interrest is to know whether I can archive the same precission >> (<100ps) in an FPGA? > > > The IOB FF's avoid the routing delay to internal FF's. Yup, but I need to OR the output of different FFs. But maybe an external gate could be an option. > > I don't know about 100ps, though. > It is only the difference of the different paths.Article: 72945
As a matter of clarity, the maximum length for most 32-bit PCI bus signals is 1.5" as you stated. But the clock line is specified to be 2.5" +-0.1" (2.4" to 2.6"). In other words, this is not a maximum length, it is a required length. I agree that you must get the specification, as there are numerous other important details. Such as decoupling ALL supply lines even if you make no connection to them. -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "newgroups" <rprovo@xs4all.nl> wrote in message news:413f5f68$0$37789$e4fe514c@news.xs4all.nl... > Hi, > > If you study the PCI specs, you will see that there is a maximum lenght > specified for the pcb traces (1.5" and 2.5 " for the clock line) . This is > quite important because the signals and switching points rely on the > reflected wave principle of the PCI bus.!!! > > I suggest you obtain the PCI specs. Your io ports on your FPGA must also be > pci compliant and you really should take care of the right timing > constraints to and from the PCI io pads, otherwise you might experience a > lot of problems on the PCI bus. > > > regards > > > ron proveniers > > > > "Ted" <ted@ted.com> schreef in bericht > news:chf9eq$frj$1@newsg2.svr.pol.co.uk... > > Hi, > > > > I would like to make a simple PCI device. I already own an FPGA > evaluation > > board and I also own a blank PCI prototyping card. I was planning on > > connecting the FPGA board to the PCI prototyping card via ribbon cables. > > Would this cause problems with noise? Would it help if I kept the ribbon > > cables quite short. > > > > Thanks for any info, > > > > > >Article: 72946
If you know nothing about hardware, you won't be able to code with VHDL. One of the basic building blocks of hardware is a register, or "flip-flop." This is a storage element that takes the data that was available on the input at (typically) the rising edge of the clock and transfers that value to the output. It is a very well defined piece of hardware that the HDLs have been designed to use. Your code will eventually be mapped to these storage elements and cannot be randomly combined. As a processor's line of assembly code has a mnemonic with specific parameters that apply for that mnemonic, so to does the hardware have specific building-blocks that can have only a preset combination of inputs and outputs. First try a simple up counter. Nothing fancy. I'd suspect you'll design with the up signal clocking the counter. Second, try to use a steady frequency to clock your counter on continuous clock edges with a one-pulse-wide enable when you want to count up. Third, extend the logic to have an up enable and a down enable to get your counter moving in the right direction, one tick at a time. Learning hardware is NOT something to do with code, it's something to do by understanding the function of the elements the HDL has to work with and writing the HDL to properly manipulate those pieces. Once you understand what the limits are of the hardware, synthesizable code should come easier. "5hinka" <anonim99@poczta.wp.pl> wrote in message news:chnsvu$f5r$1@nemesis.news.tpi.pl... > > Użytkownik "John_H" <johnhandwork@mail.com> napisał w wiadomości > news:h4H%c.9$lc3.1857@news-west.eli.net... > > Think of how you would take a positive edge triggered flip-flop and wire > it > > up to achieve your goals. > > Using multiple clocks to trigger a single register isn't a good > synchronous > > design approach. > > If you're trying to do an up/down counter triggered by other (slow) > events, > > consider running your system with a master clock and provide a single > > up/down *enable* pulse per up/down event. > > > > Ygh ?? Im litle bit new to vhdl. > Ive tried to test having only one 'if' with event (first one) and > two "ifs" normal: if Jesli11 = '0' ... but it doesnt change anything. >Article: 72947
I am testing a VHDL design using embedded CPU program memory which needs to be initialized. The data to be stored in the RAM comes from an external source and will be part of the configuration download in the final system. During simulation, I can't seem to figure out how to initialize it. I thought I might use the test bench to read the data from a file, but I can't figure out how to access the memory since it does not have an external interface. If I add logic to initialize the memory from the test bench, this will be unused in the real chip and so I will have a difference between my simulated chip and the real chip. I prefer not to do that. I have been using an initial value on the memory variable declaration, but the data changes as I work and this is very clumsy. I also saw an example using a shared variable with one process being the normal memory model and the other being an init routine. But again, this will use code that is only part of the simulation and should not be there for the end device. I guess the code will not be synthesized, but since it has to be in the target source and not the test bench, it will either need to be removed or it will likely produce errors in synthesis. Is there a way to directly access an internal signal or variable from a test bench? I seem to recall doing this before, but it was a long time ago and I may be getting a simulator command mixed up with VHDL. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72948
Thomas Rudloff wrote: > Jim Granville wrote: > >> Thomas Rudloff wrote: >> <snip> >> >>> Hi, >>> >>> I am currently developping the oposite and came up that it might not >>> be good to use an FPGA because of >>> routing delays that might no be equal on all paths. My suggestion is >>> to use a cypress Roboclock to get >>> four phases and use a CPLD to modulate the pulse. The CPLD path >>> delays are expected to be allmost >>> the same as long as you take care not to use more than five PTs. >> >> >> >> "almost the same" depends on what precision matters.... >> > I expect this within 100ps when propperly floor planed. > >>> >>> So in my application I have a 100MHz clock with four phases (1.25ns >>> increment) and the FF triggering >>> at rising and falling edges giving 800MHz resolution. >>> >>> My interrest is to know whether I can archive the same precission >>> (<100ps) in an FPGA? >>> >>> Regards >>> Thomas >>> >>> PS: It is a PWM modulator for a digital amplifier. >> >> >> >> It is not clear what you are trying to do. From the application, more >> than your questions, it sounds like you wish to control an edge >> position to a precision of ~100ps ? On what lower Frequency ? >> > Ok, wasn't quite clear. I want to controll the edge with a selected > phase with 1.25ns increment. The error between the different phases > should not be more than 100ps. So I have an effective sampling rate of > 800MHz and an error of 100ps max. > >> You can use multiple phase clocks to improve timing precision above >> 1/fclk and getting to 1ns has the consensus of do-able. >> > That's what it is. > >> If your modulator frequency is high, you can also use rate-multiplier >> edge modulation, to give better audio-band precision ? >> > I do not think that I can get the same precision. As long as the error > is predictable I can correct it (noise shaping). > >> To get to 100ps is going to push away from the realm of clock edges, >> and into the realm of silicon delay lines. >> > The 100ps are not the resolution. It's the phase error. > >> I think there are test modes in the DLLs, and carry chains are the user >> fabric with the most speed. >> >> Philip F. made this comment in another thread re Virtex4 >> > Looks like a 32 bit counter hits 360 MHz, in a -11, with preliminary >> > speed files. Gotta love the 41.5 ps/bit carry chain. >> >> that suggests a time granularity of sub 50ps will be doable in the next >> generation devices - these delays need continuous calibration, as they >> will be Vcc/Temp/Process dependant. >> > It's interresting. But can I keep the different on chip routing delays > of the different phases within 100ps to each other? > The DLL surely will give me the resolution. But if one delay is some > 100ps longer than the other there will be the same difference as phase > error on the output for some patterns > > The simpliest way is to use a SERDES but I cannot use BGA chips..And > since I need multiples using externals takes too mch PCB space. This > could be an option for the OP if only one is needed. Now I follow... The key question is: can you generate (eg) a 4 Phase clock, from a 200MHz source, to give 4 phases each 90' apart (1.25ns), with a time-precision of +/-100ps on each edge ? I believe you can do this with the std DCM (so do not need a Cypress Clock chip?), but Peter A. might be able to better advise the Family/speed grade to do this ? Since I think you want a pulse-modulation from this finer-time scheme, you will need to add the delay skews of the logic that decides which edge to act on. There is an Altera app note that specified the delays in each path of their LUT, and they are NOT all the same. Xilinx quote a single larger value, but it's not clear if that is because they are actually tightly matched, or if their SW cannot track the path deltas, so they take the worst one. -jgArticle: 72949
Christian E. Boehme wrote: > The problem arises with the PCI outputs configured as LVTTL TP outputs Forget about that ;-) The outputs are configured as PP buffers so your suggestion makes sense. It still looks a bit hack-ish, though ;) Cheers, Chris
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