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engineer_soul@yahoo.com (dave) wrote in message news:<ab662096.0403261656.1e4513fe@posting.google.com>... > Wouldn't this be dependent on the USB implementation ? > Are you implementing a USB core? > > I have used the FTDI 245BM usb module which is interfaced as a FIFO > for all the fpga cares, with a couple of control signals. The data > comes out of the chip through a bidirectional 8-bit bus. > > > Phillips has some other chips that you use through I2C > > I guess the question is if you wanting to simulate the data after the > it's been processed by a USB chip or core? Or, if the data is itself > the USB packets for the USB core? > Hi, the data is itself the USB packets for my USB application. It is the data we see on the USB. Rgds Andrés V.Article: 68176
tnbiggs@yahoo.com (tbiggs) wrote: > A few notes: > Systemverilog is getting adopted very fast (not 'in 6 years'). Most of > it is already in Synopsys's simulator, and will be in the next release > of Mentor's. Actual Modelsim is AFAIK able to do SV. > Why is everyone saying that VHDL is used more by FPGA designers? I don't know. In fact I can't see any advantages of VHDL vs Verilog that apply only for FPGA design. > Everyone I know (and I know a LOT of FPGA designers) is doing Verilog, > with the exception of the aerospace industry (because of military > contract requirements). Most European designs are VHDL based. Most European Universities teach VHDL, no Verilog. > Synopsys's CEO all but admitted that because of Systemverilog, they > will not be doing add-on work with VHDL in the future. This is HUGE. I think Sysnopsys tries to force the change to a language they could control :). But if Sysnopsy stops VHDL support, they are very likely to loose the entire European market. > somewhere where I had to learn Swahili, I could learn the language and > get work done, but not nearly as efficiently as if I could work using > English. Verilog has a lot in common with C. If you already are > familiar with C, then learning Verilog will go much faster. You are likely to crash when designing HW as SW-Programmer. But I admit, that the market of testbench engineering could use some more trained SW-Programmers. I've recently collected the advantages of SV for VHDL-Programmers for our company and there are few. SV is mostly a way to increase Verilog to VHDL with all merrits and flaws. Of course there are advantages of changing from VHDL to SV. bye ThomasArticle: 68177
Hello all, I'm using ISE6.1 and I can't seem to find a way to set the desired clk frequency. When I run synthesis without prior frequency settings of any kind, it turns out that the maximal frequency is about 45MHz. The design goal is to acchieve the frequency of 50MHz, so I'm willing to sacrifize more time remodeling to accomplish requirements. I know that there must be a way to tell the tool that you want the frequency at any cost, then (if this is not possible) to start Timing Analysis to find out which path(s) is(are) critical, and try to fix the problem by redesigning something around it(them). The only problem is that I don't know how to tell the tool what is my desired frequency. I tried using a .xcf file, the tool reports reading it, but estimates the same maximal frequency without a warning or error message. Help? Best regards, and thanks in advance MarijaArticle: 68178
On Mon, 29 Mar 2004 05:15:00 +0000 (UTC), Larry Doolittle <ldoolitt@recycle.lbl.gov> wrote: >In article <n3re60dh0tg7hkms19vi78un1tlbs7ogqj@4ax.com>, Allan Herriman wrote: >> I notice you didn't mention "correct". For me, correctness is the >> most important attribute of a simulator. > >I agree. While I am not a language lawyer, and my usage probably >passes for simple, I haven't seen any incorrect answers from Icarus >for a long time. I see plenty of problems, but I use a number of Verilog 2001 features (which don't seem to be supported all that well). Regards, Allan.Article: 68179
On 24 Mar 2004 18:29:00 -0800, mdini@dinigroup.com wrote: >1. I don't know ANYBODY that is fluent in both VHDL and Verilog that >prefers VHDL. You really need to read Karl Popper. Your hypothesis is proven false because I'm fluent in both and, on balance, I prefer VHDL. I can think of two or perhaps three things that Verilog can do that VHDL can't, and I will happily use Verilog when those things are important. If my primary concern were library-level modelling with timing models that can be back-annotated, then my preference would overwhelmingly be for Verilog. As a front-end designer, though, I'm much less worried about that stuff. > The only advantage of VHDL is the signed arithmetic. Don't be silly. What about.... - arbitrary user-defined types - arbitrary types on any entity port - arbitrary types on generics (sorry, parameters) - array and type attributes - user-defined attributes that can be configured programatically >That doesn't make up for the useless type-checking You're welcome to your opinion; some of us like to use data types to make our code more robust and to improve its self-documentation. > and lack of ifdef's. Proper use of generics and attributes usually deals with most things you may need to do with ifdef. Configurations (ooh, what are they in Verilog then?) do the rest. >2. Remember the infamous Verilog vs. VHDL competition that Cooley did >a few years back? See this link: ><http://www.deepchip.com/items/snug99-42.html> >In this contest, not a single VHDL contestant was able to finish the >problem. Not one. >3. I hope the competition is using VHDL. It is, often with great success. To the original poster I say: learn either, learn it properly, but then learn the other one as well. Then make up your own mind. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68180
>> and lack of ifdef's.
>Proper use of generics and attributes usually deals with most things
>you may need to do with ifdef. Configurations (ooh, what are they
>in Verilog then?) do the rest.
This is a good time for a rant...
Any even half decent unix/makefile hacker can apply the normal cpp
ifdef processor to a text file.
My experience with CAD tools in general is that they try to do
everyting but always miss some obscure corner that I really want to
do. This is a good example.
What I really want is a good list/map of which files are the
raw source files (edited by people) and which files read them
and what files they make so I can do several things:
1) build a makefile so I can push the big green button
from the command line by typing "make"
2) know which files I need to back up
3) know which files to inspect if I'm trying to figure
out which change fixed or broke something.
4) customize things, like adding cpp/ifdef or script hacks to work
around bugs/ommisions in the tools
My favorite example is that the pinout on an FPGA needs to be
coordinated/shared by both the FPGA tools and the board layout
tools. What I want is a single master file that gets translated
into whatever format the tool needs. (I'm happy to write the
script to do that.)
Of course, the other half of this rant is that the file formats must
be documented. I'm happy with an example or reverse engineering
for the trivial cases, but that's not good enough when things get
complicated.
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
Article: 68181On Mon, 29 Mar 2004 10:21:19 -0000, hmurray@suespammers.org (Hal Murray) wrote: >This is a good time for a rant... Nothing beats a good rant to liven up a Monday morning. [...snip a really rather mild and gentlemanly rant...] >What I really want is a good list/map of which files are the >raw source files (edited by people) and which files read them >and what files they make so I can do several things: Hear, hear. Most EDA tools create a plethora of files for each job, often in obscure subdirectories. It can be *very* hard to work out which of these are vital to the design flow, and which are just cached data or temporary files. >My favorite example is that the pinout on an FPGA needs to be >coordinated/shared by both the FPGA tools and the board layout >tools. And a bunch of other stuff too. Boundary scan tools, ATPG... > What I want is a single master file that gets translated >into whatever format the tool needs. (I'm happy to write the >script to do that.) >Of course, the other half of this rant is that the file formats must >be documented. Plain text is good. Let me say that again, loudly, in case there are any tool vendors out there who are slightly hard of hearing: PLAIN TEXT IS GOOD. And, of course, documentation as Hal says. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68182
Hi, I downloaded the 6.1i Update #1 in order to be able to generate the 1 gigabit ethernet mac with coregen. It should be possible to simulate the generated ip. However, I'am not able to do so. After running the implement.bat file from a command line, I start modelsim XE (full edition). I navigate to the test/vhdl directory and run the command "do simulate_mti.do". Two warnings are generated and the simulator is being very very busy? It's very slow in generating the results in the wave window. Is this normal, or should the testbench be executed in "no time"? And what about the warnings that are generated?? Modelsim output generated: # Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading package vital_primitives # -- Loading package textio # -- Loading package vpackage # -- Compiling entity netlist # -- Compiling architecture structure of netlist # -- Loading entity x_zero # -- Loading entity x_ff # -- Loading entity x_buf # -- Loading entity x_ibufds # -- Loading entity x_dcm # -- Loading entity x_ckbuf # -- Loading entity x_lut3 # -- Loading entity x_one # -- Loading entity x_lut4 # -- Loading entity x_lut2 # -- Loading entity x_mux2 # -- Loading entity x_sff # -- Loading entity x_srlc16e # -- Loading entity x_xor2 # -- Loading entity x_and2 # WARNING[1]: routed.vhd(38389): No default binding for component: "x_gt". (No entity named "x_gt" was found) # -- Loading entity x_or2 # -- Loading entity x_tri # -- Loading entity x_inv # -- Loading package vital_timing # -- Loading entity x_roc # -- Loading entity x_toc # Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 # -- Loading package standard # -- Compiling entity testbench # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Compiling architecture behav of testbench # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading package vital_primitives # -- Loading package textio # -- Loading package vpackage # -- Loading entity netlist # vsim -t ps work.testbench # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.numeric_std(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../vital2000.vital_timing(body) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.vcomponents # Loading C:/Modeltech_xe/win32xoem/../vital2000.vital_primitives(body) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.vpackage(body) # Loading work.testbench(behav) # Loading C:/Modeltech_xe/win32xoem/../ieee.vital_timing(body) # Loading work.netlist(structure) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_zero(x_zero_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_ff(x_ff_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_buf(x_buf_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_ibufds(x_ibufds_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_dcm(x_dcm_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.dcm_clock_divide_by_2(dcm_c lock_divide_by_2_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.dcm_maximum_period_check(dc m_maximum_period_check_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.dcm_clock_lost(dcm_clock_lo st_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_ckbuf(x_ckbuf_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_lut3(x_lut3_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_one(x_one_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_lut4(x_lut4_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_lut2(x_lut2_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_mux2(x_mux2_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_sff(x_sff_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_srlc16e(x_srlc16e_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_xor2(x_xor2_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_and2(x_and2_v) # ** Warning: (vsim-3473) Component 'gmac_core_bu2_u0_gpcs_pma_inst_mgt_mgt_gt' is not bound. # Time: 0 ps Iteration: 0 Region: /testbench/dut File: routed.vhd # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_or2(x_or2_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_tri(x_tri_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_inv(x_inv_v) # Loading C:/Modeltech_xe/win32xoem/../ieee.vital_primitives(body) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_roc(x_roc_v) # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_toc(x_toc_v) # WARNING: No extended dataflow License exists # .source .process .signals .variables .dataflow .list .wave # ** Note: Resetting core... # # Time: 0 ps Iteration: 0 Instance: /testbench # ** Note: Timing checks are valid # # Time: 700 ns Iteration: 0 Instance: /testbench # ** Note: Disabling Auto-Negotiation in PCS sublayer.... # # Time: 700 ns Iteration: 0 Instance: /testbench # ** Note: Transmitting four frames... # # Time: 27600 ns Iteration: 1 Instance: /testbench TIA, FrankArticle: 68183
Hello, Here In our company we have just installed the new ISE 6.2 plus the SP1. Previoudsly we have been using the ISE 6.1 SP3 and the EDK 6.1 SP2. Now that we have installed the ISE6.2 the EDK ( Xilinx Platform Studio ) won't start. We get the following error: $XILINX does not point to and iSE 6.1 installation. So does this mean that we have to install the ISE6.1 back? Best Regards George MercuryArticle: 68184
Hi Spyros, Thanks for offering to post your final scripts. I think I will I find them quite useful as well. -- Pete > Yes! That finally worked and now I have an .rcf file. So the > basic problem before was I hadn't any on-line help on the > logiclock_back_annotate command... > > So, I believe now I have a fairly good starting point with > the TCL logiclock flow. When I consolidate it, I will post > the final complete scripts so that others might find it > useful. > > So long and thanks for all the help, > Spyros >Article: 68185
Im designing jitter measureer for 2048kHz HDB3 signal. Part of this design will be PLL for 2048kHz signal. Jitter will be big up to 50-100 UI. I would like also to build this PLL with possibility to customize time of Loop Filter. Im thinking about DPLL in Xilinx (there will be one in this circuit). Anybody got or seen somewhere schematic/program in VHDL/Verilog of DPLL for FPGAs ?? Thx Greetings 5hinkaArticle: 68186
Hi All, I'm working on the design which needs to be implemented in radiation tolerant Actel chips. Unfortunately I have only remote access to the machine with the Actel Designer installed, so it is painfully slow. Is it possible to compile the design from the command line? Where can I find info about using the Actel tools from CLI instead of GUI? -- TIA & Regards, Wojtek ZabolotnyArticle: 68187
Jim Lewis wrote: >>What is the user base really at? Based on newsgroup >>traffic (comp.lang.vhdl vs. comp.lang.verilog), >>VHDL usage is 2X that of Verilog. >> john jakson wrote: > Aha, about as useless as counting the no of HDL textbooks in the local > EE store. But the book writing industry is remote from HW design, they > write what the Universities request. Infact its a wonder Verilog > survived the almost 100% teaching of VHDL in most schools. I rarely > hear of Verilog being tought in any school. How can you question this measure and not realize that what Cooley has published is nothing more than twisting EDA sales numbers trying to make the user base look like it is mostly Verilog. In Cooley's numbers, I did not see any normalization for tool prices. So why do you let Cooley pull the wool over your eyes. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 68188
I have a design that come very close to filling a Xilinx XCS20 - it has 400 complex logic blocks, and I'm using 388 (97% usage). Under Foundation 3.1, the design needs multiple reentrant routes to work properly, and sometimes bringing out debug information to a spare pin causes the whole thing to fail to route. Yes, I know this is cutting it close, but I'm trying to make a new set of functions fit on an old card. We're stuck with this design for now (we could go to the larger XCS40, but that would require getting new parts and replacing the existing ones - time consuming). My questions are: what is a good rule of thumb for CLB usage %, and are there particular issues with Foundation 3.1 that I should be aware of? (reply in thread so others can benefit from your expertise too...) Thanks in advance, JohnArticle: 68189
I would try to optimize the logic and reduce the LUT-count that way. There ususally is some fat that can be eliminated, without changing the functionality or performance. "Usually", not always... Peter Alfke > From: google.20.jlbraun@spamgourmet.com (John Braun) > Organization: http://groups.google.com > Newsgroups: comp.arch.fpga > Date: 29 Mar 2004 09:29:56 -0800 > Subject: CLB usage: Xilinx XCS20 and Foundation 3.1 > > I have a design that come very close to filling a Xilinx XCS20 - it > has 400 > complex logic blocks, and I'm using 388 (97% usage). Under Foundation > 3.1, > the design needs multiple reentrant routes to work properly, and > sometimes > bringing out debug information to a spare pin causes the whole thing > to fail to route. > > Yes, I know this is cutting it close, but I'm trying to make a new set > of functions fit on an old card. We're stuck with this design for now > (we could go to the larger XCS40, but > that would require getting new parts and replacing the existing ones - > time > consuming). My questions are: what is a good rule of thumb for CLB > usage %, > and are there particular issues with Foundation 3.1 that I should be > aware > of? > > (reply in thread so others can benefit from your expertise too...) > > Thanks in advance, > > JohnArticle: 68190
This maybe due to the declaration of INIT. The UNISIM defines
this as bit_vector, but you have declared it as a string.
component RAM16X1S
generic (
INIT : bit_vector := X"0000"
);
Patrick Robin wrote:
> After trying everything I could think of including all suggestions in
> this thread, it still didn't work. Then I decided to try RAM32X1S,
> that worked fine, then I tried RAM64X1S, that worked fine also. So I
> don't know why RAM16X1S won't synthesis properly when taken straight
> from the Xilinx example vhdl files and Xilinx app note 464.
>
> I won't research this further since ultimately, what I need is
> RAM64X1S . Initially, I tried RAM16X1S to start small and work my way
> up.
>
> Thanks for all suggestions.
>
> Patrick
>
>
> mike_treseler <mike_treseler@comcast.net> wrote in message news:<jNSdnYFqD-oXsPrdRVn-gw@comcast.com>...
>
>>Patrick Robin wrote:
>>
>>
>>>I have been trying to use distributed ram on a Spartan 3. I get an
>>>error from XST with with this simple example from the docs
>>
>>
>>
>>>ERROR:Xst:764 - E:/data/f100/f100mb/dutyRAM16.vhd line 48: No default
>>>binding for component: <RAM16X1S>. Generic <INIT> is not on the
>>>entity.
>>
>>
>>
>>>Am I missing something?
>>
>>Perhaps the meaning of the error message.
>>To get a default binding,
>>the component and library entity
>>must have not only the same name, but matching
>>ports and generics. Try commenting out the
>>generic maps.
>>
>>I agree with Kevin, that inferring this ram
>>would be much less trouble.
>>
>> -- Mike Treseler
--
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
\ \ ` Xilinx hotline@xilinx.com
/ / 2100 Logic Drive http://www.xilinx.com
\_\/.\ San Jose, California 95124-3450 USA
Article: 68191If you're really connecting the I/O pin of the PIC directly to the RS232 line, you must be aware that you're not meeting the standard voltage levels. It probably works with the PC because they don't use standard circuits, either. True RS232 requires voltages to swing below ground to guarantee switching the receiver. Some receivers are modified with positive threshold offset to accommodate TTL input signals. I don't know what's used on the nios, but you should probably look at the output of the receiver to see if your signal gets through. Srikanth Anumalla <srikanth_nospam@yahoo.com> wrote in message news:<del9c.3919$lt2.2992@newsread1.news.pas.earthlink.net>... > Hi > > I have pic (12f675) which is conected to a sensor. PIC will digitise the > signal from sensor and sends it over one of the on of IO pins. This pin > is connected to Rx wire of the rs232 cable. the other end of rs232(male) > is connected to console port of Altera nios board. the PIC continuously > sends 8 bit data over the Rx line of the console. My problem is, when I > am trying to read a byte from console using the default function > provided ie nr_uart_rxchar(). Its always returning -1. I have tested > the my program on PIC by connecting it to serial line of a pc and > reading the serial line using a program. It just works fine. I did not > change any parameters on nios board as I am using the default nios > values with PIC also. Please ignore my ignorance as I am just begingin > to work with rs232. I am sure I am missing something here. I would > appreciate any pointers or help regarding this. > > Thank you > SrikanthArticle: 68192
Rudolf Usselmann wrote: <snip> > Damn ! I knew about uselib but didn't check the verilog > simulation model. Turns out somebody (probably me) forgot > to update a link on the compute server ! We keep several > generations of ise around, installed under ise_m.n and > create a symbolic link "ise" pointing to the latest one. > Well, the compute server was still pointing to 6.1 ... > > OK, I recompiled everything now and rerun the simulations. > > Now I correctly see no error messages after the normal > startup complaints. And the test suite passes too. > > Why do you say that the "uselib" is not intended ? I find > it actually quite useful - if I remember that it is there ! > Saves me the trouble to look up the path for the library > and specifying it ... > As I explained before, the general recommendation is to use a pre-compilation method for our libraries and thus the `uselib would render that method ineffective. Library pre-compilation saves some compilation time and disk space in the long run, especially if multiple projects are running but if `uselib or the -y switch works for you, by all means, continue using it. As the old saying says, "There is more than one way to fry a fish", and there is certainly more than one way to simulate a design. Go with what works best for you. Glad to hear you resolved the problem. -- BrianArticle: 68193
I'm trying to find an experienced FPGA Engineer (currently holding a clearance) - where do people like this look for jobs typically? The clearance is critical to this opening. Thank you for your help - Kelly kellydingee@adelphia.netArticle: 68194
George,
EDK tools work only with the corresponding ISE releases. So, For EDK
6.1, you must have ISE 6.1. Service packs do not matter, but the major
release numbers must be in sync. This going to be the case going forward
too because EDK uses some common code from ISE and hence the two can not
be out-of-sync.
Amit.
George wrote:
> Hello,
> Here In our company we have just installed the new ISE 6.2 plus the
> SP1. Previoudsly we have been using the ISE 6.1 SP3 and the EDK 6.1
> SP2. Now that we have installed the ISE6.2 the EDK ( Xilinx Platform
> Studio ) won't start. We get the following error: $XILINX does not
> point to and iSE 6.1 installation. So does this mean that we have to
> install the ISE6.1 back?
>
> Best Regards
> George Mercury
Article: 68195I'm having a problem with a XC3S200 device, and Xilinx tech support has been stumped to this point. The device is set up for hot-swap mode (HWSAPEN=2.5V). I have a signal which is pulled low externally to the part. Everything looks fine until about the last 3mS of the configuration when it appears that the IO pullup resistor is connected to the pin. This signal is an output that is then driven low upon the completion of configuration. I just checked, and saw the same behavior on the XC3S50ES device that we used on the previous version of our board only the pullup value seems to be lower on those devices which is why it didn't cause problems for us then. We are configuring at about 500KHz. Any ideas? Thanks, GaryArticle: 68196
Hi, I'm curious if anyone else there has had difficulties programming a V2pro with a design using the xilinx gmac logicore. The specific nature of the problem i experience is as follows. I have a completely working design with 2 gmac cores and some of my own "user" logic. I download and run the design with no issues. I make some very minor changes to the user logic that is completely unrelated to the gmac core and again I download the design. now both gmac cores do not seem to work on the chip. 1 does work and communicates fine with the fiber cable attached to the MGT, but the other gmac core does not seem to function at all. Now here is the tricky part. If I burn the PROMs on my board with same bit file that did not work a minute ago and reset the board both gmac cores function properly. I'm not sure if the problem is in the gmac design or in the xilinx chip but it doesn't make sense that downloading it doesn't work but then burning it to the proms does work. Has anyone else had any experience with this? Thanks MattArticle: 68197
Gary, The HSWAP_en pin is doing its job, as the pullups are not enabled when the pin is tied high. But, the pin is pulling high 3 ms before the end of config looks like the startup options are not right. One is able to release various things prior to the DONE going high, based on the cycle of the config clock at the end. The default start-up sequence, page 39 of http://direct.xilinx.com/bvdocs/publications/ds099-2.pdf states that "one CCLK cycle after DONE goes high GTS is released." Once global tristate is released, then the IO pin will do whatever you programmed it to do. If it is a LVCMOS IO driver, after GTS is released, it immediately is going to pull high, until the input to that driver pulls low, and then it pulls low. Instead, program the IOB pin in question to be a tristate driver, with its initial state as tristate, in which case after config, or even during config, it will be tristate until the user logic is up and running, and then you can control it to do what you would like without worrying about the startup sequence. I prefer to program every pin to explicitly be what I want it to be only under my control (user logic), and not rely on the startup sequence for it to work properly, as the startup sequence is something that folks can, and do, often get confused about (and forget about in the future if it is anything different from the default). What is the pull down resistor value? The internal pullup can vary from 5K to 50K, so if it is the pullup, it is pretty easy to verify. The IOB itself will be whatever the programmed strength is, which will be at least 2 mA (~ 1K), or larger current (lower ohms). Austin Gary wrote: > I'm having a problem with a XC3S200 device, and Xilinx tech support > has been stumped to this point. The device is set up for hot-swap > mode (HWSAPEN=2.5V). > > I have a signal which is pulled low externally to the part. > Everything looks fine until about the last 3mS of the configuration > when it appears that the IO pullup resistor is connected to the pin. > This signal is an output that is then driven low upon the completion > of configuration. I just checked, and saw the same behavior on the > XC3S50ES device that we used on the previous version of our board only > the pullup value seems to be lower on those devices which is why it > didn't cause problems for us then. We are configuring at about > 500KHz. > > Any ideas? > Thanks, > GaryArticle: 68198
"Peter Sommerfeld" <petersommerfeld@hotmail.com> wrote in message news:5c4d983.0403271458.43ee7ad9@posting.google.com... > Unfortunately the AHDL > stuff could not be testbenched though Is that why Altera MaxPlus II does not support testbench for Verilog either? Other tools support testbench, MaxPlus II doesn't! HendraArticle: 68199
John Williams wrote: > > If you already are >> familiar with C, then learning Verilog will go much faster. > C is a procedural language, while Verilog is a hardware description > language. They are utterly different things, and while syntactic > analogies may be comforting, they may also cause novice hardware > designers to make the fatal error of thinking "hey cool, this is just > like C"... but fundamentally it's absolutely nothing like C! They are fundamentally different but philosophically similar. My high school geometry teacher, describing the way the class did proofs had a saying, "Why do it the easy way when there is a hard way". > In transitioning from software design to hardware design, it is the > semantic differences that are really important (sequential program code > vs hardware description). Syntax is just the means to express it. > Obscuring that fact is not going to be helpful in the long run. The idea of using simple statements and expressions when simple is all that is needed is a little like C. I was never confused about the difference between sequential and parallel design. Well, pretty much all of my verilog is structural model. Behavioral model would tend to confuse me as to sequential code. Now, the people who try to use C as a hardware description language are the ones I really don't understand. Two that I know about (though not much about) are Handel C and Transmogrifier C. (snip) -- glen
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