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Messages from 74875

Article: 74875
Subject: Real numbered operations
From: Gorker <gorker@su.sabanciuniv.edu>
Date: Wed, 20 Oct 2004 13:48:25 -0700
Links: << >>  << T >>  << A >>
Hello,
My question is simple but I'm confused. How can I make operations with any real number (for ex : 0,432)? Just a simple code that multiplies X*coef(realnumber) and puts it into Y would be enough for me. Y must be output.
Thanks

Article: 74876
Subject: Re: Real numbered operations
From: Gorker <gorker@su.sabanciuniv.edu>
Date: Wed, 20 Oct 2004 13:49:47 -0700
Links: << >>  << T >>  << A >>
by the way, I am using Verilog.

Article: 74877
Subject: Re: Real numbered operations
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 20 Oct 2004 14:07:42 -0700
Links: << >>  << T >>  << A >>
May I suggest comp.lang.verilog ?
Good luck, Syms.
"Gorker" <gorker@su.sabanciuniv.edu> wrote in message
news:ee89a09.0@webx.sUN8CHnE...
> by the way, I am using Verilog.



Article: 74878
Subject: Re: Back-Annotate Assignments
From: Ben Twijnstra <btwijnstra@chello.nl>
Date: Wed, 20 Oct 2004 21:21:38 GMT
Links: << >>  << T >>  << A >>
Hi Andre,

> what does back-annotate assignments exactly mean?

It basically means that, for instance, pin locations chosen by Quartus are
now converted to 'hard' assignments in the currently-used .qsf file.

Quartus will let you go into all sorts of detail, down to individual LE
placement. Most of the time you'll only want the pinout to be
back-annotated. 

You will very likely get into trouble with your PCB guy though, as the
automatic pin placements that Quartus produces are not the most optimal
ones for PCB design.

If you want to try out different pinouts, Quartus II 4.1 has the ability to
create several revisions of a project, including different pinouts, logic
options etc.

Best regards,


Ben


Article: 74879
Subject: Re: Real numbered operations
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Wed, 20 Oct 2004 15:23:53 -0600
Links: << >>  << T >>  << A >>
Gorker wrote:
> Hello,
> My question is simple but I'm confused. How can I make operations with any real number (for ex : 0,432)? Just a simple code that multiplies X*coef(realnumber) and puts it into Y would be enough for me. Y must be output.
> Thanks

Is this supposed to be synthesizable?  Reals in Verilog aren't 
synthesizable.  If you want to synthesize and use fractional numbers, 
you'll have to use fixed-point and keep track of the radix point yourself.
-Kevin

Article: 74880
Subject: Re: spartan 3 on 4 layers
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 20 Oct 2004 14:33:29 -0700
Links: << >>  << T >>  << A >>
All,

IBIS 4.0 is now out for bid for the "golden parser."

Without a "golden parser", no one can say they adhere to the standard.

The last golden parser was back in the IBIS 1.2 days, so that is all 
anyone can lay claim to.

If you claim something more than that, you are not being entirely 
honest.  Small errors in the IBIS file get rejected by various tools, 
and support mushrooms.

As well, not everyone implemented the changes in IBIS 2, 3.... the same 
way, or the simulators implementations were also not identical....

We have 200,000+ seats of software out there, and trying to blaze a new 
trail for IBIS is like pushing tons of wet spaghetti (hard work, and not 
very satisfying).

We are actively looking at when to fold in the new IBIS, but only after 
it is supported by the tools that allow us to succeed.  Until then, we 
use what we have got, which includes the encrypted hspice versions for 
folks that have to have the "answer."

For the MGTs, no one can say if IBIS is adequate or not for differential 
signals at 10 Gbs, so we are sticking to methods that we know work.  We 
do know that behavioral models are really fast, but also really 
inaccurate.  If someone has a complete backplane simulation with 
extracted pcb parasitics (s parameters, complex lossy t-lines, 
connectors, pre-emphasis transmitter and adaptive receiver, etc.) that 
is within 5% of the behavioral model, I'd like to know how the miracle 
occurred.

Austin

Article: 74881
Subject: Async reset
From: "Jason Berringer" <jberringer@sympatico.ca>
Date: Wed, 20 Oct 2004 18:41:08 -0400
Links: << >>  << T >>  << A >>
Hello all,

I have a general question regarding asynchronous and synchronous resets.
Does an async. reset slow down the speed of a circuit? Is it better to use a
synchronous reset, or if possible no reset at all to speed up a design? I'm
just curious as I have a larger project which has a single async reset to a
lot of different blocks using the typical:

if (reset = '0') then
...
elsif (rising_edge(clk)) then
...
else
...
end if;

Not all block require the reset since they are downstream of earlier ones
with a reset and their state isn't critical, I have just always included
them. That being said I want to speed up the design, and in one block I took
out the reset and it seemed to boost the performance slightly.

Any comments would be appreciated.

Jason



Article: 74882
Subject: When will the ML401 source be released?
From: "Pete Fraser" <pete@rgb.com>
Date: Wed, 20 Oct 2004 15:44:08 -0700
Links: << >>  << T >>  << A >>
The web site says"

"Note: Many of these demonstration programs were developed
using advance versions of the EDK 6.3 tools. The project files
and hardware/software source files will be released when these
tools are released."

6.3 has been out for a while, so when do we get the 401 sources?



Article: 74883
Subject: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 20 Oct 2004 16:27:46 -0700
Links: << >>  << T >>  << A >>
Jim Stewart <jstewart@jkmicro.com> writes:
> And conversely, we've all paid for support and not
> gotten anything at times (:

There's a saying that "you get what you pay for".  What they don't
normally bother to tell you is that that is the *best* case.

Article: 74884
Subject: Re: Async reset
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 20 Oct 2004 17:09:14 -0700
Links: << >>  << T >>  << A >>


Jason Berringer wrote:

> I have a general question regarding asynchronous and synchronous resets.
> Does an async. reset slow down the speed of a circuit? Is it better to use a
> synchronous reset, or if possible no reset at all to speed up a design? I'm
> just curious as I have a larger project which has a single async reset to a
> lot of different blocks using the typical:

If the target logic has an asynchronous reset, which I believe
all FPGAs have, then it is already there and all you need to do
is wire it up.

Synchronous reset will be done using logic resources.  It might
be that there are enough CLB inputs not to add more, though it
might need another column, depending on the function.

A separate question is that asynchronous reset needs not to be
too close to the clock edge, so it might need to be synchronized
(even though not synchronous).

-- glen


Article: 74885
Subject: Re: Active Rece\onfiguration of Xilinx FPGAs
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Thu, 21 Oct 2004 10:53:34 +1000
Links: << >>  << T >>  << A >>
Hi Kedar,

Kedar P. Apte wrote:

> I need some practical info on 
> has any body used Xilinx Vertex series of FPGAs for any project
> involving active partial reconfiguration
> 
> I mean to say that if a part of FPGA is working then can we
> reconfigure another part of the FPGA and make it work

There's a Xilinx app note with example design files that walks you 
through the most basic possible use of partial reconfiguration (xapp 260 
or 269, something like that).

A while ago I setup the partial-reconfig mailing list dedicated to this 
topic.  It's pretty quiet but feel free to join and start asking 
questions:

http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/index.html#partial-reconfig

Regards,

John

Article: 74886
Subject: Re: a pci implemenation problem, thanks
From: "NoThisRAT" <nothisrat@yahoo.com>
Date: Thu, 21 Oct 2004 09:39:39 +0800
Links: << >>  << T >>  << A >>
  Thanks Greg and Ben, I finally made it work. The problem is, I should
remove the parallel download cable from the board before rebooting :P
  Thanks again!




Article: 74887
Subject: Re: Async reset
From: Prasanth Kumar <lunix@comcast.net>
Date: Thu, 21 Oct 2004 02:29:07 GMT
Links: << >>  << T >>  << A >>
On Wed, 2004-10-20 at 18:41 -0400, Jason Berringer wrote:
> Hello all,
> 
> I have a general question regarding asynchronous and synchronous resets.
> Does an async. reset slow down the speed of a circuit? Is it better to use a
> synchronous reset, or if possible no reset at all to speed up a design? I'm
> just curious as I have a larger project which has a single async reset to a
> lot of different blocks using the typical:
> 
> if (reset = '0') then
> ...
> elsif (rising_edge(clk)) then
> ...
> else
> ...
> end if;
> 
> Not all block require the reset since they are downstream of earlier ones
> with a reset and their state isn't critical, I have just always included
> them. That being said I want to speed up the design, and in one block I took
> out the reset and it seemed to boost the performance slightly.
> 
> Any comments would be appreciated.
> 
> Jason
> 
> 

If you are using Xilinx FPGAs then they have a nice techxclusives
article about just this. 

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?
sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=kc_smart_reset



Article: 74888
Subject: Re: unstable fpga design
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 21 Oct 2004 00:12:50 -0400
Links: << >>  << T >>  << A >>
Nial Stewart wrote:
> 
> "Moti Cohen" <moti@terasync.net> wrote in message
> news:c04bfe33.0410200517.391ab8d9@posting.google.com...
> 
> > my static timing analisys looks o.k. (at least the paths that i've
> > constrained). and I realy dont know where to start looking.
> > I checked my design over and over for "bad code" parts but didnt found
> > anything that might explain this.
> 
> What is your background is FPGA design? This might be teaching you to
> suck eggs, but....
> 
> Ideally you want your whole design to be written synchronously
> off one clock. The only constraints you will then need are
> 1 for the clock and for input/output timing.
> 
> If you have ripple/gated clocks the timing analysis tools can't do a
> proper analysis on what's actually going to happen and you're likely
> to have a lot of clock races etc.

I am not sure what you mean about the clocks.  A gated clock, as in
"enabled", is still easy to analyze timing.  This becomes multicycle
which I do all the time.  I am not sure what a ripple clock is, but when
you use multiple clocks, you can specify the timing relationship between
them and the tool will do all the work.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 74889
Subject: Re: Active Rece\onfiguration of Xilinx FPGAs
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 21 Oct 2004 00:15:27 -0400
Links: << >>  << T >>  << A >>
Vic Vadi wrote:
> 
> Hi Kedar,
>                Partial Reconfiguration can definitely be used
> on most Xilinx Virtex Series FPGA's - especially in the latter
> ones. This should be documented under "ICAP Port" in the user
> guide or the chip documentation available at www.xilinx.com.
> 
>             We designed the chips such that sections of your
> chip can remain active as normal while other sections are being
> reconfigured. For more practical experience with actually
> using it - perhaps other members of comp.arch.fpga can
> share their experiences.

The chips have been designed for partial reconfiguration for a very long
time, but the software has not.  My understanding is that both the
Spartan 3 and the Virtex 4 devices are not supported by modular
configuration which is the only practical use of partial configuration
unless you are just trying to compress your bit streams.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 74890
Subject: Webpack 6.3i support for Spartan 3
From: u1000393@email.sjsu.edu (Hendra)
Date: 20 Oct 2004 21:25:50 -0700
Links: << >>  << T >>  << A >>
Hi folks,
I notice that the pull down menu for Webpack 6.3i SP2 indicates it
supports Spartan 3 XC3S2000, 4000 and 4000L. Xilinx website said that
this version of Webpack only supports up to XC3S1500. Is there
something wrong with the software GUI, or is the support for higher
device for real?
Thanks in advance!

Hendra

Article: 74891
Subject: Re: unstable fpga design
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 20 Oct 2004 23:26:39 -0500
Links: << >>  << T >>  << A >>
>I am not sure what you mean about the clocks.  A gated clock, as in
>"enabled", is still easy to analyze timing.  This becomes multicycle
>which I do all the time.  I am not sure what a ripple clock is, but when
>you use multiple clocks, you can specify the timing relationship between
>them and the tool will do all the work.

I think "gated clock" in the ASIC world means a clock made by ANDing
the enable with the clock signal.  Just like we used to do in the
old TTL days when only a few chips had enable pins.  (Worked OK
as long as you ran your normal/main clock through a dummy gate
to keep the clock skew reasonably close.)

They have the advantage of saving the power on the rest of the
clock distribution chain when the clock isn't enabled.

"Ripple clock" probably refers to ripple counters.  You build a
counter out of toggle FFs.  The 0=>1 transition of bit N clocks
bit N+1.  I'd guess it is small but I don't know if it's used
much.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 74892
Subject: Re: Simultaneously Switching Outputs in Spartan-II
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 20 Oct 2004 23:29:02 -0500
Links: << >>  << T >>  << A >>
>I am trying to figure out the pin allocation for a Xilinx Spartan-II
>device in the PQ208 package that is to implement a PCI agent (target
>and master).  ...

There is an interesting discussion of this area for Spartan3 going
on.  Subject is "spartan 3 on 4 layers"  (this newsgroup)

No simple answers though.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 74893
Subject: Re: Async reset
From: u1000393@email.sjsu.edu (Hendra)
Date: 20 Oct 2004 21:58:16 -0700
Links: << >>  << T >>  << A >>
"Jason Berringer" <jberringer@sympatico.ca> wrote 
> Does an async. reset slow down the speed of a circuit? 

I guess synchronous reset need extra logic, so it may speed up a
little if you use asynchronous reset.

> Is it better to use a
> synchronous reset, or if possible no reset at all to speed up a design? 

Yes, it is possible to have no reset at all in an FPGA since FPGA will
automatically clear all FFs inside the chip during downloading from
the bitstream. However, not having the reset will make it harder to
simulate since some simulators require all the FFs to be resetted
before you can do any simulation. Moreover, what would happen when for
some reason your FFs go to undesired state, then you can not get out
of the loop!

There are some articles regarding sync vs async at
http://www.sunburst-design.com/papers/

Hendra

Article: 74894
Subject: Re: Async reset
From: mk<kal@delete.dspia.com>
Date: Thu, 21 Oct 2004 05:20:35 GMT
Links: << >>  << T >>  << A >>
On Wed, 20 Oct 2004 18:41:08 -0400, "Jason Berringer"
<jberringer@sympatico.ca> wrote:

>Hello all,
>
>I have a general question regarding asynchronous and synchronous resets.
>Does an async. reset slow down the speed of a circuit? Is it better to use a
>synchronous reset, or if possible no reset at all to speed up a design? I'm
>just curious as I have a larger project which has a single async reset to a
>lot of different blocks using the typical:
>
>if (reset = '0') then
>...
>elsif (rising_edge(clk)) then
>...
>else
>...
>end if;
>
>Not all block require the reset since they are downstream of earlier ones
>with a reset and their state isn't critical, I have just always included
>them. That being said I want to speed up the design, and in one block I took
>out the reset and it seemed to boost the performance slightly.
>
>Any comments would be appreciated.
>
>Jason
>

For standard cell based designs, flops without async resets are almost
always faster than the ones which do (and they are smaller as an added
bonus), so if you don't need them don't use them. For FPGAs, when
programmed not have an async reset a flop might have a different clk
to Q delay (or a faster setup) which would make the design faster. One
method would be to use async resets only for the registers which you
know would need them and then add the ones later if you have to.
Of course you should never let an async reset reach a flop without
being synchronized to its clock, at least the release of the reset
signal. Not doing so would cause unmentionable heart-ache in a
real-life design.


Article: 74895
Subject: Partial reconfiguration of Xilinx
From: kedarpapte@gmail.com (Kedar P. Apte)
Date: 20 Oct 2004 22:56:03 -0700
Links: << >>  << T >>  << A >>
Hello,

Has anybody used Xilinx Vertex series of FPGAs with partial
reconfiguration option in there designs successfully...?

I need some info about that

thanks in advance 

rgds
Kedar

Article: 74896
Subject: Re: Metastability pipeline causes bad juju
From: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?= <xjohbex@xfoix.se>
Date: Thu, 21 Oct 2004 08:35:04 +0200
Links: << >>  << T >>  << A >>
Symon wrote:

> Johan,
> Yeah, I did a very similar project to you, lots of cascaded DSP blocks. My
> DSP blocks were homespun, so I did initially functionally simulate them
> separately, but not especially thoroughly, while my hardware was being
> built. When the hardware turned up, I mostly used Chipscope to fault find.
> Your point about using a real input source for the blocks is a key advantage
> of Chipscope, especially in computationally intense apps like DSP. Chipscope
> revealed several 'design opportunities' when I tested with real signals,
> that simulation missed because of the limited time and effort available to
> make test vectors.
> Chipscope is also a winner for soft processors. It's easy to use Data2mem to
> upload new code to a BRAM, and debug your code in Chipscope without needing
> a P&R cycle.
> Cheers, Syms.


Good to hear that I'm not the only one using that type of design 
methodology...  =)

Keep on Chipscoping in the free world...

johan

Article: 74897
Subject: Re: Active Rece\onfiguration of Xilinx FPGAs
From: kedarpapte@gmail.com (Kedar P. Apte)
Date: 21 Oct 2004 03:13:50 -0700
Links: << >>  << T >>  << A >>
thanks John

I have subscribed my email for that list let us see 
I need more info on if any body had done partial reconfiguration in
Xilinx when a part of FPGA is already active

So in that details about tools used configuration modes and a bit of
hardware configuration required and finally does it work

Thanks alot for your help I will try and post messeges on that also

Rgds
Kedar

John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<cl7146$9a1$1@bunyip.cc.uq.edu.au>...
> Hi Kedar,
> 
> Kedar P. Apte wrote:
> 
> > I need some practical info on 
> > has any body used Xilinx Vertex series of FPGAs for any project
> > involving active partial reconfiguration
> > 
> > I mean to say that if a part of FPGA is working then can we
> > reconfigure another part of the FPGA and make it work
> 
> There's a Xilinx app note with example design files that walks you 
> through the most basic possible use of partial reconfiguration (xapp 260 
> or 269, something like that).
> 
> A while ago I setup the partial-reconfig mailing list dedicated to this 
> topic.  It's pretty quiet but feel free to join and start asking 
> questions:
> 
> http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/index.html#partial-reconfig
> 
> Regards,
> 
> John

Article: 74898
Subject: interfacing a PC based program with a FPGA
From: srinivaserj@gmail.com (Srinivas)
Date: 21 Oct 2004 04:01:43 -0700
Links: << >>  << T >>  << A >>
Hi,
I'm looking to integrate a FPGA based program into a PC based
application.
I understand i need to write a serial interfacing code on the FPGA
side and an API on the PC side,considering i intend to use a RS 232
serial interface bet'n the PC and the FPGA board.
I need help regarding the PC side API programming.I'll be using a 'C'
program and would like to call the FPGA based functions.
Can anyone suggest how i go about this?any references?

TIA. 
Srinivas

Article: 74899
Subject: Re: simprim errors
From: pruthvi <pruthvi_srireddy@yahoo.com>
Date: Thu, 21 Oct 2004 04:09:09 -0700
Links: << >>  << T >>  << A >>
hi ..
1. create a simprim libraray in ur proj with >>> vlib simprim
2. map simprim to the destination directory >>
  vmap simprim destination.
3. then compile the design.
 >> project compileall
4. then simulate with simprim library and sdf file. 

      > vsim sdffile design file




but prior to step 1 compile all vhdl/verilog source files to simprim library. (this can be differenr project)depending on what backannoneted netlist you generate.

bye



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