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sk wrote: > > Hey > I'm actually designing a comparator circuit > > > |--------feedback resistor------| > | | > | |---------------------| | > RC CIRCUIT ----|------|+ | | > | COMPARATOR CIRCUIT | | > INPUT----------|- |--|---------OUT > |---------------------| > The task is to design this cirucit in such a way that when an input > pulse (0.5,-2.5) with a pulse width of 8micro seconds is given it > should produce me an output which remains high for atleast like > 64micro seconds..i tried using R=2248.5k and C=8500pF and the feedback > resistor i used was 90k..i was able to get an o/p which remains high > for 64microseconds but when looked at it carefuly i was able to figure > out that the outout remained high just beacuse of the large difference > between the resistors(the storage capacitance is not much observed in > the o/p graph)...it should basically work like a monostable > multivibrator (without using ic 555 timer though)...it would be of > great help to me if u could give me some suggestions as how could i do > this.. I'm not sure I understand what you are doing, but if I get it right, your input pulse goes from 0.5 volts to -2.5 volts and 8 uS later returns to 0.5 volts. You want an output pulse starting when the input pulse goes low and lasts for 64 uS. If this is right, I would say you need to swap the feedback resistor with the RC. Actually, you don't need an RC, just a C will do. But this circuit will have all the problems with noise that the 555 timer has and may even be worse since noise on the comparator output can affect your circuit. BTW, where did you get a 2248.5k ohm resistor? What is that, .001% tolerance? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75376
Hi, The best board to quickly develop a gambling machine (but not exclusively this): Merlino Board -> www.seventech.it Its the best alternative to a PC for embedded application. I hope that this can help you. Jezz ".::[ IchiGeki ]::." <nomail@please.com> ha scritto nel messaggio news:3D%hd.251662$35.11845320@news4.tin.it... > Hi there, > > I'm looking for an FPGA board for game and amusement with jamma and cctalk > connector, some ideas? ;) > > Thanx > > >Article: 75377
> http://www.seventech.it > > Merlino Board Gambling Machine Dev Kit (The Dev kit include all the software > tools and C++ demo code, to develop a gambling machine) Very good card but the cost is a little higher than other solutions. So if I pay this board 300 euros (circa) whow much I have to ask to my final customers? ;-) SincerelyArticle: 75378
> The best board to quickly develop a gambling machine (but not exclusively > this): > Merlino Board -> www.seventech.it > Its the best alternative to a PC for embedded application. > I hope that this can help you. Thank you Jazz. About this board, I think this is an hi-performance solution, but the cost is very high for a single board (300 euros) and the SDK 15K!!! Too expensive!!! :-\ Sincerely,Article: 75379
Hello,
I'd appreciate some help on two questions I have relating to the
SRL16E_1 primitive.
Q1. What is the correct instantiation template for the SRL16E_1
primitive in VHDL?
When I synthesise my VHDL code (see end of message) I get the
following warnings:
WARNING:Xst:647 - Input <A0> is never used.
WARNING:Xst:647 - Input <A1> is never used.
WARNING:Xst:647 - Input <A2> is never used.
WARNING:Xst:647 - Input <A3> is never used.
WARNING:Xst:79 - Model 'SRL16E_1' has different characteristics in
destination library
WARNING:Xst:80 - Model name has been changed to 'SRL16E_11'
When I change the instantiated component name to SRL16E_11 I no longer
get the warnings but I get errors at ngdbuild like the following:
ERROR:NgdBuild:604 - logical block 'cell6' with type 'SRL16E_11' could
not be resolved. A pin name misspelling can cause this, a missing edif
or ngc file,
or the misspelling of a type name. Symbol 'SRL16E_11' is not supported
in
target 'virtex2'.
Q2. How do I find minimum period between the SRL16 clock and capturing
the resulting Q in the flip-flop?
Eric.
ps I am using ISE 6.1.03i and XST.
library ieee;
use ieee.std_logic_1164.all;
entity ten_srl16s is
port(
Clock : in std_logic;
CE : in std_logic;
NewContent : in std_logic_vector (9 downto 0);
Stimulus : in std_logic_vector(3 downto 0);
Output : out std_logic_vector(9 downto 0)
);
end ten_srl16s;
architecture structure of ten_srl16s is
signal tempoutput : std_logic_vector(9 downto 0);
component SRL16E_1
port (Q : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
-- Instantiate the 10 srl16s
instantiatesrl16s: for i in 0 to 9 generate
cell : SRL16E_1 port map(Q=>tempoutput(i),
A0=>stimulus(0),
A1=>stimulus(1),
A2=>stimulus(2),
A3=>stimulus(3),
CE=>CE,
C=>Clock,
D=>newcontent(i)
);
end generate;
process(Clock)
variable answer : std_logic_vector(9 downto 0);
begin
Output<=answer;
if (Clock'event) and (Clock='0') then
answer:=tempoutput;
end if;
end process;
end structure;
Article: 75380Jim, The configuration logic is such that the device only starts up if all the data is loaded correctly. In the case I mentioned, all the data is loaded correctly, the CRC check at the end of configuration is succesful, and the device starts up, meaning internal nodes are released from 3-state. When you mistakenly load a bitstream targeted to another device for the architectures I mentioned before, the device will start up, but the mistargeted configuration could set internal nodes into a contention state, possibly destroying the device. In your case, if the device is properly targeted, only the correct data will enable the device to start up (otherwise the CRC will fail), which means no damage will occur. You will see evidence of a failed configuration with DONE being low and INIT being low as well. HTH, Mike Jim Lewis wrote: > Mike, > >> One way to blow up a device is to try to download a bitstream that is >> targeted to a different device, like loading a 2s50 bitstream into a >> 2s200 part. Here's the link: >> >> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=8436 >> >> >> Not that likely in a strict design environment, but I could see it >> happening quite often in a classroom setting. Notice this is no >> longer an issue for Virtex-II(Spartan-3) and later devices. > > > Can the same thing happen if I use the correct device, but the > device does not successfully program? I have a particularly > high programming failure rate with XST 6.2.02i. The parallel > port programming cable is thin and it is right next to the > power cord on the laptop, so there may be some noise issues. > > Regards, > Jim -- -- -- Please ignore the reply to address, and use -- mike -dot- peattie -at- xilinx -dot- com --Article: 75381
Hi .
Me along with my Professor at Clemson University are planning to
have a new FPGA board for implementing sensor networks with FPGA's
...So can anyone suggest me that we could buy and then implement our
designs on that ..I prefer to have Xilinx FPGA's because I am more
familiar with Modelsim and ISE ...
Article: 75382vax, 9000, Cool Results. For some reason the synthesis tool got lost. Some devices do not have an asynchronus set. Hence, they implement it with an asynchronous load and '1' on the data lines when asynchronous set is specified. However, if this was truely the case, then why not simplify the PRE input and not use the CLR input. Perhaps there is a bug in the synthesis part library. Are you sure you really want an asynchronous load. Typically I only do asynchronous set and clears. All normal functionality is synchronous to clock. Cheers, Jim > Hi group, > When I am developing code for a hobby project, I find that XILINX webpack > infers unnecessary MUX. I suspect that the MUX eats resource so I'd like to > remove it to pack more function into the XC95144XL target. > I am using the version 6.1. > Here is the sample code (complete and compiles) and the synthesized > schematic is posted at > <http://geocities.com/mscpscsi/PHOTOS/CPLD_VHDL.jpg>. I think ADDR_NEXT can > be connected to D only and HOST_DATA can be connected to pre-set/clr only. > Any idea? Thanks. > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > entity busmaster is > Port ( > ADDR: out std_logic_vector(7 downto 0); > ADDR_CLK_I: in std_logic; > ADDR_NEXT: in std_logic_vector(7 downto 0); > HOST_DATA: in std_logic_vector(7 downto 0); > HOST_CSWR: in std_logic > ); > end busmaster; > architecture Behavioral of busmaster is > begin > ADDR_UPDATE: process (HOST_DATA,HOST_CSWR,ADDR_CLK_I) > begin -- process > if HOST_CSWR = '0' then > ADDR <= HOST_DATA; > elsif ADDR_CLK_I'event and ADDR_CLK_I = '1' then > ADDR <= ADDR_NEXT; > end if; > end process; > end Behavioral; > > > --VAX, 9000 > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 75383
Parag wrote: > Me along with my Professor at Clemson University are planning to > have a new FPGA board for implementing sensor networks with FPGA's > ...So can anyone suggest me that we could buy and then implement our > designs on that ..I prefer to have Xilinx FPGA's because I am more > familiar with Modelsim and ISE ... Suzaku is pretty cute: http://www.atmark-techno.com/en/product/suzaku.html Tiny form factor, ethernet connectivity, reasonable number of free user IO. Best of all, it's preconfigured with microblaze uClinux ;-) Cheers, JohnArticle: 75384
On Wed, 03 Nov 2004 19:08:22 -0500, Parag <pbeerak@clemson.edu> wrote: >Hi . > Me along with my Professor at Clemson University are planning to > have a new FPGA board for implementing sensor networks with FPGA's > ...So can anyone suggest me that we could buy and then implement our > designs on that ..I prefer to have Xilinx FPGA's because I am more > familiar with Modelsim and ISE ... A couple of places that I've used: http://www.fpga4fun.com/ http://www.digilentinc.com/ and there's a long list of others at: http://www.fpga-faq.com/FPGA_Boards.shtml -- Rich Webb Norfolk, VAArticle: 75385
> Me along with my Professor at Clemson University are planning to > have a new FPGA board for implementing sensor networks with FPGA's > ...So can anyone suggest me that we could buy and then implement our > designs on that ..I prefer to have Xilinx FPGA's because I am more > familiar with Modelsim and ISE ... What's a "sensor network"? How much are you willing to spend? How much network bandwidth do you need? How big/fast of an FPGA do you need? Need memory? CPU? The Xilinx Spartan3 starter kit is a nice package for $100. It doesn't have an Ethernet, but you can add one for $60. (Look at the Digilent web site.) It does have a RS232 port. For $60 you can get an Analog card with an 8 bit A/D and 2 channels of 8 bit D/A and a couple of op-amps and a breadboard area. The FAQ has a list of FPGA boards. Worth browsing to get a calibration on what's available. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 75386
"Nitro" <nitro-57@no_spam_please_usa.net> wrote in message news:<avgebabfcnzcyrnfrhfnarg.i6l7qq0.pminews@news.randori.com>... > I am Not sure at what level you are looking but the Xilinx site > (http://www.xilinx.com) has a few on-line tutorials. If you are near Texas I > noticed a free CPLD intor class with developer kit at one of the local > distributors. Yeah, there in fact a handbook on there site http://www.xilinx.com/publications/products/cpld/logic_handbook.pdf, which I already have. Book is all about FPGA implementation, which is definitely not my purpose. I need to know how it actually works.Article: 75387
rickman <spamgoeshere4@yahoo.com> wrote > Falk Salewski wrote: > > > > Didn't know about flash based FPGAs before. Maybe it's something to think > > about. > > Thanks for your reply! > > The ones I have seen are actually SRAM FPGAs with an automatic loader > from on-chip flash. This loads much faster than an external flash > would, but otherwise the process is the same. As far as I know, are Actel ProAsic Plus not SRAM-Cells with on-chip flash. Of course there are SRAM-Cells for embedded RAM, but the logic itself seems to be stored in flash technology. The only fpga I unterstood using SRAM-logic with on-chip flash are lattice Fpgas. But feel free to correct me, I like to learn something new :=). bye ThomasArticle: 75388
"Jim Lewis" <Jim@SynthWorks.com> wrote in message news:10oj0c074aip4ac@corp.supernews.com... > vax, 9000, > Cool Results. For some reason the synthesis tool got > lost. > > Some devices do not have an asynchronus set. Hence, they > implement it with an asynchronous load and '1' on > the data lines when asynchronous set is specified. > However, if this was truely the case, then why not simplify > the PRE input and not use the CLR input. Perhaps there > is a bug in the synthesis part library. > > Are you sure you really want an asynchronous load. > Typically I only do asynchronous set and clears. > All normal functionality is synchronous to clock. > > Cheers, > Jim > > > > Hi group, > > When I am developing code for a hobby project, I find that XILINX webpack > > infers unnecessary MUX. I suspect that the MUX eats resource so I'd like to > > remove it to pack more function into the XC95144XL target. > > I am using the version 6.1. > > Here is the sample code (complete and compiles) and the synthesized > > schematic is posted at > > <http://geocities.com/mscpscsi/PHOTOS/CPLD_VHDL.jpg>. I think ADDR_NEXT can > > be connected to D only and HOST_DATA can be connected to pre-set/clr only. > > Any idea? Thanks. > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity busmaster is > > Port ( > > ADDR: out std_logic_vector(7 downto 0); > > ADDR_CLK_I: in std_logic; > > ADDR_NEXT: in std_logic_vector(7 downto 0); > > HOST_DATA: in std_logic_vector(7 downto 0); > > HOST_CSWR: in std_logic > > ); > > end busmaster; > > architecture Behavioral of busmaster is > > begin > > ADDR_UPDATE: process (HOST_DATA,HOST_CSWR,ADDR_CLK_I) > > begin -- process > > if HOST_CSWR = '0' then > > ADDR <= HOST_DATA; > > elsif ADDR_CLK_I'event and ADDR_CLK_I = '1' then > > ADDR <= ADDR_NEXT; > > end if; > > end process; > > end Behavioral; > > > > > > --VAX, 9000 As an experiment, what happens if you take HOST_DATA out of the sensitivity list? For a standard clocked process template I'd only expect to see asynchronous control signals and the clock in the sensitivity list, e.g. addr_update:process(host_cswr, addr_clk_i) begin ... regards Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 75389
Hi there! Quick question. Is anyone using the Nios II IDE (Quartus II Software version 4.1 by Altera)? If so, I'm having difficulties in how to include certain header files, e.g. socket.h and so on when using the C/C++ editor. Is there an option, I can select which tells the IDE where to find those header files? In the installation directory of Quartus I've already spotted lot's of these .h files, problem is the IDE obviously doesn't know that :-( A workaround that I've found is to include those files manualy in my project using File -> Import, but in a larger project where header files depend on other header files, this becomes very time consuming and therefore doesn't seem to be a very smart solution. I've also tried right click on the root directory of the project -> System Library Properties -> C/C++ Build -> Include Paths, and entered the path where my needed headers are located, but to no avail. Any hints or solutions are greatly appreciated, because a site search at Altera wasn't very enlightning for me either. regards, Chris.Article: 75390
In article <cmb8rh$buc$1@charm.magnus.acs.ohio-state.edu>, vax9000 @gmail.com says... > Hi group, > When I am developing code for a hobby project, I find that XILINX webpack > infers unnecessary MUX. I suspect that the MUX eats resource so I'd like to > remove it to pack more function into the XC95144XL target. > I am using the version 6.1. > Here is the sample code (complete and compiles) and the synthesized > schematic is posted at > <http://geocities.com/mscpscsi/PHOTOS/CPLD_VHDL.jpg>. I think ADDR_NEXT can > be connected to D only and HOST_DATA can be connected to pre-set/clr only. > Any idea? Thanks. > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > entity busmaster is > Port ( > ADDR: out std_logic_vector(7 downto 0); > ADDR_CLK_I: in std_logic; > ADDR_NEXT: in std_logic_vector(7 downto 0); > HOST_DATA: in std_logic_vector(7 downto 0); > HOST_CSWR: in std_logic > ); > end busmaster; > architecture Behavioral of busmaster is > begin > ADDR_UPDATE: process (HOST_DATA,HOST_CSWR,ADDR_CLK_I) > begin -- process > if HOST_CSWR = '0' then > ADDR <= HOST_DATA; > elsif ADDR_CLK_I'event and ADDR_CLK_I = '1' then > ADDR <= ADDR_NEXT; > end if; > end process; > end Behavioral; > > > --VAX, 9000 > > This is an error I tried to tell Xilinx a long time ago. My FAE told me it will be fixed in version 7.1. In the mean time you have to infer a FDCP primitive and attach your signals directly to the inputs. Best regards Klaus FalserArticle: 75391
The price that I have known is different. For SDK, we have a agreement that diverts the dev kit cost from the production boards cost. I don't know if this is a reserved information, you should directly contact Seventech and .....to bargain over. Jezz ".::[ IchiGeki ]::." <nomail@please.com> ha scritto nel messaggio news:Wvcid.121987$b5.6040102@news3.tin.it... >> The best board to quickly develop a gambling machine (but not exclusively >> this): >> Merlino Board -> www.seventech.it >> Its the best alternative to a PC for embedded application. >> I hope that this can help you. > > Thank you Jazz. About this board, I think this is an hi-performance > solution, but the cost is very high for a single board (300 euros) and the > SDK 15K!!! Too expensive!!! :-\ > > Sincerely, > > >Article: 75392
Eric, Q1: I think you are missing the two lines below: Library UNISIM; use unisim.vcomponents.all; Then, I don't think you need to declare the component. Clean the project files and that should solve the error. Q2:The timing report will tell you this. You can as well use the timing analyser. Suggestion: You can use the primitive SRLC16E_1. it instantiate a SRL16 followed by a FF in the same CLB. Anyway, I think the tool is clever enough to place your FF in the same CLB Hope this helps. Vincent. Eric wrote: > Hello, > > I'd appreciate some help on two questions I have relating to the > SRL16E_1 primitive. > > Q1. What is the correct instantiation template for the SRL16E_1 > primitive in VHDL? > > When I synthesise my VHDL code (see end of message) I get the > following warnings: > > WARNING:Xst:647 - Input <A0> is never used. > WARNING:Xst:647 - Input <A1> is never used. > WARNING:Xst:647 - Input <A2> is never used. > WARNING:Xst:647 - Input <A3> is never used. > WARNING:Xst:79 - Model 'SRL16E_1' has different characteristics in > destination library > WARNING:Xst:80 - Model name has been changed to 'SRL16E_11' > > When I change the instantiated component name to SRL16E_11 I no longer > get the warnings but I get errors at ngdbuild like the following: > > ERROR:NgdBuild:604 - logical block 'cell6' with type 'SRL16E_11' could > not be resolved. A pin name misspelling can cause this, a missing edif > or ngc file, > or the misspelling of a type name. Symbol 'SRL16E_11' is not supported > in > target 'virtex2'. > > Q2. How do I find minimum period between the SRL16 clock and capturing > the resulting Q in the flip-flop? > > Eric. > ps I am using ISE 6.1.03i and XST. > > library ieee; > use ieee.std_logic_1164.all; > > entity ten_srl16s is > port( > Clock : in std_logic; > CE : in std_logic; > NewContent : in std_logic_vector (9 downto 0); > Stimulus : in std_logic_vector(3 downto 0); > Output : out std_logic_vector(9 downto 0) > ); > end ten_srl16s; > > architecture structure of ten_srl16s is > signal tempoutput : std_logic_vector(9 downto 0); > > component SRL16E_1 > port (Q : out STD_ULOGIC; > A0 : in STD_ULOGIC; > A1 : in STD_ULOGIC; > A2 : in STD_ULOGIC; > A3 : in STD_ULOGIC; > CE : in STD_ULOGIC; > C : in STD_ULOGIC; > D : in STD_ULOGIC > ); > end component; > > begin > -- Instantiate the 10 srl16s > instantiatesrl16s: for i in 0 to 9 generate > cell : SRL16E_1 port map(Q=>tempoutput(i), > A0=>stimulus(0), > A1=>stimulus(1), > A2=>stimulus(2), > A3=>stimulus(3), > CE=>CE, > C=>Clock, > D=>newcontent(i) > ); > end generate; > > process(Clock) > variable answer : std_logic_vector(9 downto 0); > begin > Output<=answer; > if (Clock'event) and (Clock='0') then > answer:=tempoutput; > end if; > end process; > > end structure;Article: 75393
> I don't know if this is a reserved information, you should directly contact > Seventech and .....to bargain over. I contacted Seventech and the board cost is 300 euros per piece, 15000 euros for the SDK. Sincerely,Article: 75394
I want to use XC3S2000, but appearantly they are only available as engineering samples til Feb 05. What aspect of these parts does not meet spec? Is it well defined enough that careful design would still let me ship Eng. Samp. in a finished product? Thanks.Article: 75395
Hi, I'm facing a stange behaviour of the PLB-IPIF interface and I would like an advice about it. I've designed my own plb bus master wich loads data from a sram connected to an opb-emc unit. The plb and opb bus are connected through a bridge. The plb bus is 64 bit (double word) and the opb and sram are 32 bits (word). I need to perform variable burst length (because it depends on my data) and I have a very strange problem. When the burst length is 9, it seems that the burst is transformed to two 16 word sram accesses. This behaviour is correct (described in documents) but when I perform a second 9 double word burst, the two are messed !! Indeed, the IPIF signals a complete transfert when the 9 double words are loaded but the second 16 word sram access is still in progress. The second 9 double word burst is messed with the previous unfinished sram accesses !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! There are no error signals and so on.... Is it a bug or did I missed something ? Is this corrected in new versions ? (I'm using ISE-62i and edk 6.2) What sould I do ? Thanks a lot StephaneArticle: 75396
Thomas, Soon there will appear (I just reviewed it) a Tech Xclusive on failure rates, both soft and hard. Bottom line, is that 4/5ths of the failures (or more) of any typical system are hardware failures (solder, connectors, capacitor shorts, etc.) as opposed to soft errors induced by cosmic rays (example here was a complete cellular base station with ten 2VP100's! radios and all). Additionally, there are three known ways to eliminate soft errors as a cause of functional failures, so you had better worry about the 'real' problem, and not chase red herrings (where in the world does that colloquialism come from?). Just keep checking: http://tinyurl.com/4uks8 the article should be posted in a week or so. Austin Thomas Stanka wrote: > "Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote: > >>I am interested in safety for embedded applications. So I read this articels >>dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 >>with great interest. >> >>People listed a lot of advantages of FPGAs, however the major problem >>(related to safety) left was that the FPGA has to be reprogrammed at each >>power up. >> >>My question: isn't an CPLD a good solution for small safety critical >>applications? > > > What principle advantage do you think to gain with an CPLD over an > FPGA? > If you think about a flash based CPLD, why not using a flash based > FPGA? > > A lot of Hi-Rel applications use fuse-based fpgas which are (almost) > immune against functional changes after programming and are ready to > start after power-up. So you end nearly in a safety level you reach > with asics. > > bye ThomasArticle: 75397
What you need to do is flatten your code. Remove the hierarchy in your object structure. I've compiled huge designes that were entirely flattened, i.e., only one object -- the top level object. I've compiled for 37k slices by doing that, though you're still 10k above me. The tools seem to run out of memory much faster if you have a steep hiearchy, i.e., you try to do something normal like reuse code. The other thing you can do is instatiate your primitives manually. Declare all your multiplier and RAM primitives instead of using the inferred objects. It doesn't appear to me that the Xilinx tools ever use more than 2GB of RAM on a 32bit system. I think that is normal. It's possible that is all a process can get access to. However, if you could get your hands on a 64bit system.... "Eric" <swankoski@nrl.navy.mil> wrote in message news:84d8efa2.0411020557.78be0f2e@posting.google.com... > OK, so I'm trying to synthesize a huge design. Just for quick > reference, the inferred macros are below: > > HDL Synthesis Report > > Macro Statistics > # Block RAMs : 112 > 16x24-bit dual-port block RAM : 64 > 1024x12-bit single-port block RAM : 48 > # ROMs : 3 > 16x10-bit ROM : 3 > # Multipliers : 480 > 12x12-bit registered multiplier : 480 > # Adders/Subtractors : 3856 > 10-bit adder : 20 > 8-bit adder : 32 > 9-bit adder : 16 > 7-bit adder : 16 > 12-bit adder : 1792 > 24-bit adder : 480 > 12-bit subtractor : 1472 > 4-bit subtractor : 15 > 5-bit adder : 1 > 4-bit adder : 12 > # Counters : 1 > 5-bit up counter : 1 > # Registers : 13434 > 4-bit register : 30 > 24-bit register : 577 > 12-bit register : 480 > 10-bit register : 20 > 5-bit register : 1 > 1-bit register : 12325 > 3-bit register : 1 > # Comparators : 44 > 10-bit comparator greatequal : 12 > 5-bit comparator lessequal : 2 > 5-bit comparator greater : 2 > 10-bit comparator greater : 7 > 10-bit comparator less : 11 > 10-bit comparator lessequal : 8 > 5-bit comparator greatequal : 1 > 5-bit comparator less : 1 > # Multiplexers : 1070 > 4-bit 2-to-1 multiplexer : 10 > 1-bit 2-to-1 multiplexer : 2 > 12-bit 2-to-1 multiplexer : 1040 > 24-bit 2-to-1 multiplexer : 1 > 24-bit 64-to-1 multiplexer : 1 > 24-bit 16-to-1 multiplexer : 16 > # Xors : 480 > 1-bit xor2 : 480 > > The code is fairly well-optimized and functionally correct. However, > it is a huge design, and it should be about 47,000 SLICEs once all is > said and done. But, alas: > > "ERROR: Portability:3 - This Xilinx application has run out of memory > or has encountered a memory conflict..." > > I'm sure plenty of you have gotten this error before. On a machine > with 2.5 GB of memory and dual 3.0 GHz processors, should I be getting > this error? I've been working on optimizing my code but I was > wondering if there is a point where the design is simply too large.Article: 75398
Buzz, We define an engineering sample as a part that has not been 'fully qualified' for production. That can include things as trivial as the final marking, or the results of the high temperature operating life burn-in (which may be already done on other parts in the same family). ES also means that the production test coverage may not be as high as we target for production. We will tell you what we know, but obviously, we can not tell you what we do not know. The speeds files are also in an early stage, and we have had to base them off foundry models, as we have not seen all of the corners of the process yet. Given Spartan 3 has shipped more than 1 million + units, that is probably not an issue for your part. Early in a product, the ES markings may also mean that there is a published errata describing any known defects associated with the units. Always check to see if there is an errata associated with the ES part. Shipping an engineering sample in a finished product is a business decision on your part, and I can not really comment on that. Others may also not want to comment, as competitive pressures may have forced them to ship ES parts in a 'production' system. The risk is yours to decide. We will let you know where we are in the process for a particular part. Contact your Xilinx FAE. Austin buzz wrote: > I want to use XC3S2000, but appearantly they are only available as > engineering samples til Feb 05. > > What aspect of these parts does not meet spec? > Is it well defined enough that careful design would still let me ship > Eng. Samp. in a finished product? > > Thanks. >Article: 75399
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity srltest is port( clk : in std_logic; q : out std_logic ); end srltest; architecture Behavioral of srltest is -- Component Attribute specification for SRL16 -- should be placed after architecture declaration but -- before the begin keyword component SRL16 port ( Q : out std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; CLK : in std_logic; D : in std_logic); end component; -- Enter attributes here. -- This is the data or pattern that gets circulated around. -- If the number of bits in the rotation cycle is less than 16, -- it will be the least significant bits (the rightmost bits) -- that get circulated. -- This example "0340" translates to binary 0000 0011 0100 0000 -- Only the 11 0100 0000 bits circulate in the 10 bit cycle below. attribute init: string ; attribute init of SRL16_INSTANCE_NAME: label is "0340"; signal feedback : std_logic; begin -- Component Instantiation for SRL16 is placed -- in architecture after the begin keyword. -- SRL16 Circulating Bit Pattern Instantiation -- The A inputs determine how many bits cycle around. -- The number of bits is one more than the A input. -- The maximum is 16 bits; the minimum is 1 bit. -- In this case shown below, there will be 10 bits. SRL16_INSTANCE_NAME : SRL16 port map ( Q => feedback, A0 => '1', -- * 1 bit = 1 A1 => '0', -- * 2 bits = 0 A2 => '0', -- * 4 bits = 0 A3 => '1', -- * 8 bits = 8 so we get 1+0+0+8+1=10 bits CLK => clk, D => feedback ); -- generate an output pad q <= feedback; end Behavioral;
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