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Messages from 75475

Article: 75475
Subject: Re: what's the scenario out there
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sun, 07 Nov 2004 00:10:01 -0800
Links: << >>  << T >>  << A >>
ram wrote:
> Howz the FPGA market doing now, is there any hiring going on in the
> market for coding and developing.

Consider reading monster.com.
Not many hiring managers read this group.

> My perceptive is industry is now
> seeking individuals with more experience 

Always has.

> So what would be a choice for a fresh graduate , how his outlook
> should be. If this choice of hiring( experienced ) continues, what
> sort of training the fresh graduate has to undertake him/herself to
> break the ice.

Get experienced.
The truly interested,
are already doing their own
projects because they enjoy it.

> The current situation forces many B.S students to seek M.S and M.S
> degree holders to seek Ph.d's. Will this not disturb the balance??

It might disturb the balance for university professors.

Figure out what *you* want to do, and get started.
Sometimes the boss doesn't know what
he wants until he sees it.

        -- Mike Treseler



Article: 75476
Subject: Re: minimum module name length in 6.3i?
From: moti@terasync.net (Moti Cohen)
Date: 7 Nov 2004 00:54:02 -0800
Links: << >>  << T >>  << A >>
"RobJ" <rsefton@abc.net> wrote in message news:<2v22uiF2e5cfmU1@uni-berlin.de>...
> "Chris Stratton" <cs_posting@hotmail.com> wrote in message 
> news:ae2ff5ca.0411050655.5f5c0d91@posting.google.com...
> >
> > Have you tried other three letter combinations?  Could it be a
> > reserved word problem rather than a minimum length one?
> 
> No, I didn't think of that. Changing from 'adc' to 'adc1' fixed it, but I 
> ended up calling it 'adc_if'. I kind of doubt it's a reserved word problem 
> because it did pull the module into the project. It just put it in the wrong 
> place. I'll open a case with Xilinx when I get a minute.
> 
> Rob

Just a wild guess, I experienced a similar problem when I used the
xilinx core generator. it went like this - I created a XCO module
using the core-gen tool and inserted it to the project. afterwards
when I wanted to create a new project I copied all the files from the
old project but insted of taking the xco file I took the .vhd file
(that was also generated by the core gen tool) and attached it to the
project instead of the .XCO - then the project view gave me the
picture you described. So maybe if you are using core gen modules you
can check out this option...

Regards, Moti.

Article: 75477
Subject: Mixed RTL ,XILINX EDK
From: mmkumar@gmail.com (mack)
Date: 7 Nov 2004 01:56:13 -0800
Links: << >>  << T >>  << A >>
Hi,
  I want to add my peripheral(which has both VHDL and Verilog design
files) into xilinx MB system.I am using XILINX 6.3 currently.I went
thru CREATE/IMPORT PERIPHERAL WIZARD.There in no option available
there to mention that my design has both VHDL and Verilog.But I could
succesfully add my peripheral(rtls) thru the peripheral wizard.But the
pcore/<design_top>/HDL/VHDL is only created and all my verilog RTLs
are present in VHDL folder only.When i generated bitstream ,it gave me
error saying that"fle not found in repository" ../hdl/vhdl/abc.vhd"
.But abc component is my verilg module.Kindly help me out in this...

Regards,
Mack..

Article: 75478
Subject: Re: chipscope pro problem (par)
From: "Yttrium" <Yttrium@pandora.be>
Date: Sun, 07 Nov 2004 10:06:24 GMT
Links: << >>  << T >>  << A >>
thanks for the link, i'm checking it out right now ... thx...

"Daniel Leu" <daniel.leu@gmail.com> wrote in message
news:1099700135.775503.19790@c13g2000cwb.googlegroups.com...
> > As of CS vs SignalTap vs Identify - all are good tools, but I wish
> there
> > would be something better. Something that is cross platform and more
> open in
> > design - ChipScope doesnt not provide option for low clock or clock
> enable,
> > or and well my wishlist is long. So long it might be easier todo by
> itself
> > then attempting to use existing tools.
> >
> > Antti
>
> Did you check out DiaLite from Temento Systems (www.temento.com)?
> /daniel
>



Article: 75479
Subject: Fifo problem in Cyclone devices
From: tal_h@elbit.co.il (tal_h)
Date: 7 Nov 2004 02:37:15 -0800
Links: << >>  << T >>  << A >>
Hi,

I had implemented an interface between two processors with a dc-fifo
in Cyclone device.
the mechanism is P#1 (processor) writes a packet, signals the FPGA, 
the FPGA signals to P#2 for reading, P#2 reads the packet, signals the
FPGA it finished reading. than the FPGA signals P#1 that it can writes
a new packet.
every packet is 64 words size.
I perform a test of transmitting a known constant packet (a decreasing
number). the test is fine but 1 100,000 packets is wrong.
I thought it is a timing problem. but when I check in P#2 what packet
was wrong, I found out that the packet is built by an INCREASING
number until some point and then: decreasing number as it should be
(in the appropriate place).

I figure it is connected to the FIFO implementation.....

Does someone hear about problems in Cyclone FIFO's?

thanks,

tal

Article: 75480
Subject: Re: Mixed RTL ,XILINX EDK
From: "Antti Lukats" <antti@case2000.com>
Date: Sun, 7 Nov 2004 11:40:41 +0100
Links: << >>  << T >>  << A >>
"mack" <mmkumar@gmail.com> wrote in message
news:aba94305.0411070156.5833f7fa@posting.google.com...
> Hi,
>   I want to add my peripheral(which has both VHDL and Verilog design

welcome abroad!

the mixed verilog-vhdl designs with EDK is the biggest problem with EDK that
ASFAIK is not fully solved.

1) using any import wizard is most likely not possible at all

2) if you write your own IP core (not using import wizard) you can specify
"BOTH" as synthesis language, this does not mean you can mix verilog and
vhdl in single edk ip core, it means you must supply BOTH verilog and VHDL
versions!!

3) if you need parts (of same EDK ip core) to be verilog and part VHDL you
need to create 2 Cores

one would be visible in the EDK/XPS the other one not, the visible one
refers to the other one, so I would say the visible one should be VHDL as
most of EDK cores are in VHDL, the other one in verilog, for both core
packages you specidy one HDL language in the MPD file not BOTH!

several EDK supplied cores are actually made with this approuch:

opb_emc_v1_10.b  - this is the "visible" part that references the
emc_common  - the invisible part

in your case you need as example
opb_mycore - in VHDL
mycore_common - verilog

The above approuch is the only way that might work! or ok you can use 3rd
party synthesis tools or command line scripts to perform synthesis outside
the EDK toolchain, that another option

Antti













Article: 75481
Subject: Re: Epp interface with Cyclone
From: "Victor Schutte" <victors@mweb.co.za>
Date: Sun, 7 Nov 2004 14:32:44 +0200
Links: << >>  << T >>  << A >>
Use a simple counter, in this case a single D-Type Flip Flop.You don't need
a PLL if you need sub factors or the main clock.

Victor
http://www.zertec.co.za



"Michele Bergo" <michelebergo@libero.it> wrote in message
news:%ORid.18871$Ni.665341@twister1.libero.it...
> I want to realize an EPP interface using Altera FPGA Cyclone (read and
write
> operation) but I have some synchronization problems. I want to sample
datas
> from a 4 bits chip,  storing them in a ZBT SRAM memory (Flow trought) and
> later acquiring them by parallel port. the chip works at 10MHz but the pll
> on board can't divide input clock of 20MHz for 2. How can I divide the
> frequency?
> thanks.  Does anyone do something like that?
>
>



Article: 75482
Subject: Re: chipscope pro problem (par)
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sun, 07 Nov 2004 07:10:10 -0800
Links: << >>  << T >>  << A >>
Antti Lukats wrote:

> Sure it is possible to do it all without the use of any OnChipInstrumentation
> tools at all.
   . . .
> But if you work with external ASIC PHY test chips without even having proper
> timing specs for those or in case the latency specs for the external phy
> chips are wrong, then well you just cant simulate what you do not know
   ...
> Attaching
> ChipScope makes that all visible, you see the problem and you can write ip
> cores that take care of that, or if you want can write simulation models
> that the real behavior into account.

Yes, specifying and modeling the interface is very important.
But this is a job best done by the vendor of the chip.

I agree that logic design and simulation are useless
until all interfaces are specified. I also understand
that instrumentation of some sort is required for this
task by the person doing it. But this alone
does not validate the design on *my* side of the
interface nor does it allow me to specify or model
my design for use by others.

> Sure there are many very
> serious project that can be completed very succesfully without ever using
> OCI.

Using devices from vendors who supply full
timing specs and simulation models makes it possible.

> As of CS vs SignalTap vs Identify - all are good tools, but I wish there
> would be something better. Something that is cross platform and more open in
> design.

HDL simulation is like that.

          -- Mike Treseler

Article: 75483
Subject: Re: Fifo problem in Cyclone devices
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sun, 07 Nov 2004 07:38:54 -0800
Links: << >>  << T >>  << A >>
tal_h wrote:

> I perform a test of transmitting a known constant packet (a decreasing
> number). the test is fine but 1 100,000 packets is wrong.

Sounds like a logic race.

> I thought it is a timing problem. but when I check in P#2 what packet
> was wrong, I found out that the packet is built by an INCREASING
> number until some point and then: decreasing number as it should be
> (in the appropriate place).

I think it is a timing problem.
Could be an unsynchronized empty/full flag.
Check all inputs for synchronization to the system clock
and run a static timing analysis.
> 
> I figure it is connected to the FIFO implementation.....
> Does someone hear about problems in Cyclone FIFO's?

Single clock fifos are fully synchronized.
Dual clock fifos assume that you
are doing any required synchronization yourself.

         -- Mike Treseler



Article: 75484
Subject: Re: the compactflash true ide mode access
From: cs_posting@hotmail.com (Chris Stratton)
Date: 7 Nov 2004 08:05:49 -0800
Links: << >>  << T >>  << A >>
"NoThisRAT" <nothisrat@yahoo.com> wrote in message news:<cmifuj$2oel$1@mail.cn99.com>...
> Hi, friends,
>   I wrote a module to access the compactflash in true ide mode (pio0), the
> status register. the clock frequence is 50Mhz, every time I try to read, I
> got 0x54 from the cf_data, I think I should get 0x50 if it works right. What
> is wrong with me??

I don't know for sure that anything is wrong here, 0x54 means it's not
busy, seek is complete, and it's ready to talk.  Having the DRQ on -
the four - doesn't seem like a problem to me, though I just modified
my project to check and I'm finding that the actual IDE disk I'm using
powers on to report 0x80 and then 0x50 when no commands have yet been
sent. Have you tried sending it commands?   Identify is a simple one,
otherwise set up a read command.  You may need to select the device
first with a write to the head register though.

Did you reset it?

Chris

Article: 75485
Subject: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have tool
From: "Antti Lukats" <antti@case2000.com>
Date: Sun, 7 Nov 2004 17:33:45 +0100
Links: << >>  << T >>  << A >>
Hello,

I possible should shut up already, but sometimes I just cant :) - ChipScope
Pro is a *MUST* have thing ! ! !

I did take some time and prepared special webpage with ChipScope Pro
screenshot explaing one situation where it would not been possible to achive
the goal (100% working Serial ATA OOB detector with RocketIO) without the
use of ChipScope Pro.

http://xilinx.openchip.org/ChipScope/

Xilinx, anyone who can explain why rocketIO sees a "pseudo-random pattern"
(as in the screenshot on the webpage above) I would like to hear it, but so
long I see no other options as to look itself (with ChipScope).

There can be many different situations where "things happen" inside FPGA,
things that you just need to visualize.

Quating Mike Teseler: "use devices from vendors that supply full timing
specs.." - that is not always possible. Not only timing specs can be wrong,
also the actual behaviour can be completly unexpected. Also when using first
silicon dies of an packaged ASIC macrocell from the vendor who has not
tested that silicon run itself, then there can be no proper timing specs at
all.

Antti

http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=3851381123



Article: 75486
Subject: SpartanII + ARM7 Question
From: "Patrick Gao" <foolboylei@vip.sina.com>
Date: Mon, 8 Nov 2004 00:36:44 +0800
Links: << >>  << T >>  << A >>
Hello,

I am doing a project to build a system to receive GPS signals.

I selected a Baseband Processor Zarlink GP4020 which has a ARM7TDMI core
embened inside it.

Now I want to add a FPGA(SpartanII XC2S200) to assist it in some arithmatic
computation. And I want to use a Dual Port SRAM to store the temporary data
and make the main processor and the FPGA communicate with each other.

My question is : In what way can this two chip synchronize the process with
each other? (maybe about timing and signal exchange)


Thank you

Regards
Patrick



Article: 75487
Subject: Re: Epp interface with Cyclone
From: "Michele Bergo" <michelebergo@libero.it>
Date: Sun, 07 Nov 2004 16:48:42 GMT
Links: << >>  << T >>  << A >>

"Victor Schutte" <victors@mweb.co.za> ha scritto nel messaggio
news:cml4l6$7i8$1@ctb-nnrp2.saix.net...
> Use a simple counter, in this case a single D-Type Flip Flop.You don't
need
> a PLL if you need sub factors or the main clock.
>
> Victor
> http://www.zertec.co.za
>
>
>
> "Michele Bergo" <michelebergo@libero.it> wrote in message
> news:%ORid.18871$Ni.665341@twister1.libero.it...
> > I want to realize an EPP interface using Altera FPGA Cyclone (read and
> write
> > operation) but I have some synchronization problems. I want to sample
> datas
> > from a 4 bits chip,  storing them in a ZBT SRAM memory (Flow trought)
and
> > later acquiring them by parallel port. the chip works at 10MHz but the
pll
> > on board can't divide input clock of 20MHz for 2. How can I divide the
> > frequency?
> > thanks.  Does anyone do something like that?
> >
> >
thank u very much



Article: 75488
Subject: Re: FPGA Network Encryption Engine
From: "Antti Lukats" <antti@case2000.com>
Date: Sun, 7 Nov 2004 18:32:45 +0100
Links: << >>  << T >>  << A >>
"Shakith" <cybershakith@hotmail.com> wrote in message
news:d700b4dc.0411061950.716fef3d@posting.google.com...
> Hey all,
>
> I have some questions on ISE/EDK.
> I would really appreciate some help.
>
> Before I start, some explanation of my project. It's called Network
> Encryption Engine.
> There are two components in the project, Client and Server. Client is
> our FPGA board.
> Whenever client has request use a specific encryption standard (we
> just using AES only). It will connect to server and download the
> bit-stream and run it on FPGA and will give the necessary outputs.
>
> Question A
> For simple case, we assume the AES part is available locally.
> Our code for AES is on Verilog.
> Our application is running on PowerPC developed by EDK.
> Problem is right now interfacing these two.
>
> For simpler case, like full adder in Verilog and Simple C application
> to write the UART (HyperTerminal), how do I integrate it so that I can
> read the input (full adder) from UART and write it to ports on the
> Verilog code and display the output back in the UART.
>
> Question B
> For network development part, there are several options
> a. XIlnet
> b. RTOS like Vxworks, Linux

free PPC linux should useable as well

> c. ucLinux
> d. Connect to another board which has TCP/IP Stack already enabled.
>
> -Found the Xilinx site that, option (a) is not stable and unreliable

- thats weird! Why is Xilinx providing a solution that they say is not
stable?

> -BSP for option (b) came with the ML310 board, but IDE's to develop
> application need to be bought and are expensive.
> - ucLinux must be ported to ML310 Microblaze design

basic uCLinux porting for new (but suitable) board takes less than one day
(at least to the shell prompt, getting networking done could be taking some
more time). I have done a few ports, after the first one the next ones are
easy :)

Antti




Article: 75489
Subject: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
From: "mike_treseler" <tres@fl_ke.com>
Date: Sun, 07 Nov 2004 13:18:18 -0500
Links: << >>  << T >>  << A >>
Antti wrote:

> Quating Mike Teseler: "use devices from vendors 
> that supply full timing specs.."

What I said was:

"Using devices from vendors who supply full timing specs 
and simulation models makes it (the use of simulation)
possible."

I agree that ChipScope is a cool tool for
characterizing unspecified interfaces, and
I don't doubt that you need it for your work.

But I don't agree that

> "ChipScope Pro is a *MUST* have thing" 

If I'm not driving nails, I don't use a hammer.

         -- Mike Treseler



Article: 75490
Subject: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
From: "Antti Lukats" <antti@case2000.com>
Date: Sun, 7 Nov 2004 20:17:54 +0100
Links: << >>  << T >>  << A >>

"mike_treseler" <tres@fl_ke.com> wrote in message
news:e9aa82b10d77ca24d93eff53b2ae23d2@localhost.talkaboutelectronicequipment.com...
> Antti wrote:
>
> > Quating Mike Teseler: "use devices from vendors
> > that supply full timing specs.."
>
> What I said was:
>
> "Using devices from vendors who supply full timing specs
> and simulation models makes it (the use of simulation)
> possible."
>
> I agree that ChipScope is a cool tool for
> characterizing unspecified interfaces, and
> I don't doubt that you need it for your work.
>
> But I don't agree that
>
> > "ChipScope Pro is a *MUST* have thing"
>
> If I'm not driving nails, I don't use a hammer.
>
>          -- Mike Treseler
>
LOL, ok I give up, you win! ;)

oh smile - actually I admit that I still have a way to go learning proper
simulations, and I also possible use ChipScope also in some cases where pure
simulations could do. However there are pretty many scenarios where
simulations do not deliver the results.

Antti



Article: 75491
Subject: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Sun, 07 Nov 2004 19:31:30 GMT
Links: << >>  << T >>  << A >>
On Sun, 7 Nov 2004 20:17:54 +0100, "Antti Lukats" <antti@case2000.com>
wrote:

>
>"mike_treseler" <tres@fl_ke.com> wrote in message
>news:e9aa82b10d77ca24d93eff53b2ae23d2@localhost.talkaboutelectronicequipment.com...
>> Antti wrote:
>>
>> > Quating Mike Teseler: "use devices from vendors
>> > that supply full timing specs.."
>>
>> What I said was:
>>
>> "Using devices from vendors who supply full timing specs
>> and simulation models makes it (the use of simulation)
>> possible."
>>
>> I agree that ChipScope is a cool tool for
>> characterizing unspecified interfaces, and
>> I don't doubt that you need it for your work.
>>
>> But I don't agree that
>>
>> > "ChipScope Pro is a *MUST* have thing"
>>
>> If I'm not driving nails, I don't use a hammer.
>>
>>          -- Mike Treseler
>>
>LOL, ok I give up, you win! ;)
>
>oh smile - actually I admit that I still have a way to go learning proper
>simulations, and I also possible use ChipScope also in some cases where pure
>simulations could do. However there are pretty many scenarios where
>simulations do not deliver the results.

I don't think there are that many.  Could you provide us a list?

Bob Perlman
Cambrian Design Works


Article: 75492
Subject: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
From: "Antti Lukats" <antti@case2000.com>
Date: Sun, 7 Nov 2004 21:42:40 +0100
Links: << >>  << T >>  << A >>
"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message
news:j4uso0l2k7n98if17s0bp03g7g57sijhdh@4ax.com...
> On Sun, 7 Nov 2004 20:17:54 +0100, "Antti Lukats" <antti@case2000.com>
> wrote:
>
> >
> >"mike_treseler" <tres@fl_ke.com> wrote in message
>
>news:e9aa82b10d77ca24d93eff53b2ae23d2@localhost.talkaboutelectronicequipmen
t.com...
> >> Antti wrote:
> >>
> >> > Quating Mike Teseler: "use devices from vendors
> >> > that supply full timing specs.."
> >>
> >> What I said was:
> >>
> >> "Using devices from vendors who supply full timing specs
> >> and simulation models makes it (the use of simulation)
> >> possible."
> >>
> >> I agree that ChipScope is a cool tool for
> >> characterizing unspecified interfaces, and
> >> I don't doubt that you need it for your work.
> >>
> >> But I don't agree that
> >>
> >> > "ChipScope Pro is a *MUST* have thing"
> >>
> >> If I'm not driving nails, I don't use a hammer.
> >>
> >>          -- Mike Treseler
> >>
> >LOL, ok I give up, you win! ;)
> >
> >oh smile - actually I admit that I still have a way to go learning proper
> >simulations, and I also possible use ChipScope also in some cases where
pure
> >simulations could do. However there are pretty many scenarios where
> >simulations do not deliver the results.
>
> I don't think there are that many.  Could you provide us a list?
>
> Bob Perlman
> Cambrian Design Works

Hi Bob,

http://xilinx.openchip.org/ChipScope/

just for you I created that list! There are only things that did pop-up
easily. I guess there could a few others who could thing of some more cases
where using ChipScope (or other OCI) is really required. And that would make
the list long enough already I would say. :)

Antti




















Article: 75493
Subject: Re: FPGA Network Encryption Engine
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 08 Nov 2004 09:04:44 +1000
Links: << >>  << T >>  << A >>
Hi Sakith,

Shakith wrote:
> Question B
> For network development part, there are several options

> c.	ucLinux

> - ucLinux must be ported to ML310 Microblaze design

The biggest challenge here is the architecture of the ML310 - the 
ethernet NIC is on the PCI bus, not directly connected to the FPGA. 
Fine idea, but makes system implementation that much more complicated 
(more complicated than necessary?)...

So, there's be a bit of work to get the PCI support up and running in 
Microblaze uClinux,  I'm not sure if anyone has done it yet.  I know 
that PCI is regularly supported in other uClinux targets, so perhaps 
it's not such a big deal.  Hit the uclinux-dev and microblaze-uclinux 
mailing lists to find out.

Regards,

John

Article: 75494
Subject: Re: Data Swtich from LPT to LCD Module!
From: johnsonlee@itri.org.tw (Johnson Lee)
Date: 7 Nov 2004 17:27:28 -0800
Links: << >>  << T >>  << A >>
> To summarise :-
> 
> Test 1: PC LPT-->FPGA-->LCD.  FAILS.
> Test 2: PC LPT-->CPLD-->LCD.  FAILS.
> Test 3: PC LPT-->LCD.  No CPLD.  No FPGA.  Works OK.
> Test 4: CPLD-->LCD.  No PC.  Works OK
> Test 5: FPGA-->LCD.  No PC.  Works OK.
> 
> Is this correct?
> Did you check _all_ outputs using an oscilloscope in tests 1+2?
> Was the LCD connected to the same outputs in 1+2 as it was in 4+5?
> Are you using the Altera Quartus development environment?
> Could you post sample Quartus archive (.QAR) files?

Hi Andrew,
 Yes, you are right about those 5 different tests!
 And I didn't check all outputs using oscolloscope only Enable pin and
some data bits. I  can see from oscilloscope when enable pin is
initiate, the data pin voltage will sweep between 3.0V to 5.0 when LCD
module is switched on, but remain 3.0V when LCD is off.
 Same IO assignment in those files...
 Ya, I can show you my code!
 But I don't know how to do that!
 Mail the .QAR to you directly?

 BR,
 Johnson Lee

Article: 75495
Subject: Personality Module (Z-Dok) proto board for ML310
From: "bh" <spam_not@nosuch.com>
Date: Mon, 08 Nov 2004 02:58:52 GMT
Links: << >>  << T >>  << A >>
The Xilinx ML310 evaluation board has a set of connectors
for high-speed interfaces using a Tyco Z-Dok+ interface (6.25Gps).

I've seen in some of the Xilinx brochures a proto board that mates
to these connectors. Does Xilinx provide this board, or is there
a third party that makes the personality module interface boards?

The adapter board connector is a Tyco part 1367555-1 which is
a Z-Dok+6 connector.

I've even seen reference to proto boards like on hitechglobal
that call out the HW-V2P-PM which is described as
"Virtex-II Pro ML310 Personality (Conversion) Modules"
But I can't see any place to order such a thing.

Anyone have any pointers?



Article: 75496
Subject: XST Question
From: "Naimesh" <naimesh.thakkar@gmail.com>
Date: 7 Nov 2004 19:20:25 -0800
Links: << >>  << T >>  << A >>
How do I buffer a signal in XST as I feel it is getting overloaded.
if I write
Signal1 <= Signal;
XST automatically optimizes it.

Please help.
Naimesh


Article: 75497
Subject: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Mon, 08 Nov 2004 05:16:41 GMT
Links: << >>  << T >>  << A >>
On Sun, 7 Nov 2004 21:42:40 +0100, "Antti Lukats" <antti@case2000.com>
wrote:

>"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message
>news:j4uso0l2k7n98if17s0bp03g7g57sijhdh@4ax.com...
>> On Sun, 7 Nov 2004 20:17:54 +0100, "Antti Lukats" <antti@case2000.com>
>> wrote:
>>
>> >
>> >"mike_treseler" <tres@fl_ke.com> wrote in message
>>
>>news:e9aa82b10d77ca24d93eff53b2ae23d2@localhost.talkaboutelectronicequipmen
>t.com...
>> >> Antti wrote:
>> >>
>> >> > Quating Mike Teseler: "use devices from vendors
>> >> > that supply full timing specs.."
>> >>
>> >> What I said was:
>> >>
>> >> "Using devices from vendors who supply full timing specs
>> >> and simulation models makes it (the use of simulation)
>> >> possible."
>> >>
>> >> I agree that ChipScope is a cool tool for
>> >> characterizing unspecified interfaces, and
>> >> I don't doubt that you need it for your work.
>> >>
>> >> But I don't agree that
>> >>
>> >> > "ChipScope Pro is a *MUST* have thing"
>> >>
>> >> If I'm not driving nails, I don't use a hammer.
>> >>
>> >>          -- Mike Treseler
>> >>
>> >LOL, ok I give up, you win! ;)
>> >
>> >oh smile - actually I admit that I still have a way to go learning proper
>> >simulations, and I also possible use ChipScope also in some cases where
>pure
>> >simulations could do. However there are pretty many scenarios where
>> >simulations do not deliver the results.
>>
>> I don't think there are that many.  Could you provide us a list?
>>
>> Bob Perlman
>> Cambrian Design Works
>
>Hi Bob,
>
>http://xilinx.openchip.org/ChipScope/
>
>just for you I created that list! There are only things that did pop-up
>easily. I guess there could a few others who could thing of some more cases
>where using ChipScope (or other OCI) is really required. And that would make
>the list long enough already I would say. :)
>
>Antti

I looked through your list, and most of the cases you cite are ways in
which ChipScope can be used to augment simulation, not replace it.  I
have no problem with that.  But if you're doing little or no
simulation, and are using ChipScope in a Burn-And-Learn environment,
well, you're probably not making the best use of your time.

I used ChipScope on a recent project, and it was, as you suggest, very
handy.  But I also wrote a suite of 175 simulation tests that, run
together, take 5 days to complete.  If I'd relied on ChipScope to do
all of my initial testing and subsequent regression testing (and I
can't overstress the importance of being able to make sure that a
change or addition doesn't torpedo something else), we'd still be
trying to get things working in the lab.

I think Mike Treseler is correct: use the tool that matches the job.

Bob Perlman
Cambrian Design Works



Article: 75498
Subject: SRAM to be able to read/write Micron SDRAM
From: iamyourengineer2004@hotmail.com (Vick)
Date: 7 Nov 2004 21:31:31 -0800
Links: << >>  << T >>  << A >>
Hello all,

I had psted this question earlier but havent got any response yet... 
I was wondering if the questions I asked made any sense (or) were they
just out of the way... So again, I have the Micron SDRAM Verilog code
and I need to make SRAM read/write the SDRAM... Obviosuly, the SRAM
shold maintain its own functionality (i.e. it itself can be
read/written).

The questions I have are:

(1) Should my SRAM just issue Read/Write command to SDRAM Controller
and then it will do the rest i.e. Read/write from SDRAM.

(2) Should'nt  the SRAM output (Q) be a bi-directional since this pin
Q has to be used for SRAM read and also for SDRAM read?


The logidc diagram I have come up with is as below:


                 INTERFACE -Logic
             ______________________________
            |IF Read_SDRAM = 1 then        |       ``````````````````
            |- Initiate SDRAM Read Command |------>|SDRAM Controller|
            |- Addr = SDRAM_Address;       |       `````````````````` 
            |                              |          |
            |IF Write_SDRAM = 1 then       |          |
            |- We_n = Write_SDRAM;         |          |
            |- Addr = SDRAM_Address;       |          |       
             ------------------------------           v
       A ******>| | |                                ____________
      B**********>| |              Addr(11-bits)--->|            |
     C*************>|                    other I/Ps |            |
                | | |                          ...  |            |
                V V V                          ...  |            |
                _____                          ...  |   Micron   |
      Data---->|     |                       ------>|   SDRAM    |
      Wad ---->|     |_________  Q                  |  (168-pin) |
      Rad ---->|SRAM |       |                      |            |
          ---->|_____|       |                      |            |   
                ^ ^ ^        |                      |            |
                | | |        |_______Dq (16-bits)__ |            |
                | | |                               |            |
         clk____| | |                                ____________
       WE ________| |
      RE____________| 




Steps to the above logic-diagram:

(1) I have allocated 3 new pins to the SRAM above namely A,B,C which
are designated as:

   A --> Read_SDRAM (1-bit)
   B --> Write_SDRAM (1-bit)
   C --> SDRAM_Address (11-bits)


(2) The Interface-Logic shown above programs the SDRAM Controller as
to whether the SRAM wants to Read (or) Write the SDRAM. ie. the SDRAM
Controller is asked to fire the appropriate Command to the SDRAM
(Read, Write, Aotorefresh etc..)

(3) The SDRAM Controller then takes over by firing executing the
Command requested by SRAM.

(4) Say, if the SRAM requested a Read from SDRAM, then the data read
(16-bits) is sent back to the pin-Q of SRAM.

Note: that the pin-Q is also used for outputting the 16-bit data for
Reading the SRAM itself!

So folks , please let me know if the above logic and its description
makes sense...


Thanx,
Eagerly waiting...
Vick

Article: 75499
Subject: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
From: "Antti Lukats" <antti@case2000.com>
Date: Mon, 8 Nov 2004 07:41:26 +0100
Links: << >>  << T >>  << A >>

"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message
news:6evto0dq9l3f5c29eid4c8khbp3djbdgab@4ax.com...
> On Sun, 7 Nov 2004 21:42:40 +0100, "Antti Lukats" <antti@case2000.com>
> wrote:
>
> >"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message
> >news:j4uso0l2k7n98if17s0bp03g7g57sijhdh@4ax.com...
> >> On Sun, 7 Nov 2004 20:17:54 +0100, "Antti Lukats" <antti@case2000.com>
> >> wrote:
> >>
> >> >
> >> >"mike_treseler" <tres@fl_ke.com> wrote in message
> >>
>
>>news:e9aa82b10d77ca24d93eff53b2ae23d2@localhost.talkaboutelectronicequipme
n
> >t.com...
> >> >> Antti wrote:
> >> >>
> >> >> > Quating Mike Teseler: "use devices from vendors
> >> >> > that supply full timing specs.."
> >> >>
> >> >> What I said was:
> >> >>
> >> >> "Using devices from vendors who supply full timing specs
> >> >> and simulation models makes it (the use of simulation)
> >> >> possible."
> >> >>
> >> >> I agree that ChipScope is a cool tool for
> >> >> characterizing unspecified interfaces, and
> >> >> I don't doubt that you need it for your work.
> >> >>
> >> >> But I don't agree that
> >> >>
> >> >> > "ChipScope Pro is a *MUST* have thing"
> >> >>
> >> >> If I'm not driving nails, I don't use a hammer.
> >> >>
> >> >>          -- Mike Treseler
> >> >>
> >> >LOL, ok I give up, you win! ;)
> >> >
> >> >oh smile - actually I admit that I still have a way to go learning
proper
> >> >simulations, and I also possible use ChipScope also in some cases
where
> >pure
> >> >simulations could do. However there are pretty many scenarios where
> >> >simulations do not deliver the results.
> >>
> >> I don't think there are that many.  Could you provide us a list?
> >>
> >> Bob Perlman
> >> Cambrian Design Works
> >
> >Hi Bob,
> >
> >http://xilinx.openchip.org/ChipScope/
> >
> >just for you I created that list! There are only things that did pop-up
> >easily. I guess there could a few others who could thing of some more
cases
> >where using ChipScope (or other OCI) is really required. And that would
make
> >the list long enough already I would say. :)
> >
> >Antti
>
> I looked through your list, and most of the cases you cite are ways in
> which ChipScope can be used to augment simulation, not replace it.  I
> have no problem with that.  But if you're doing little or no
> simulation, and are using ChipScope in a Burn-And-Learn environment,
> well, you're probably not making the best use of your time.
>
> I used ChipScope on a recent project, and it was, as you suggest, very
> handy.  But I also wrote a suite of 175 simulation tests that, run
> together, take 5 days to complete.  If I'd relied on ChipScope to do
> all of my initial testing and subsequent regression testing (and I
> can't overstress the importance of being able to make sure that a
> change or addition doesn't torpedo something else), we'd still be
> trying to get things working in the lab.

Sure I did not want to say ChipScope shoud be considered primary before
simulation or replace simulations. Only that in some pure simulations are
not enough if not assisted in the use of on chip instrumentation in the FPGA
verification phase. I kind of did assume that the designs that will will be
used with ChipScope are either passed some formal verication or testbenching
(succesfully!).

Antti

> I think Mike Treseler is correct: use the tool that matches the job.

Sure, - after succesfull simulations try FPGA implementation if it works you
are done, no problems. If still problems, try fix simulations and check
again, if that doesnt help after 10 rounds of fixed problems then it is time
for on chip probing.

> Bob Perlman
> Cambrian Design Works
>
>





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