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Messages from 74625

Article: 74625
Subject: Re: JBits and Spartan
From: Susantha <susantha@mail.com>
Date: Fri, 15 Oct 2004 03:54:00 -0700
Links: << >>  << T >>  << A >>
Does anybody know where JBits verson 1.0 or 1.1 can be downloaded.
Thanks

Article: 74626
Subject: Quartus 4.0, Excalibur Synthesis problem
From: viveklk@hotmail.com (Vivek)
Date: 15 Oct 2004 05:47:46 -0700
Links: << >>  << T >>  << A >>
Hi,

I am facing a strange problem while doing Synthesis P&R of a 
logic on "Excalibur" device (Altera EPXA10F1020C1 Package 
FBGA1020) using "Quartus 4.0".

The logic written in Verilog is as below:-

---------------------------------------------------------
always @(negedge ResetN or posedge Clk1)
    begin:logic1
        if(ResetN == 1'b0)
        begin
            delayedReadyN1 <= 1'b1;
        end
        else
        begin
            delayedReadyN1 <= ReadyN;
        end
    end
    
    
always @(negedge ResetN or posedge Clk2)
    begin:logic2
        if(ResetN == 1'b0)
        begin
            delayedReadyN2 <= 1'b1;
        end
        else
        begin
            delayedReadyN2 <= ReadyN;
        end
    end    
----------------------------------------------------------

ReadyN      = is a signal generated in 'Clk1' domain.
Clk1 & Clk2 = are '80MHz' clocks.
ResetN      = Asynchronous reset.

Quartus timing analyzer "doesn't give any timing violation" on these
but
when I do timing simulation using ModelSim (using .vo & .sdo files), 
I observed that 'delayedReadyN2' changes as expected but 
'delayedReadyN1' doesn't change at all even though input signal
 'ReadyN' is changing! 

ReadyN is generated in Clk1 domain is being assigned to 
'delayedReadyN2' under Clk2 but not to 'delayedReadyN1'
under same clock Clk1.

I examined the cells in .vo file, which appears as below :-


----------------------------------------------------------

// atom is at LC5_12_I2
apex20ke_lcell \delayedReadyN1~I (
// Equation(s):
// delayedReadyN1 = DFFE(!\ReadyN~combout , \Clk1~combout ,
GLOBAL(\ResetN~combout ), , )

    .dataa(vcc),
    .datab(vcc),
    .datac(vcc),
    .datad(\ReadyN~combout ),
    .cin(gnd),
    .cascin(vcc),
    .clk(\Clk1~combout ),
    .aclr(!\ResetN~combout ),
    .ena(vcc),
    .sclr(gnd),
    .sload(gnd),
    .devclrn(devclrn),
    .devpor(devpor),
    .combout(),
    .regout(delayedReadyN1),
    .cout(),
    .cascout());
// synopsys translate_off
defparam \delayedReadyN1~I .operation_mode = "normal";
defparam \delayedReadyN1~I .packed_mode = "false";
defparam \delayedReadyN1~I .lut_mask = "00FF";
defparam \delayedReadyN1~I .output_mode = "reg_only";
// synopsys translate_on

 
// atom is at LC2_13_R2
apex20ke_lcell \InstA|delayedReadyN2~I (
// Equation(s):
// \InstA|delayedReadyN2  = DFFE(!\ReadyN~combout ,
GLOBAL(\Clk2~combout ), GLOBAL(\ResetN~combout ), , )

    .dataa(vcc),
    .datab(vcc),
    .datac(vcc),
    .datad(\ReadyN~combout ),
    .cin(gnd),
    .cascin(vcc),
    .clk(\Clk2~combout ),
    .aclr(!\ResetN~combout ),
    .ena(vcc),
    .sclr(gnd),
    .sload(gnd),
    .devclrn(devclrn),
    .devpor(devpor),
    .combout(),
    .regout(\InstA|delayedReadyN2 ),
    .cout(),
    .cascout());
// synopsys translate_off
defparam \InstA|delayedReadyN2~I .operation_mode = "normal";
defparam \InstA|delayedReadyN2~I .packed_mode = "false";
defparam \InstA|delayedReadyN2~I .lut_mask = "00FF";
defparam \InstA|delayedReadyN2~I .output_mode = "reg_only";
// synopsys translate_on

----------------------------------------------------------

I checked all the signals related to the cells & found to be 
exactly as expected. 

What can be the problem? :(

Best Regards,
Vivek

Article: 74627
Subject: Re: WebPACK post-PAR min clock period?
From: "Channing_W" <channing@pldsupport.com>
Date: Fri, 15 Oct 2004 21:37:09 +0800
Links: << >>  << T >>  << A >>
Dear Eric,

You can get the clock period in Timing Analyzer by selecting "Against Auto
Generated Design Constraints..." whatever you have added the PERIOD
constraints or not,  even if that is recomanded.



"Eric Smith" <eric-no-spam-for-me@brouhaha.com> ????
news:qhoej4jzix.fsf@ruckus.brouhaha.com...
> I wrote:
> > I'm using WebPACK 6.3.01i.  The synthesis report tells me the minimum
> > clock period is about 17 ns.  [...] How do I get the same kind of
> > static timing info after place and route?
>
> "Symon" <symon_brewer@hotmail.com> writes:
> > You must constrain your design before the P&R tools try to meet timing.
In
> > the Xilinx tools I add a line like:-
> > NET "CLOCK" PERIOD = 10ns;
> > or something like that. Read the Xilinx constraints guide.
>
> Thanks, I'll give that a try.  It seems somewhat surprising that they
> don't report the clock period without an explicit constraint; Cypress
> WARP does.



Article: 74628
Subject: Re: Question on Xilinx VirtexPro II FPGA chip... please
From: "E.S." <emu@ecubics.com>
Date: Fri, 15 Oct 2004 07:41:57 -0600
Links: << >>  << T >>  << A >>
Tuukka Toivonen wrote:

> Which development kit exactly? There are quite a bit of them:
> http://www.xilinx.com/publications/matrix/devboard_color.pdf

It would really help to know ...
;-)

>>change buying decisions - its already here, we need to know:
>>1. Is it possible to put either Linux or Nucleus RTOS into this chip memory, 
>>to my knowledge your chip includes two PowerPC's and we intend to use it as 
> 
> Into the _FPGA_ chip memory--no, I don't think it has enough memory
> (just a few hundred of kilobytes).

If he got the xc2vp100, probably ...

> I don't have the hardware yet (planning to get it), but I know
> that there are Linux distributions that run on the FPGA, for example
> TimeSys Linux which should run on Amirix development boards out of the box.

The support for the VirtexIIPro is in the CVS (AFAIK), so why do you 
need a special distribution ?

> I don't know how much work would it be to port the Linux to run
> on some other development kit, but in theory it is possible.

To get Linux booting (kernel and console I/O) shouldn't be more than 
very few days. The big part is to get the drivers right for the "weird" 
devices you probably have on the board ..


cheers



Article: 74629
Subject: Re: spartan 3 on 4 layers
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 15 Oct 2004 07:27:17 -0700
Links: << >>  << T >>  << A >>
Tom,

There is no "C" in Ldi/dt.

If you can find out how varying a capacitance in any way changes the 
induced bounce (V=-Ldi/dt), let me know.

Bypass capacitance prevents rail collapse, but it does nothing to 
prevent ground bounce (it can actually make it worse, as there is more 
energy stored which makes di larger and dt faster).

Austin

Tom Seim wrote:
> Austin Lesea <austin@xilinx.com> wrote in message news:<ckjgil$5pe1@cliff.xsj.xilinx.com>...
> 
>>Colin,
>>
>>Our SSO rules assume you have dedicated planes for Vccint, Vcco.  If you 
>>do not have both a power and a ground plane for each of these supplies, 
>>the SSO numbers must be reduced.  This also goes for simultaneously 
>>switching CLBs, and not just IOs.  We assume a power and ground plane 
>>(yes that would be four layers just for power) for low inductance on the 
>>Vccint/Vcco.
>>
>>You might want to investigate the Point of Load concept (POL or POLA) 
>>from TI (US) and Belkin (Japan).
>>
>>By placing power supplies directly at the load, the loop inductance is 
>>greatly reduced.
>>
>>I have a SDRAM+2VP20 PCI pcb that has four layers, and operates very 
>>well.  Perhaps you pay more for a more capable power supply, but you pay 
>>less for the PCB.
>>
>>Remember that V=-LdI/dt.  There is no way to reduce ground and Vcc 
>>bounce without reducing either the I (current switched by reducing the 
>>number of things switching), or reducing the L (indutance). The time 
>>(dt) is not something that can be changed (as in internal nodes switch 
>>time is fixed by process and design).
>>
>>No amount of bypass caps will fix a bad pcb.
> 
> 
> This is a very curious statement. Bypass caps provide virtually all of
> the high frequency current-they get recharged by power supply.
> Granted, you need low impedance to recharge the caps before they are
> used again, but the power supply is not supplying the fast edge
> currents.

Article: 74630
Subject: Re: Question on Xilinx VirtexPro II FPGA chip... please
From: Tuukka Toivonen <tuukkat@killspam.ee.oulu.finland.invalid>
Date: Fri, 15 Oct 2004 14:33:12 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <DsQbd.63$_d5.53@fe39.usenetserver.com>, E.S. wrote:
>> I don't have the hardware yet (planning to get it), but I know
>> that there are Linux distributions that run on the FPGA, for example
>> TimeSys Linux which should run on Amirix development boards out of the box.
> 
> The support for the VirtexIIPro is in the CVS (AFAIK), so why do you 
> need a special distribution ?

Which CVS? Do you mean latest Linux kernel 2.6.8.1? Grepping around the
source, I find some interesting defines in arch/ppc/boot/simple/rw4.
Can you provide any pointers for documentation about running standard
Linux on Virtex-II Pros?

> To get Linux booting (kernel and console I/O) shouldn't be more than 
> very few days. The big part is to get the drivers right for the "weird" 
> devices you probably have on the board ..

Very interesting.

Article: 74631
Subject: Re: Metastability pipeline causes bad juju
From: Chris <>
Date: Fri, 15 Oct 2004 08:24:03 -0700
Links: << >>  << T >>  << A >>
ModelSim's free edition isn't too great. I tried using it with my design early on and it ran into its max number of gates very quickly. The Xilinx Edition is a crippled version of the full version that still only has a pretty limited FPGA size. Given $10k and the choice between a logic analyzer and Modelsim, I think it's a pretty obvious choice.

I'm not against simulating, of course, but in my experience it can take just as long to run a simulation as it does to compile and burn code into a chip. Perhaps I am a little biased from my days of working with ModelSim on Sparc Stations, where it might take 20 minutes to run a simulation of medium complexity and anything over a certain size you might as well run over your lunch break or even overnight. Back then I just got in the habit of testing/troubleshooting in hardware with a logic analyzer if the simulation was too complex. With little effort you can route all of the important nodes in the device out to your logic analyzer and change between different sets of test signals in real-time by just putting in a little serial port control program or even by setting jumpers on the board.

As far as the impossibility of doing this with a "complex" design, I've got an XC2V1500 about 70% full and I've never simulated any of it. This includes a custom soft processor, Viterbi and Reed Solomon encoder, etc. It's not exactly rocket science but it's not 2k territory either.

Another thing -- as a system becomes more complex, simulations become less viable. Just ask any weatherman or climatologist. Okay, so an FPGA isn't a chaotic system but it still applies. At what point does it become such a pain to simulate all the various interfaces with sufficient fidelity that you're better off just trying it in the hardware? How often have you had a problem in the hardware and it turns out to be something you never even THOUGHT to simulate?

Article: 74632
Subject: Re: spartan 3 on 4 layers
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 15 Oct 2004 15:51:18 GMT
Links: << >>  << T >>  << A >>
"Austin Lesea" <austin@xilinx.com> wrote in message
news:ckomo5$s21@cliff.xsj.xilinx.com...
> Tom,
>
> There is no "C" in Ldi/dt.
>
> If you can find out how varying a capacitance in any way changes the
> induced bounce (V=-Ldi/dt), let me know.
>
> Bypass capacitance prevents rail collapse, but it does nothing to
> prevent ground bounce (it can actually make it worse, as there is more
> energy stored which makes di larger and dt faster).
>
> Austin
[snip]

I think the point being made here is that bypass caps located where the
inductance between the caps and the chip is small, the i in di/dt *is*
significantly altered if the i being discussed is power/ground plane
inductance.

The regulator at the load should only help out if 1) the regulator has
extremely fast response or 2) the current demands fluctuate at very high
aplitudes at much lower frequencies.

The designer *must* keep in mind the effect of a sudden increase in current
on the total available charge from the bypass caps locally.  If the
step-increase in current deflates those bypass caps beyond the voltage
tolerance of the target device, very bad things will happen.  It's better to
overdesign the bypass caps (rather than relying on the minimum operating
voltage of the chip) because of other effects like induced jitter.

When the bypass caps do their job in the frequency range they're designed
for, the lower frequencies still need to be accommodated.  That's where the
regulator takes over.  With a response in the 10s of microseconds, a good
regulator won't have a problem delivering the change of current where the
bypass caps are starting to lose effectiveness.

If there are inexpensive regulators with 100s of nanoseconds respons time,
I'd be paying closer attention to a distributed power delivery approach.  I
took a quick look at a some LDO regulators which - while claiming to have
"fast transient response" - give no actual data on the recovery time.  Is it
worth a 500 mV dropout into 1.2V to use an LDO rather than a switcher far
from the chip with an appropriate bypassing scheme?

The "Point of Load" at ti.com comes up with a DC/DC switcher module where
"the transient response of the DC/DC converter has been
characterized using a load transient with a di/dt of 1 A/s."  While this
appears to be a better spec than I originally figured (for available supply
voltages down to 3.3V, not 1.2V yet) the location could still easily be a
couple nanoseconds of board distance away (about 10"?) and not feel the
difference in the transient due to the di/dt of the power plane.

If there is a "new, better way" to power our transient-rich designs compared
to good - local - decoupling schemes, I'd be interested to read up.  As long
as decoupling is within 1/10 the wavelength of the capacitor's effective
frequency on a zero inductance plane, the capacitor will do it's job.  As
long as the capacitor is not degraded by the plane inductance between the
cap and the chip, the cap will do its job.  If a cap is marginalized by an
inductance, the cap will be less effective and some analysis may be
warranted.  The numbers whould be considered.



Article: 74633
Subject: Re: EP1C12 or XC3S400?
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 15 Oct 2004 12:07:28 -0400
Links: << >>  << T >>  << A >>
Arash Salarian wrote:
> 
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:416EE08B.443D61B5@yahoo.com...
> > I have not been able to
> > confirm that the Altium board is usable without the Altium software
> > (demo version has a 30 day license only).  There are JTAG ports on the
> > board, but the use a connector for the PC parallel port.  I also don't
> > understand why there are *two* of them, soft and hard.
> 
> I remember to read it somewhere in the Altium site that says that the boards
> WORK without Altium software. Also, by looking at the schematics you can see
> that in the Altera's version, they say the interface is compatible with
> ByteBlaster and for the Xilinx version it has been written to be compatible
> with ISE.

I have not seen that.  I downloaded the Xilinx version info and did not
see anything relevant in the manual.  In particular, my concern is how
to acutally hook the board up and get it to work without the Altium
tools.  The connector on the eval board is not standard and is designed
to work with their cable and PC software talking to the parallel port. 
I belive it will require Altium software to make this work.  


> I could not find any Cyclone EP1C12 or Spartan 3 XC3S400 prototype board
> with more than just an FPGA on it under (I mean, with some RAM, connectors,
> programmer interface, ...) under $200 and it seems that the Altium's
> offering has a great price.
> The only thing that I find missing in this board is the lack of a AD/DA on
> board. It would be very nice if they could fit a fast AD/DA in the same
> board and keep the same price ;)

The board does have a stereo output which is driven by an FPGA output
pin.  I assume they intend for this to be driven by a PWM output.  They
also supply a crude DAC for the VGA outputs.  It uses three bits driving
different value resistors.  

For my needs it is very short on user IO.  They only bring 36 pins to
connectors and has many pins on the FPGA unconnected.  

I find it interesting that it has both keyboard and mouse PS/2
connectors.  With the VGA output, this could be used for video games and
such.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 74634
Subject: Re: Metastability pipeline causes bad juju
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 15 Oct 2004 12:22:57 -0400
Links: << >>  << T >>  << A >>
Chris wrote:
> 
> ModelSim's free edition isn't too great. I tried using it with my design early on and it ran into its max number of gates very quickly. The Xilinx Edition is a crippled version of the full version that still only has a pretty limited FPGA size. Given $10k and the choice between a logic analyzer and Modelsim, I think it's a pretty obvious choice.

I guess I am not clear about this.  The "max" lines of code have to do
with the simulation speed.  I am currently still using the free version
of modelsim even though I passed the size threshold long ago.  I really
don't see a significant slowdown in my simulations.  I guess if I were
running very long simulations it might be an issue, but the software is
still very usable.  

I am not trying to argue the point with you, but how do you probe inside
the FPGA with a logic analyzer?  Do you recompile to bring out internal
points to IO pins?  


> I'm not against simulating, of course, but in my experience it can take just as long to run a simulation as it does to compile and burn code into a chip. Perhaps I am a little biased from my days of working with ModelSim on Sparc Stations, where it might take 20 minutes to run a simulation of medium complexity and anything over a certain size you might as well run over your lunch break or even overnight. Back then I just got in the habit of testing/troubleshooting in hardware with a logic analyzer if the simulation was too complex. With little effort you can route all of the important nodes in the device out to your logic analyzer and change between different sets of test signals in real-time by just putting in a little serial port control program or even by setting jumpers on the board.

One of the things you can do in a simulation is to create a test bench
that not only drives the inputs to your design, it verifies the
outputs.  This can relieve you of a lot of tedious manual checking of
signals.  

If you are happy with your technique, fine.  But you might want to
revisit the simulation world and see what has changed in the last
however many years.  


> As far as the impossibility of doing this with a "complex" design, I've got an XC2V1500 about 70% full and I've never simulated any of it. This includes a custom soft processor, Viterbi and Reed Solomon encoder, etc. It's not exactly rocket science but it's not 2k territory either.
> 
> Another thing -- as a system becomes more complex, simulations become less viable. Just ask any weatherman or climatologist. Okay, so an FPGA isn't a chaotic system but it still applies. At what point does it become such a pain to simulate all the various interfaces with sufficient fidelity that you're better off just trying it in the hardware? How often have you had a problem in the hardware and it turns out to be something you never even THOUGHT to simulate?

I catch all sorts of bugs in simulation that I did not expect.  I don't
design my simulation purely to find bugs I think of.  I design my
simulations to verify that a circuit is working correctly, just like the
tests I run on the hardware.  

So how does *not* simulating help finding bugs that would be missed in
simulation?  

I am not trying to argue this point.  If you are happy not simulating,
fine.  But you asked about a problem that in simulation would likely
have been identified quickly or at least could be explored.  I am just
trying to point out that fact.  Why isn't the logic analyzer helping you
with this problem?  Can't you bring these signals and data out to the IO
pins?  That should identify the problem.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 74635
Subject: Re: EP1C12 or XC3S400?
From: "John Williams" <john.williams@remove.alumni.stanford.org>
Date: Fri, 15 Oct 2004 09:23:04 -0700
Links: << >>  << T >>  << A >>

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:416FF5C0.2703E83A@yahoo.com...
>
> I have not seen that.  I downloaded the Xilinx version info and did not
> see anything relevant in the manual.  In particular, my concern is how
> to acutally hook the board up and get it to work without the Altium
> tools.  The connector on the eval board is not standard and is designed
> to work with their cable and PC software talking to the parallel port.
> I belive it will require Altium software to make this work.
>

It will work with the standard Xilinx toolset (ISE 6.x, impact).
The parallel port cable is pin compatible with the Xilinx download cables at
the PC end (standard JTAG programming chain)  but adds an additional JTAG
channel for Altium's special "soft" chain.



Article: 74636
Subject: Re: spartan 3 on 4 layers
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 15 Oct 2004 12:28:35 -0400
Links: << >>  << T >>  << A >>
John_H wrote:
> 
> "Austin Lesea" <austin@xilinx.com> wrote in message
> news:ckomo5$s21@cliff.xsj.xilinx.com...
> > Tom,
> >
> > There is no "C" in Ldi/dt.
> >
> > If you can find out how varying a capacitance in any way changes the
> > induced bounce (V=-Ldi/dt), let me know.
> >
> > Bypass capacitance prevents rail collapse, but it does nothing to
> > prevent ground bounce (it can actually make it worse, as there is more
> > energy stored which makes di larger and dt faster).
> >
> > Austin
> [snip]
> 
> I think the point being made here is that bypass caps located where the
> inductance between the caps and the chip is small, the i in di/dt *is*
> significantly altered if the i being discussed is power/ground plane
> inductance.

The L di/dt issue is a red herring.  Every good engineer knows that *NO*
circuit is pure L or pure C or even pure R.  All circuits are a
combination of the three (hopefully linear) and what matters is the
resulting Z.  


> The regulator at the load should only help out if 1) the regulator has
> extremely fast response or 2) the current demands fluctuate at very high
> aplitudes at much lower frequencies.

NO regulator has enough speed to respond at the frequencies that power
planes address.  Even if they did, the required distance between the
regulator and the chip would add L (increasing the Z) to a point that
counters the feature.  


 
> When the bypass caps do their job in the frequency range they're designed
> for, the lower frequencies still need to be accommodated.  That's where the
> regulator takes over.  With a response in the 10s of microseconds, a good
> regulator won't have a problem delivering the change of current where the
> bypass caps are starting to lose effectiveness.

...snip..
 
> If there is a "new, better way" to power our transient-rich designs compared
> to good - local - decoupling schemes, I'd be interested to read up.  As long
> as decoupling is within 1/10 the wavelength of the capacitor's effective
> frequency on a zero inductance plane, the capacitor will do it's job.  As
> long as the capacitor is not degraded by the plane inductance between the
> cap and the chip, the cap will do its job.  If a cap is marginalized by an
> inductance, the cap will be less effective and some analysis may be
> warranted.  The numbers whould be considered.

You are preaching to the choir now!  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 74637
Subject: Re: altera quartus II handbook is wrong??
From: sdatta@altera.com (Subroto Datta)
Date: 15 Oct 2004 09:34:42 -0700
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> wrote in message news:<416F5B46.94C42BCB@yahoo.com>...


> "Easiest" is a subjective term.  I avoid all instantiations if I can to
> make the code more portable.  Is there a way to use an initialization
> file with inferred RAM or ROM?  In my case it actually will be RAM since
> the processor can update its own program.  
> 


Hi Rick,

   We hear you and are working on specifying the initialization file
within the HDL. It will be available in one of the 2005 releases.

Hope this helps,

Subroto Datta
Altera Corp.

Article: 74638
Subject: Re: EP1C12 or XC3S400?
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 15 Oct 2004 13:02:37 -0400
Links: << >>  << T >>  << A >>
John Williams wrote:
> 
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:416FF5C0.2703E83A@yahoo.com...
> >
> > I have not seen that.  I downloaded the Xilinx version info and did not
> > see anything relevant in the manual.  In particular, my concern is how
> > to acutally hook the board up and get it to work without the Altium
> > tools.  The connector on the eval board is not standard and is designed
> > to work with their cable and PC software talking to the parallel port.
> > I belive it will require Altium software to make this work.
> >
> 
> It will work with the standard Xilinx toolset (ISE 6.x, impact).
> The parallel port cable is pin compatible with the Xilinx download cables at
> the PC end (standard JTAG programming chain)  but adds an additional JTAG
> channel for Altium's special "soft" chain.

Ok, that makes sense.  I exchanges about a dozen emails with one of
Altium's tech people and I still did not get an answer that gave me
confidence that my question was understood.  I guess they feel it is
obvious that the vendor tools are used to do the download.  

Does Altium use the same cable with both the Spartan 3 and the Cyclone
version of the boards?  Are the same parallel port pins used by the
Quartus and the ISE software?  Or did they design the cable to
accomodate both sets of connections in one cable?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 74639
Subject: ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor
From: "Sandeep Dutta" <webmaster@niktech.com>
Date: Fri, 15 Oct 2004 10:07:48 -0700
Links: << >>  << T >>  << A >>
http://www.niktech.com

Hardware Features

 Data Path Width 32 bits
 Most instructions are 16 bit. PC Relative jump instructions are 32 bit.
 Four stage pipeline.
 Von Neumann Architecture (Data and Instruction in the same address space).
 Sixteen, 32 bit General Purpose Registers.
 Four USER defined instructions (with Register File Write back capability).
 Parallel execution of independent Load/Store, Multiply/Shift ,
    User Defined Instructions and  ALU instructions (In order issue;  Out of
order completion)
 Some Conditional Instructions (Reduces branches & increases code density).
 Built in 32 bit Timer.
 Power Down Mode.
 32x32 Multiplier (Multi cycle execution).

Software Development Tools
 GNU Assembler, Linker (binutils)
 GCC (C  Compiler)
 GDB (Debugger) and Instruction Set Simulator
 Standalone C-Library (RedHat newlib)
 Modified version of DietLibc

Size and Performance.

Netlists for the current implementation is available for XILINX Virtex,
Spartan-II and Spartan-IIE; it
utilizes 1375 LUTs (809 slices); the size includes a 32 bit timer and a
32x32 bit LUT based multiplier.

The design has been tested to operate at  60MHZ on a Spartan-II (speed
grade -6).

Netlists, Documentation and Development tools can be downloaded from
http://www.niktech.com.



Article: 74640
Subject: Re: Metastability pipeline causes bad juju
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 15 Oct 2004 10:10:23 -0700
Links: << >>  << T >>  << A >>
Rick,
In those days, simulation was *more* important. No auto-router to get the
test signals out. Anyone remember SILOS?
Syms.
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:416F6EB4.38D9B2C2@yahoo.com...
> one *at all*!  Have you ever designed an FPGA without simulating???  If
> you have, I bet it was before I was working with FPGAs, most likely on
> the Xilinx 2k devices...  ;)
>



Article: 74641
Subject: which xilinx CPLD to select?
From: "vax, 9000" <vax9000@gmail.com>
Date: Fri, 15 Oct 2004 13:11:42 -0400
Links: << >>  << T >>  << A >>
I am pretty new to the Xilinx world and I am seeking the answers to my
questions here. The requirements are listed here,
1. 3.3V or 5V parts (compatible with TTL/HTCmos)
2. no smaller than XC95288
3. supported by free webpack
4. easy to deal with (PLCC or TQ or PQFP or PGA, no BGA)
5. more than 80 I/O pins
6. can buy in small quantities (3, for example).
7. low cost

XC95288/XC95288XL fit 1,2,3,4,5,6 but I think there might exist cheaper
parts. Less than $10 will be considered good enough. Thanks.

BTW, is it easy to move a CPLD design (VHDL) to FPGA? It has mostly adders
(5 MHz or lower) and state machines (20MHz). Thanks. If so, would you also
let me know what FPGA family to look at, with those requirements applied?

vax, 9000

Article: 74642
Subject: Re: which xilinx CPLD to select?
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 15 Oct 2004 13:21:56 -0400
Links: << >>  << T >>  << A >>
"vax, 9000" wrote:
> 
> I am pretty new to the Xilinx world and I am seeking the answers to my
> questions here. The requirements are listed here,
> 1. 3.3V or 5V parts (compatible with TTL/HTCmos)
> 2. no smaller than XC95288
> 3. supported by free webpack
> 4. easy to deal with (PLCC or TQ or PQFP or PGA, no BGA)
> 5. more than 80 I/O pins
> 6. can buy in small quantities (3, for example).
> 7. low cost
> 
> XC95288/XC95288XL fit 1,2,3,4,5,6 but I think there might exist cheaper
> parts. Less than $10 will be considered good enough. Thanks.
> 
> BTW, is it easy to move a CPLD design (VHDL) to FPGA? It has mostly adders
> (5 MHz or lower) and state machines (20MHz). Thanks. If so, would you also
> let me know what FPGA family to look at, with those requirements applied?

I can tell you that item 1, 5 and 7 are hard to combine.  The Xilinx
parts that might do best are the Coolrunner (not Coolrunner II)
XCR3128XL or larger.  But they won't be cheap depending on how you
define cheap.  Expect to pay around $15 or so in 100's. If you need the
XCR3256XL or larger the price goes up very quickly!  I believe they want
over $40 for the XCR3512XL.  But prices are always negotialble.  

Lattice has some parts as well, the 5000MX family.  But be careful about
the 5 volt tolerance, it has limitations.  

Getting 5 volt tolerance in a PLD or FPGA is getting hard to find.  If
you don't need Flash non-volatility, look at the ACEX parts (EP1Kxx)
from Altera.  This is one of the more modern, low-cost, 5 volt tolerant
FPGAs around.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 74643
Subject: Was EP1C12 or XC3S400? : Is Altium eval board
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 15 Oct 2004 13:28:17 -0400
Links: << >>  << T >>  << A >>
I had noticed a few issues with the Altium schematics for their FPGA
boards earlier.  But I was looking closely at the Altera version of the
schematic and realize that they have actual wiring flaws in the
drawings!  The PP_HARD_TDI signal has no connection to the parallel port
connector and the PP_HARD_TDO signal runs over top of a resistor and may
actually be shorting two nets!!!  Isn't Altium selling the eval board to
get you to evaluate their tools including schematic capture and board
layout???  This is not much of a recommendation.  

On the page with the FPGA many of the net lables are turned around and
upsidedown and lie over top of other net labels so that they can not be
read.  Maybe it's just me, but I would not even consider buying software
that the makers find hard to use.  I don't' think I can even make these
mistakes with Orcad.  The software is not that "capable".  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 74644
Subject: SPARTANI II - PCI target logic - what code generates burst read ?
From: "Dan DeConinck of PixelSmart" <Dan@pixelsmart.com>
Date: Fri, 15 Oct 2004 13:36:56 -0400
Links: << >>  << T >>  << A >>
Hello ,

I have designed a PCI target ( 32bits/33 Mhz ) and I have implemented it in
a Xilinx Spartan II

It is working correctly for single data phase reads. Now I want the CPU to
generate a burt read.

I have been unable to generate the CPU burst read. My code was written with
DEBUG under DOS
 This code moves 255 16bit words from my PCI target to the CPU main memory

Mov CX, 00FF
REPZ
MOVSW

The code successfully executes BUT it is done as individual transactions.
Each transaction is a single double word read.

There are 20 PCI clocks between reads. ( my PCI logic added 2 wait states as
intended by the design )

QUESTION ONE: - what code should I use to generate a burst read ?
QUESTION TWO: - why are there 20 pci clocks between reads ? ( 14 more than I
would expect )

Thank you.

Sincerely Daniel DeConinck, PixelSmart Tel 416-248-4473 or 800-884-1734
www.PixelSmart.com ----Move Your Pixels Smarter ! -----  2004 PixelSmart ,
All Rights reserved.



Article: 74645
Subject: Re: WebPACK post-PAR min clock period?
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 15 Oct 2004 10:43:19 -0700
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> writes:
> I am not aware that they *don't* report a max clock speed, but it is
> very unusual to care about clock speed if you don't spec a requirement. 
> If you don't use a speed constraint, the tool assumes you don't care
> about the speed and just does a route without any optimization.  Isn't
> that obvious? 

No, it's not obvious.  You could just as easily say that an automaker
shouldn't include a speedometer in a new car unless you tell the dealer
how fast you plan to drive.

If I give an explicit constraint, I want the tools to work harder (if
necessary) to try to meet it, but that doesn't mean that if I don't give
a constraint that I don't care about it at all.  By that reasoning it
would be fine for the tools to produce a design with a minimum clock
period of a fortnight.

Article: 74646
Subject: Re: spartan 3 on 4 layers
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 15 Oct 2004 10:46:04 -0700
Links: << >>  << T >>  << A >>
John,

See comments below,

Austin


> [snip]
> 
> I think the point being made here is that bypass caps located where the
> inductance between the caps and the chip is small, the i in di/dt *is*
> significantly altered if the i being discussed is power/ground plane
> inductance.

Actually, my point is this: given some bypass arrangement, the ground 
bounce does not vary if you suddenly make all the byapssing 10X better 
(ie better caps, more farads).  In fact, bounce may get worse because 
the rails are not collapsing (anymore) externally.

> 
> The regulator at the load should only help out if 1) the regulator has
> extremely fast response or 2) the current demands fluctuate at very high
> aplitudes at much lower frequencies.

Agreed.  On chip, the current demand is almost instant.  By the time the 
local capacitance on die is exhausted, and the caps in the package are 
out of charge, and the immediate external bypass caps have also given up 
their electrons, the time of the current profile has been stretched.  If 
a regulator is fast enough, it can help.  If it is too slow, it can't.

The PCI/SDRAM card I have with the POL ultra-fast transient regulators 
was able to use 4 layers.  Never seen anything less than 8 layers used 
before.  Pretty clever designers for that PDS.

-snip-

> The "Point of Load" at ti.com comes up with a DC/DC switcher module where
> "the transient response of the DC/DC converter has been
> characterized using a load transient with a di/dt of 1 A/s."  While this
> appears to be a better spec than I originally figured (for available supply
> voltages down to 3.3V, not 1.2V yet) the location could still easily be a
> couple nanoseconds of board distance away (about 10"?) and not feel the
> difference in the transient due to the di/dt of the power plane.

I believe they have all the way down to 1.0 volt available now.  Check 
with your TI disti.  Belnix is adjustable with a resistor.

http://www.belnix.co.jp  (most of the literature is in Japanese, and I 
have received some recent English translations, but I am still at a 
disadvantage here....)

http://focus.ti.com/docs/pr/pressrelease.jhtml?prelId=sc04126

> 
> If there is a "new, better way" to power our transient-rich designs compared
> to good - local - decoupling schemes, I'd be interested to read up.  As long
> as decoupling is within 1/10 the wavelength of the capacitor's effective
> frequency on a zero inductance plane, the capacitor will do it's job.  As
> long as the capacitor is not degraded by the plane inductance between the
> cap and the chip, the cap will do its job.  If a cap is marginalized by an
> inductance, the cap will be less effective and some analysis may be
> warranted.  The numbers whould be considered.

Agree on all of the above.

The Belnix POL supply has a 50 mV  MAX droop for a 5 ampere load change 
(step, instant load change).  Looks like it never even saw the load 
change, except the IR drop happens and you see 50 mV change.  They talk 
about a ~100 ns time to go from 0 amperes, to supplying 5 amperes with 
no overshoot or ringing of the output (beyond the normal switching noise 
and the IR drop of 50 mV).

Initially, I was a non-believer, like you.  Basic rules were separate 
planes, minimize inductance, maximize bypass, etc.  1/10 wavelength back 
of the envelope rules, etc.  Then I saw a 4 layer pcb with a POL 
regulator (actually, two, one for core, and one for IO) and very few 
bypass caps.  I had never seen a working 4 layer pcb prior to that with 
PCI AND SDRAM on a 2VP20 (let alone one without a lot of caps).  Just 
too much current needs to be switched for BOTH PCI and SDRAM, and the 
only other solution I had seen were two planes for Vccint, and two 
planes for Vcco, plus a lot of bypass caps (one per power ground pin pair).

Perhaps we are both over simplifying the problem?  Perhaps is it more 
like a power transfer problem over a 2-D transmission line:   the longer 
the line, the worse the problem?  By shortening the line to less than 1" 
(25.4mm), the POL concept is a better solution?  The output impedance of 
the power supply (an active and complex value) is reflected to the load 
and is kept at a much lower magnitude, which causes much less voltage 
fluctuation?

Article: 74647
Subject: Re: Metastability pipeline causes bad juju
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 15 Oct 2004 11:02:40 -0700
Links: << >>  << T >>  << A >>
Chris,

I won't say that simulation isn't a good thing, but I will say that 
Chipscope Pro(tm) sure beats using a logic analyzer.

Austin

Chris wrote:
> ModelSim's free edition isn't too great. I tried using it with my design early on and it ran into its max number of gates very quickly. The Xilinx Edition is a crippled version of the full version that still only has a pretty limited FPGA size. Given $10k and the choice between a logic analyzer and Modelsim, I think it's a pretty obvious choice.
> 
> I'm not against simulating, of course, but in my experience it can take just as long to run a simulation as it does to compile and burn code into a chip. Perhaps I am a little biased from my days of working with ModelSim on Sparc Stations, where it might take 20 minutes to run a simulation of medium complexity and anything over a certain size you might as well run over your lunch break or even overnight. Back then I just got in the habit of testing/troubleshooting in hardware with a logic analyzer if the simulation was too complex. With little effort you can route all of the important nodes in the device out to your logic analyzer and change between different sets of test signals in real-time by just putting in a little serial port control program or even by setting jumpers on the board.
> 
> As far as the impossibility of doing this with a "complex" design, I've got an XC2V1500 about 70% full and I've never simulated any of it. This includes a custom soft processor, Viterbi and Reed Solomon encoder, etc. It's not exactly rocket science but it's not 2k territory either.
> 
> Another thing -- as a system becomes more complex, simulations become less viable. Just ask any weatherman or climatologist. Okay, so an FPGA isn't a chaotic system but it still applies. At what point does it become such a pain to simulate all the various interfaces with sufficient fidelity that you're better off just trying it in the hardware? How often have you had a problem in the hardware and it turns out to be something you never even THOUGHT to simulate?

Article: 74648
Subject: Re: direct calculation of the modulus ?
From: ccon67@netscape.net (Marlboro)
Date: 15 Oct 2004 11:04:15 -0700
Links: << >>  << T >>  << A >>
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<55kum0lpfu23e8darsn23f8ugk8gookr5k@4ax.com>...
> On 14 Oct 2004 18:38:32 -0700, john.l.smith@titan.com (John) wrote:
> 
> >shankar.sb@gmail.com (Shankar B) wrote in message news:<b1296d94.0410132245.200a7019@posting.google.com>...
> >> > >mete wrote:
> >> > >
> >> > >> Is there method that is more efficient than regular division for
> >> > >> calculating modulus ?
> 
> [snip]
> 
> >John (always interested in these type circuits)
> 
> You might be interested in this thread:
> http://groups.google.com/groups?threadm=18c289aa.0304230854.6897fb3b%40posting.google.com
> which discusses a combinatorial circuit for evaluating a ten bit
> number mod 3 in a single CLB.
> 
> Regards,
> Allan

It's even simpler for mod 0, isn't it?  IHMO, ingeneral cases you
can't avoid the DIV operation or some agorithm similar to that,
cheers,

Article: 74649
Subject: XAPP253
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Fri, 15 Oct 2004 11:18:03 -0700
Links: << >>  << T >>  << A >>
I am trying to understand XAPP253, a DDR SRAM controller.  Is the use of a
RAM LUT still a good idea for transferring data from one clock domain to
another? I can't seem to run ModelSim. Is there some compatibility issue
with newer software?

Thanks,

b r a d @ a i v i s i o n . c o m





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