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Messages from 133650

Article: 133650
Subject: Altera FPGA and data from matlab workspace.
From: natarajan.jayaram@gmail.com
Date: Tue, 8 Jul 2008 07:27:54 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hey,

I need to send some data to the Altera Stratix II FPGA board from the
matlab workspace and then do some FFT, FIR process on that and then
return the data from the FPGA  back into the matlab workspace. How do
I do that? Kindly let me know if there is some tutorial which is
Altera specific on this which can tell me how to do it step by step.

Thanks and Regards,
Jayaram

Article: 133651
Subject: Spartan 3E I/O Pins -- LPC Bus Interface
From: Zhane <me75@hotmail.com>
Date: Tue, 8 Jul 2008 07:40:08 -0700 (PDT)
Links: << >>  << T >>  << A >>
Im trying to make a LPC bus interface to record the bus traffic as a
result of keypresses.

Im using the clk from the LPC bus as my process clock. But it seems
that the LFRAME# signal is always high and never drop low.

Im using the Expansion Connectors I/Os, accessory headers, on the
spartan 3e fpga to do the probing.

I'm not sure if the I/O pins Im using is appropriate. I'm using the J4
and J1 6-pin accessory header on the board to probe... with LVTTL as
my I/O standard.

Is it fast enough? cause the result of my output does not look like it
is appearing fast enough

Anyone has any idea what else I can do?


Article: 133652
Subject: How to download bitstream into Cyclone III starter board
From: "shivashankara" <shankaran.siva7@gmail.com>
Date: Tue, 08 Jul 2008 13:12:00 -0500
Links: << >>  << T >>  << A >>
Hi All,
I am migrating from Spartan 3e to Cyclone III. We bought only cyclone III
starter board. We don't have any USB blaster download cable.  I devloped
the my current design. Now i want to download into FPGA using USB cable. 
What are the steps to follow?

regards,
S Shankaran



Article: 133653
Subject: How do I send data and receive data from the FPGA and simulink/matlab
From: jaya <natarajan.jayaram@gmail.com>
Date: Tue, 8 Jul 2008 11:30:53 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi all,

I am using Altera DSP Builder to implement an OFDM receiver. I am
working on Stratix II Altera FPGA.I need to send data into the DAC (in
the FPGA board) from the matlab worspace and loop it to the ADC(on the
board) and then perform certian operations on the data in the FPGA and
route it back to the simulink/matlab worspace. Can I do it with the
JTAG cable? I want the final values in an array form in the matlab
workspace.

Thanks and Regards,
Jayaram

Article: 133654
Subject: 2 BUFIOs in the same clock-capable pair?
From: Pete <petersen.curt@gmail.com>
Date: Tue, 8 Jul 2008 12:55:30 -0700 (PDT)
Links: << >>  << T >>  << A >>
I have 2 clock inputs coming into the FPGA through a clock-capable IO
pair (AN19 and AN20).  The clock inputs are of the same frequency, but
not in phase.  Is it possible to route each through their own
IODELAYs, and BUFIOs, to separate local clock nets?  I want one clock
going to a bunch of ISERDES "CLK" ports and the other clock going to
the same ISERDES "CLKB" ports.


Here's some of my code:

    cq_IDELAY_INST: IDELAY
    generic map (
        IOBDELAY_TYPE => "VARIABLE"
    )
    port map (
        I => cq,
        O => cq_delayed,
        C => MemClk,
        CE => IDELAY_En(0),
        INC => IDELAY_Inc,
        RST => IDELAY_Rst(0)
    );
    cq_BUFIO_INST: BUFIO
    port map (
        I => cq_delayed,
        O => dq_rd_clk
    );

    cq_l_IDELAY_INST: IDELAY
    generic map (
        IOBDELAY_TYPE => "VARIABLE"
    )
    port map (
        I => cq_l,
        O => cq_l_delayed,
        C => MemClk,
        CE => IDELAY_En(1),
        INC => IDELAY_Inc,
        RST => IDELAY_Rst(1)
    );
    cq_l_BUFIO_INST: BUFIO
    port map (
        I => cq_l_delayed,
        O => dq_rd_clk_l
    );


    IO_DQ: for i in 0 to 17 generate

        dq_in_ISERDES_INST : ISERDES_NODELAY
        generic map(
            BITSLIP_ENABLE => FALSE,
            DATA_RATE => "DDR",
            DATA_WIDTH => 4,
            INIT_Q1 => '0',
            INIT_Q2 => '0',
            INIT_Q3 => '0',
            INIT_Q4 => '0',
            INTERFACE_TYPE => "MEMORY",
            NUM_CE => 2,
            SERDES_MODE => "MASTER")
        port map (
            BITSLIP => '0',
            CE1 => '1',
            CE2 => '1',
            CLK => dq_rd_clk,
            CLKB => dq_rd_clk_l,
            CLKDIV => MemClk,
            D => dq_in(i),
            OCLK => MemClk,
            RST => rst,
            SHIFTIN1 => '0',
            SHIFTIN2 => '0',
            Q1 => i_dq_in_falling(i), -- falling edge data
            Q2 => i_dq_in_rising(i), -- rising edge data
            SHIFTOUT1 =>open,
            SHIFTOUT2 =>open);
    end generate;


ISE is giving the following error in the MAP phase:



Running timing-driven packing...

Phase 1.1
ERROR:Place:730 - The I/O clock buffer (BUFIO) "sr0/cq_l_BUFIO_INST"
is driven
   by IODELAY component "sr0/cq_l_IDELAY_INST/IODELAY". The IODELAY
component
   must be placed into a clock capable I/O tile and the BUFIO
component must be
   placed into the corresponding BUFIO site. The following issue has
been
   detected:
   All of the logic associated with this structure is locked and the
relative
   placement of the logic violates the structure. The problem was
found between
   the relative placement of IODELAY sr0/cq_l_IDELAY_INST/IODELAY at
site
   IODELAY_X1Y100 and BUFIO sr0/cq_l_BUFIO_INST at site BUFIO_X1Y11.


I've LOCated my IODELAYs and BUFIOs to those components next to the
pads:


INST "sr0/cq_IDELAY_INST/IODELAY" LOC = "IODELAY_X1Y101" ;
INST "sr0/cq_BUFIO_INST" LOC = "BUFIO_X1Y10" ;
INST "sr0/cq_l_IDELAY_INST/IODELAY" LOC = "IODELAY_X1Y100" ;
INST "sr0/cq_l_BUFIO_INST" LOC = "BUFIO_X1Y11" ;
NET "sr0_cq_l" LOC = "AN19" ;
NET "sr0_cq" LOC = "AN20" ;


Does anyone have any suggestions?  I read in the Virtex-5 User Guide
that there are 4 clock nets per IO column.  I'm wondering if perhaps
my 2 BUFIO signals cannot be used at the same time, or if they can't
drive different local clock nets.

Article: 133655
Subject: Re: How to download bitstream into Cyclone III starter board
From: Lorenz Kolb <lorenz.kolb@uni-ulm.de>
Date: Tue, 08 Jul 2008 22:48:28 +0200
Links: << >>  << T >>  << A >>
shivashankara wrote:
> Hi All,
> I am migrating from Spartan 3e to Cyclone III. We bought only cyclone III
> starter board. We don't have any USB blaster download cable.  I devloped
> the my current design. Now i want to download into FPGA using USB cable. 
> What are the steps to follow?
> 
> regards,
> S Shankaran
> 
> 

I assume that what You do have is officially called "Cyclone III Starter 
FPGA Kit" - right?

There is quite a good step-by-strep guide for a own design at: 
http://nioswiki.jot.com/WikiHome/Cyclone%20III%20-%20Nios%20II%20-%20Starter%20board

You can also have a look at it's greater brother the "Nios II Embedded 
Evaluation Kit, Cyclone III Edition" (you can download an example design 
from Terasic which even includes the SDRam.

For actually downloading the bitfile there are quite a few methods, 
either if Your design features the "remote update" IP-Core via remote 
update or via serial or parallel programming pins which can be reused 
later (see the nioswiki from above for a detailed step-by-step-guide).

Regards,

Lorenz


Article: 133656
Subject: How can I create a direct FSL connection?
From: james <james@email.com>
Date: Tue, 8 Jul 2008 16:54:45 -0500
Links: << >>  << T >>  << A >>
Hi all ... I'm new to using Xilinx's EDK (version 10.1.02) and could 
use a little help.

I'd like to create a direct FSL connection between a MicroBlaze 
processor and a peripheral.  I  generated the peripheral using the 
"create peripheral" functionality and specified a FSL bus.  I have also 
enabled an "FSL link" under the "Buses" tab in my MicroBlaze 
configuration.  However, I can't seem to figure out how to create a 
"Direct FSL connection" (p.84 in MicroBlaze Processor Reference Guide 
(v9.2)) between the two.  I can only connect them via a buffered FSL 
bus, which isn't what I want.

I've read what little documentation is provided regarding the "Direct 
FSL connection" and it is of little help.  Does anyone have some tips 
or insight into what I might be doing wrong?

Any help would be greatly appreciated.
Thanks,
James


Article: 133657
Subject: Re: 2 BUFIOs in the same clock-capable pair?
From: Yottameter <yottameter@yahoo.com>
Date: Tue, 08 Jul 2008 15:48:38 -0700
Links: << >>  << T >>  << A >>
Looks like you want to use the 2 clock DDR mode, not the DDR mode. I 
think the DATA_RATE option needs to be changed, but I'm not quite sure 
on what the value is. I'm assuming you are trying to correct for duty 
cycle distortion internal to the chip.



Pete wrote:
> I have 2 clock inputs coming into the FPGA through a clock-capable IO
> pair (AN19 and AN20).  The clock inputs are of the same frequency, but
> not in phase.  Is it possible to route each through their own
> IODELAYs, and BUFIOs, to separate local clock nets?  I want one clock
> going to a bunch of ISERDES "CLK" ports and the other clock going to
> the same ISERDES "CLKB" ports.
> 
> 
> Here's some of my code:
> 
>     cq_IDELAY_INST: IDELAY
>     generic map (
>         IOBDELAY_TYPE => "VARIABLE"
>     )
>     port map (
>         I => cq,
>         O => cq_delayed,
>         C => MemClk,
>         CE => IDELAY_En(0),
>         INC => IDELAY_Inc,
>         RST => IDELAY_Rst(0)
>     );
>     cq_BUFIO_INST: BUFIO
>     port map (
>         I => cq_delayed,
>         O => dq_rd_clk
>     );
> 
>     cq_l_IDELAY_INST: IDELAY
>     generic map (
>         IOBDELAY_TYPE => "VARIABLE"
>     )
>     port map (
>         I => cq_l,
>         O => cq_l_delayed,
>         C => MemClk,
>         CE => IDELAY_En(1),
>         INC => IDELAY_Inc,
>         RST => IDELAY_Rst(1)
>     );
>     cq_l_BUFIO_INST: BUFIO
>     port map (
>         I => cq_l_delayed,
>         O => dq_rd_clk_l
>     );
> 
> 
>     IO_DQ: for i in 0 to 17 generate
> 
>         dq_in_ISERDES_INST : ISERDES_NODELAY
>         generic map(
>             BITSLIP_ENABLE => FALSE,
>             DATA_RATE => "DDR",
>             DATA_WIDTH => 4,
>             INIT_Q1 => '0',
>             INIT_Q2 => '0',
>             INIT_Q3 => '0',
>             INIT_Q4 => '0',
>             INTERFACE_TYPE => "MEMORY",
>             NUM_CE => 2,
>             SERDES_MODE => "MASTER")
>         port map (
>             BITSLIP => '0',
>             CE1 => '1',
>             CE2 => '1',
>             CLK => dq_rd_clk,
>             CLKB => dq_rd_clk_l,
>             CLKDIV => MemClk,
>             D => dq_in(i),
>             OCLK => MemClk,
>             RST => rst,
>             SHIFTIN1 => '0',
>             SHIFTIN2 => '0',
>             Q1 => i_dq_in_falling(i), -- falling edge data
>             Q2 => i_dq_in_rising(i), -- rising edge data
>             SHIFTOUT1 =>open,
>             SHIFTOUT2 =>open);
>     end generate;
> 
> 
> ISE is giving the following error in the MAP phase:
> 
> 
> 
> Running timing-driven packing...
> 
> Phase 1.1
> ERROR:Place:730 - The I/O clock buffer (BUFIO) "sr0/cq_l_BUFIO_INST"
> is driven
>    by IODELAY component "sr0/cq_l_IDELAY_INST/IODELAY". The IODELAY
> component
>    must be placed into a clock capable I/O tile and the BUFIO
> component must be
>    placed into the corresponding BUFIO site. The following issue has
> been
>    detected:
>    All of the logic associated with this structure is locked and the
> relative
>    placement of the logic violates the structure. The problem was
> found between
>    the relative placement of IODELAY sr0/cq_l_IDELAY_INST/IODELAY at
> site
>    IODELAY_X1Y100 and BUFIO sr0/cq_l_BUFIO_INST at site BUFIO_X1Y11.
> 
> 
> I've LOCated my IODELAYs and BUFIOs to those components next to the
> pads:
> 
> 
> INST "sr0/cq_IDELAY_INST/IODELAY" LOC = "IODELAY_X1Y101" ;
> INST "sr0/cq_BUFIO_INST" LOC = "BUFIO_X1Y10" ;
> INST "sr0/cq_l_IDELAY_INST/IODELAY" LOC = "IODELAY_X1Y100" ;
> INST "sr0/cq_l_BUFIO_INST" LOC = "BUFIO_X1Y11" ;
> NET "sr0_cq_l" LOC = "AN19" ;
> NET "sr0_cq" LOC = "AN20" ;
> 
> 
> Does anyone have any suggestions?  I read in the Virtex-5 User Guide
> that there are 4 clock nets per IO column.  I'm wondering if perhaps
> my 2 BUFIO signals cannot be used at the same time, or if they can't
> drive different local clock nets.

Article: 133658
Subject: Re: SBC with ADC, 1GE, and SATA2?
From: John Adair <g1@enterpoint.co.uk>
Date: Tue, 8 Jul 2008 15:58:08 -0700 (PDT)
Links: << >>  << T >>  << A >>
Mike

It's just possible that a couple of products that we in the pipeline
might be close enough to meet your needs. I can let out the secret
that they are FPGA based. I'm sure that surprised everyone on this
group. Proper launch of these in September when everyone is back from
their hols. So if you can wait that long keep an eye out for the press
releases.

Details of our current board products http://www.enterpoint.co.uk/boardprod=
ucts.html
if want to have a look at what we already do.

John Adair
Enterpoint Ltd. - Home of Darnaw1. The PGA FPGA Solution.


On 7 Jul, 22:59, mike...@mikemac.com (Mike McDonald) wrote:
> =A0 I'm lokking for a small (4x6", 6x8", range) SBC that has a reasonably=
 good A/D converter (100+MSPS),
> at least one 1G ethernet, and one or more SATA-2 ports. I'm not picky abo=
ut the processor. Anything that
> runs Linux or an FPGA would be fine. A nice option would be an LCD and ke=
ypad interface.
>
> =A0 Has anyone got any recommendations? All of my Google queries are poss=
essed! I keep getting the same
> wedsite under 15 different names that only has 6U and bigger boards.
>
> --
>
> =A0 Mike McDonald
> =A0 mike...@mikemac.com


Article: 133659
Subject: Re: ISE Simulator
From: kumarator@gmail.com
Date: Tue, 8 Jul 2008 18:41:10 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 5, 2:36=A0am, meralonu...@gmail.com wrote:
> Xilinx ISE 9.2 and 10.1 =A0(Webpack)
>
> signal cntr: integer range 0 to 3;
> ...
> if(clk'event and clk=3D'1') then cntr<=3Dcntr+1; end if;
> inferres 2 FFs as I see from the RL schematics.
> But when I try to simulate, the simulator does not recognize any upper
> limit. That is, it counts limitlessly.
> I am a beginner. What is the problem?
> Thanks.

Hi,

ISE Simulator has simulation run time value range check turned off by
default, hence you do not see your out of range value being detected
and reported as error.

If you are using ISE 9.2, please do following to turn the value range
check on:

1) Right click on "Simulate Behavioral Model" and select
"Properties.."
2) On the Properties dialog set the "Propert display level" to
Advanced
3) You will see a Property named "Value Range Check". Select the box
against this property to turn the value range check on.

If you are a command line user, type fuse -help and you will see that
there is a switch called -rangecheck that turns on the value range
check. Use this switch and you would see value range check being
performed during simulation.

Generaly speaking, ISE 10.1 verison of ISE simulator is hugely
improved in quality and speed over ISE 9.2 version of the simulator;
However, I have to admit that 10.1 ISim does have run time value
rangecheck broken. We are going to fix the broken value range check in
10.1 Service pack 3.

Thank you for using ISim (SE Simulator) and providing this feedback!
Kumar (ISE Simulator team)



Article: 133660
Subject: JTAG IR length detection
From: slide_o_mix <slide.o.mix@gmail.com>
Date: Tue, 8 Jul 2008 18:44:27 -0700 (PDT)
Links: << >>  << T >>  << A >>
We are currently building a board at work that will have connectors
for X number of boards (that is between 0 and the number of connectors
on the board) which will have FPGAs on them. We are looking at using
different types of FPGAs for price reasons on different boards (make
some boards cheaper than others etc). My task is to provide an in
circuit FPGA configuration mechanism (we're looking at using Xilinx
mostly for now) using JTAG. I have the code which successfully goes
out and determines the number of devices in the scan chain, but am
having difficulty determining how to detect the size of the
instruction register for each device. Can someone point me to some
code?

Thanks,

slide

Article: 133661
Subject: Help =(
From: Zhane <me75@hotmail.com>
Date: Tue, 8 Jul 2008 20:23:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
I've problem with my codes.

I'm trying to make a LPC Bus interface with my Spartan 3E to tap the
bus traffic coming from keypresses.

I'm using the LCLK from the bus and the FPGA 50Mhz clock for my
processes. I'm using those expansion connectors to probe the bus,
storing it into a 2-clock FIFO, and a uart which reads from the FIFO
and send it to the PC

I've simulated it on my modelsim and it come out as desired, but when
I try out on the actual thing...the uart data is weird.

I've modified my code to only allow 2 kind of data to be sent out.
"00000000" will be sent out every 13 cycles, while during the 13
cycles it will be the other set of data, "01111111". However the data
I collected doesnt appear to be so.

http://www.savefile.com/files/1655663 << Log file from programming of
FPGA
http://www.savefile.com/files/1655664 << my source codes

Pls help me... I'm at my wits

Article: 133662
Subject: Help Needed - LPC Bus Interface
From: Zhane <me75@hotmail.com>
Date: Tue, 8 Jul 2008 20:28:18 -0700 (PDT)
Links: << >>  << T >>  << A >>
I've problem with my codes.

I'm trying to make a LPC Bus interface with my Spartan 3E to tap the
bus traffic coming from keypresses.

I'm using the LCLK from the bus and the FPGA 50Mhz clock for my
processes. I'm using those expansion connectors to probe the bus,
storing it into a 2-clock FIFO, and a uart which reads from the FIFO
and send it to the PC

I've simulated it on my modelsim and it come out as desired, but when
I try out on the actual thing...the uart data is weird.

I've modified my code to only allow 2 kind of data to be sent out.
"00000000" will be sent out every 13 cycles, while during the 13
cycles it will be the other set of data, "01111111". However the data
I collected doesnt appear to be so.

http://www.savefile.com/files/1655663 << Log file from programming of
FPGA
http://www.savefile.com/files/1655664 << my source codes

Pls help me... I'm at my wits

Article: 133663
Subject: Re: Spartan 3E I/O Pins -- LPC Bus Interface
From: Zhane <me75@hotmail.com>
Date: Tue, 8 Jul 2008 23:38:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 8, 10:40=A0pm, Zhane <m...@hotmail.com> wrote:
> Im trying to make a LPC bus interface to record the bus traffic as a
> result of keypresses.
>
> Im using the clk from the LPC bus as my process clock. But it seems
> that the LFRAME# signal is always high and never drop low.
>
> Im using the Expansion Connectors I/Os, accessory headers, on the
> spartan 3e fpga to do the probing.
>
> I'm not sure if the I/O pins Im using is appropriate. I'm using the J4
> and J1 6-pin accessory header on the board to probe... with LVTTL as
> my I/O standard.
>
> Is it fast enough? cause the result of my output does not look like it
> is appearing fast enough
>
> Anyone has any idea what else I can do?

I've changed the stuffs slightly.

I'm using the LCLK from the bus and the FPGA 50Mhz clock for my
processes. I'm using those expansion connectors to probe the bus,
storing it into a 2-clock FIFO, and a uart which reads from the FIFO
and send it to the PC

I've simulated it on my modelsim and it come out as desired, but when
I try out on the actual thing...the uart data is weird.

I've modified my code to only allow 2 kind of data to be sent out.
"00000000" will be sent out every 13 cycles, while during the 13
cycles it will be the other set of data, "01111111". However the data
I collected doesnt appear to be so.

http://www.savefile.com/files/1655663 << Log file from programming of
FPGA
http://www.savefile.com/files/1655664 << my source codes

Pls help me... I'm at my wits

Article: 133664
Subject: Can I store the output of my FPGA logic inside FPGA memory for debug
From: vlsi_learner <bajajk@gmail.com>
Date: Wed, 9 Jul 2008 02:00:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

I am using altera FPGA.

How can I put the output of my logic into the FPGA internal
memories(assuming I have unused memories available)?

Article: 133665
Subject: Re: HWICAP initialization
From: lixia.rem@gmail.com
Date: Wed, 9 Jul 2008 02:00:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 6=D4=C21=C8=D5, =CF=C2=CE=E77=CA=B159=B7=D6, Atukem <atu...@googlemail.c=
om> wrote:
> On May 27, 1:55 pm, fmostafa <fatma.abouele...@ugent.be> wrote:
>
> > hi all,
>
> > I am trying to use HWICAP to configure  certain LUTs , I guess that
> > starting with the examples from XILINX will be a good start, the
> > problem that after many trials and of course nothing working, I
> > noticed that the DONE bit which in  the status reg in the HWICAP is
> > low all the time so nothing is working, but before calling  the
> > function XHwIcap_Initialize the Done bit is high , I don't know if
> > what I noticed is really a problem as I guess or not, I am using EDK
> > 9.1 and XUP board for XC2VP30 under Linux, I don't may be the problem
> > in Linux or some thing else.
>
> > thanks
>
> > fatma
>
> Could you give a little bit more detail about you system, when it
> stops working, does it actually complete the initialisation process, I
> guess you might be using microblaze ....

hi fatma,
i have the same problem with Atukem,and it hanppens when call
XHwicap_DeviceRead function,the return value is "Device is busy".So,in
fact,the initialisation process is not complete successfully.
the value of M0M1M2 should be set only through the switches on the
board or both in the gitgen.ut file? Is there anything else shoule be
noticed except the value of M0M1M2 and persist?

Article: 133666
Subject: Re: Virtex 4 expected production end-of-life
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Wed, 09 Jul 2008 04:28:57 -0500
Links: << >>  << T >>  << A >>

>Thanks Peter and all who replied.  That's reassuring then so we'll continue
>on the path we're taking.  As you say, with 18 months in NFND we can do a
>lot in that time (including go out of business ;) ), and as someone 
>else pointed out it is really a matter of pushing the redevelopment 
>costs out into the future or facing them now.  Future's definitely
>better.

There is another option to add to your list.

If you still have products in production using a chip that goes
EOL, buy a lot of them, say enough for 10 more years.  Maybe
round up a bit.

This obviously works better if you can accurately estimate
your production volumes and/or know how long you want to
sell those products.


-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 133667
Subject: Re: Altera FPGA and data from matlab workspace.
From: kclo4 <alexis.gabin@gmail.com>
Date: Wed, 9 Jul 2008 02:55:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 8, 10:27 pm, natarajan.jaya...@gmail.com wrote:
> Hey,
>
> I need to send some data to the Altera Stratix II FPGA board from the
> matlab workspace and then do some FFT, FIR process on that and then
> return the data from the FPGA  back into the matlab workspace. How do
> I do that? Kindly let me know if there is some tutorial which is
> Altera specific on this which can tell me how to do it step by step.
>
> Thanks and Regards,
> Jayaram

What is your board?? What are your bandwidth need? Personally I used a
RS232 it is easy to implement on both FPGA and matlab but it's slow so
I use it only for debugging.

Article: 133668
Subject: Re: SBC with ADC, 1GE, and SATA2?
From: kclo4 <alexis.gabin@gmail.com>
Date: Wed, 9 Jul 2008 03:08:24 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 8, 5:59 am, mike...@mikemac.com (Mike McDonald) wrote:
>   I'm lokking for a small (4x6", 6x8", range) SBC that has a reasonably good A/D converter (100+MSPS),
> at least one 1G ethernet, and one or more SATA-2 ports. I'm not picky about the processor. Anything that
> runs Linux or an FPGA would be fine. A nice option would be an LCD and keypad interface.
>
>   Has anyone got any recommendations? All of my Google queries are possessed! I keep getting the same
> wedsite under 15 different names that only has 6U and bigger boards.
>
> --
>
>   Mike McDonald
>   mike...@mikemac.

First you need to know which technology you want to use because FPGA
and CPU are completely different!! Then what is your budget? I don't
think you can expect to find something cheap with a 100msps A/D
converter (by the way how many bits for the ADC ?) There is some
development kit available from both xilinx and altera that can fit
most of your need (including FPGA +ADC up to 125MSPS) of you can also
take a normal FPGA board and buy a develpment kit from analog device
with the ADC you want (others ADC company may also make dev kit)

Article: 133669
Subject: Configure registers of CMOS Sensor by Spartan3
From: Kicn <Kicn2008@gmail.com>
Date: Wed, 09 Jul 2008 18:50:40 +0800
Links: << >>  << T >>  << A >>
Hi, I am trying to configure the registers on the MT9T001 Image sensor 
using a Spartan3 board.

I fed a 50MHz to the SCLK, the SDATA is pull-up by 3.3V, and after 
feeding the start bit and 16bit address, it does not reply with an 
acknowledge bit. I read the acknowledge by setting the I/O as 'Z'. I am 
wondering if I am doing the tri-state correctly.

Thanks.

A fragment of my codes...

signal msgb : std_logic :='0';
cam_sdata<=msgb;
process(clk50M)
begin
	if rising_edge(clk50M)
	then
		if state=1 then
			msgb<='1'; --from HIGH
			state<=2;
			
		elsif state=2 then
			msgb<=addr1(ctr1); --register address, 0xBA
			ctr1<=ctr1-1;
			if ctr1<0 then
				state<=3;
				msgb<='Z'; -- for ack
			end if;
			
		elsif state=3 then
			msgb<='Z'; -- for ack
			if revb='0' then --ack
				state<=4;
				ctr1<=7; -- for next state
			end if;
			
		elsif state=4 then
			msgb<=reg1(ctr1); -- write value to register
			ctr1<=ctr1-1;
			if ctr1=0 then
				state<=6;
				msgb<='Z'; -- for ack
			end if;
			
		end if;
	end if;
end process;

-kicn

Article: 133670
Subject: Regarding Xilinx tool
From: vignesh_karthi <pvprabhuraj@gmail.com>
Date: Wed, 9 Jul 2008 04:26:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
 My name is vignesh.

 I am also new guy to Xilinx .. i want to know the following things...
please help me...

1. how can i create the *.ucf file using xilinx Tool ? (if you have
provide me )

2. how can i avoid the multicycle path and false path ? (if you have
provide me )

3. Do you have any basic user manual for xilinx tool ? (if you have
provide me )


Advanced Thanks to you...

Article: 133671
Subject: Xilinx ISE impact outputs bad idcode when in batch mode but works in
From: axr0284 <axr0284@yahoo.com>
Date: Wed, 9 Jul 2008 05:45:55 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

 I am trying to create a batch file to load a bit file into an FPGA
(Spartan 3E 500 -5 PQ208). I used the following commands:

setMode -bscan
setCable -p auto
addDevice -p 1 -file "C:\perforce\depot\eni\eng\projects\DEV\E9352_MOAC
\P01_System_Controller_FPGA\Src\synthesis\blank_fpga\blank_fpga.bit"
program p 1



Impact outputs the following:

...

...

...

>addDevice -p 1 -file "C:\perforce\depot\eni\eng\projects\DEV\E9352_MOAC\P01_System_Controller_FPGA\Src\synthesis\blank_fpga\blank_fpga.bit"
'1': Loading file
'C:\perforce\depot\eni\eng\projects\DEV\E9352_MOAC
\P01_System_Controller_FPGA\Src\synthesis\blank_fpga
\blank_fpga.bit' ...

done.
INFO:iMPACT:1777 -
   Reading C:/Xilinx92i/spartan3e/data/xc3s500e.bsd...

INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the
bitstream
   stored in memory,
   but the original bitstream file remains unchanged.
INFO:iMPACT:501 - '1': Added Device xc3s500e successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------

>program -p 1
ERROR:iMPACT:583 - '1': The idcode read from the device does not match
the
   idcode in the bsdl File.
INFO:iMPACT:1578 - '1':  Device IDCODE :
00000011100001000100000100100110

INFO:iMPACT:1579 - '1': Expected IDCODE:
00000001110000100010000010010011
Elapsed time =      0 sec.



The weird thing is if I go through the GUI, it works fine. I am
wondering if anybody has seen this before. Thanks,

Amish

Article: 133672
Subject: Re: Regarding Xilinx tool
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 9 Jul 2008 14:05:08 +0100
Links: << >>  << T >>  << A >>

"vignesh_karthi" <pvprabhuraj@gmail.com> wrote in message 
news:ecf5b59d-ba57-4c5f-9b30-93f0ff38e2f6@59g2000hsb.googlegroups.com...
> My name is vignesh.
>
> I am also new guy to Xilinx .. i want to know the following things...
> please help me...
>
> 1. how can i create the *.ucf file using xilinx Tool ? (if you have
> provide me )
>
> 2. how can i avoid the multicycle path and false path ? (if you have
> provide me )
>
> 3. Do you have any basic user manual for xilinx tool ? (if you have
> provide me )
>
>
> Advanced Thanks to you...

Hi Vignesh,

In a Windows environment, follow this procedure.

start -> All Programs -> Xilinx ISE -> Documentation -> Software manuals

Look at the contraints guide and the Development system reference.

I hope this has provided you Advanced Help.

Syms.


p.s. You might like to try this link to help you in future...
http://catb.org/~esr/faqs/smart-questions.html
and more particularly...
http://catb.org/~esr/faqs/smart-questions.html#rtfm 



Article: 133673
Subject: Re: JTAG IR length detection
From: Gabor <gabor@alacron.com>
Date: Wed, 9 Jul 2008 06:41:12 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 8, 9:44 pm, slide_o_mix <slide.o....@gmail.com> wrote:
> We are currently building a board at work that will have connectors
> for X number of boards (that is between 0 and the number of connectors
> on the board) which will have FPGAs on them. We are looking at using
> different types of FPGAs for price reasons on different boards (make
> some boards cheaper than others etc). My task is to provide an in
> circuit FPGA configuration mechanism (we're looking at using Xilinx
> mostly for now) using JTAG. I have the code which successfully goes
> out and determines the number of devices in the scan chain, but am
> having difficulty determining how to detect the size of the
> instruction register for each device. Can someone point me to some
> code?
>
> Thanks,
>
> slide

Can you detect the size of the instruction register?  Xilinx iMpact
software
seems to need you to enter this or use a pre-built BSDL file for the
device
you found.

Article: 133674
Subject: Re: 2 BUFIOs in the same clock-capable pair?
From: Gabor <gabor@alacron.com>
Date: Wed, 9 Jul 2008 06:48:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 8, 6:48 pm, Yottameter <yottame...@yahoo.com> wrote:
> Looks like you want to use the 2 clock DDR mode, not the DDR mode. I
> think the DATA_RATE option needs to be changed, but I'm not quite sure
> on what the value is. I'm assuming you are trying to correct for duty
> cycle distortion internal to the chip.
>
> Pete wrote:
> > I have 2 clock inputs coming into the FPGA through a clock-capable IO
> > pair (AN19 and AN20).  The clock inputs are of the same frequency, but
> > not in phase.  Is it possible to route each through their own
> > IODELAYs, and BUFIOs, to separate local clock nets?  I want one clock
> > going to a bunch of ISERDES "CLK" ports and the other clock going to
> > the same ISERDES "CLKB" ports.
>
> > Here's some of my code:
>
> >     cq_IDELAY_INST: IDELAY
> >     generic map (
> >         IOBDELAY_TYPE => "VARIABLE"
> >     )
> >     port map (
> >         I => cq,
> >         O => cq_delayed,
> >         C => MemClk,
> >         CE => IDELAY_En(0),
> >         INC => IDELAY_Inc,
> >         RST => IDELAY_Rst(0)
> >     );
> >     cq_BUFIO_INST: BUFIO
> >     port map (
> >         I => cq_delayed,
> >         O => dq_rd_clk
> >     );
>
> >     cq_l_IDELAY_INST: IDELAY
> >     generic map (
> >         IOBDELAY_TYPE => "VARIABLE"
> >     )
> >     port map (
> >         I => cq_l,
> >         O => cq_l_delayed,
> >         C => MemClk,
> >         CE => IDELAY_En(1),
> >         INC => IDELAY_Inc,
> >         RST => IDELAY_Rst(1)
> >     );
> >     cq_l_BUFIO_INST: BUFIO
> >     port map (
> >         I => cq_l_delayed,
> >         O => dq_rd_clk_l
> >     );
>
> >     IO_DQ: for i in 0 to 17 generate
>
> >         dq_in_ISERDES_INST : ISERDES_NODELAY
> >         generic map(
> >             BITSLIP_ENABLE => FALSE,
> >             DATA_RATE => "DDR",
> >             DATA_WIDTH => 4,
> >             INIT_Q1 => '0',
> >             INIT_Q2 => '0',
> >             INIT_Q3 => '0',
> >             INIT_Q4 => '0',
> >             INTERFACE_TYPE => "MEMORY",
> >             NUM_CE => 2,
> >             SERDES_MODE => "MASTER")
> >         port map (
> >             BITSLIP => '0',
> >             CE1 => '1',
> >             CE2 => '1',
> >             CLK => dq_rd_clk,
> >             CLKB => dq_rd_clk_l,
> >             CLKDIV => MemClk,
> >             D => dq_in(i),
> >             OCLK => MemClk,
> >             RST => rst,
> >             SHIFTIN1 => '0',
> >             SHIFTIN2 => '0',
> >             Q1 => i_dq_in_falling(i), -- falling edge data
> >             Q2 => i_dq_in_rising(i), -- rising edge data
> >             SHIFTOUT1 =>open,
> >             SHIFTOUT2 =>open);
> >     end generate;
>
> > ISE is giving the following error in the MAP phase:
>
> > Running timing-driven packing...
>
> > Phase 1.1
> > ERROR:Place:730 - The I/O clock buffer (BUFIO) "sr0/cq_l_BUFIO_INST"
> > is driven
> >    by IODELAY component "sr0/cq_l_IDELAY_INST/IODELAY". The IODELAY
> > component
> >    must be placed into a clock capable I/O tile and the BUFIO
> > component must be
> >    placed into the corresponding BUFIO site. The following issue has
> > been
> >    detected:
> >    All of the logic associated with this structure is locked and the
> > relative
> >    placement of the logic violates the structure. The problem was
> > found between
> >    the relative placement of IODELAY sr0/cq_l_IDELAY_INST/IODELAY at
> > site
> >    IODELAY_X1Y100 and BUFIO sr0/cq_l_BUFIO_INST at site BUFIO_X1Y11.
>
> > I've LOCated my IODELAYs and BUFIOs to those components next to the
> > pads:
>
> > INST "sr0/cq_IDELAY_INST/IODELAY" LOC = "IODELAY_X1Y101" ;
> > INST "sr0/cq_BUFIO_INST" LOC = "BUFIO_X1Y10" ;
> > INST "sr0/cq_l_IDELAY_INST/IODELAY" LOC = "IODELAY_X1Y100" ;
> > INST "sr0/cq_l_BUFIO_INST" LOC = "BUFIO_X1Y11" ;
> > NET "sr0_cq_l" LOC = "AN19" ;
> > NET "sr0_cq" LOC = "AN20" ;
>
> > Does anyone have any suggestions?  I read in the Virtex-5 User Guide
> > that there are 4 clock nets per IO column.  I'm wondering if perhaps
> > my 2 BUFIO signals cannot be used at the same time, or if they can't
> > drive different local clock nets.

My understanding of clock inputs for Virtex 5 is that you can only use
the positive side of the pair.  The other input is only "clock
capable"
when used as the other half of the differential pair.  So if your
clocks
are single-ended, you may need to use another pin or find another
workaround.

Regards,
Gabor



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