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Messages from 111950

Article: 111950
Subject: IEEE 1149.6 support in Virtex-5
From: "Antti" <Antti.Lukats@xilant.com>
Date: 13 Nov 2006 09:37:36 -0800
Links: << >>  << T >>  << A >>
Hi

Virtex-5 seems to support AC/differential signal debugging via JTAG
scan but I am not finding any closer documentation about it in Xilinx
docs?

is some document just not yet published or =EDs the 1149.6 support not
working and has been obmitted from the documents (like the EFUSE what
is in silicon? but apparently not working)

Antti


Article: 111951
Subject: Compile error by Cadence NC-Sim
From: "uvbaz" <uvbaz@stud.uni-karlsruhe.de>
Date: 13 Nov 2006 09:41:21 -0800
Links: << >>  << T >>  << A >>
hi, everyone,

I want to compile two VHDL-Code, and the Xilinx simprim library into my
design.

1. hdl.var:
DEFINE WORK worklib
DEFINE LIB_MAP($LIB_MAP, \
               $XILINX/verilog/src/simprims => SIMPRIM_VER, \

               src/fprint.vhd => FPRINT, \
               src/fprint_body.vhd => FPRINT)


2. cds.lib
SOFTINCLUDE .../cds.lib
DEFINE std ...
...
DEFINE worklib /.../publib/worklib
DEFINE SIMPRIM_VER /.../publib/simprim_ver
DEFINE FPRINT /.../publib/fprint

3. ncvlog.options
-messages
-status
-sv31a
-linedebug
-cdslib cds.lib    // Use the specified cds.lib file
-hdlvar hdl.var    // Use the specified hdl.var file
-logfile ncvlog.log
// Files to be compiled:
$XILINX/verilog/src/simprims/*.v

4. ncvhdl.options
-messages
-status
-v93
-linedebug
-assert
-cdslib cds.lib
-hdlvar hdl.var
-logfile ncvhdl.log

// Files to be compiled:
src/fprint.vhd
src/fprint_body.vhd

5. c-shell script under unix
#!/bin/csh -f
clear
ncvlog -f ncvlog.options           # Compile the verilog files
ncvhdl -f ncvhdl.options           # Compile the vhdl files

There are two points, i cant understand:
1. fprint.vhd + fprint_body.vhd were compiled, but put to the WORK,
however, i want it in FPRINT
2. $XILINX/verilog/src/simprims/*.v cant be compiled, an error: ncvlog:
*E,BADFIL: invalid file:
/design/software/XILINX/ISE/8.2i-SP1/verilog/src/simprims (not a
regular file)

Thanks for your answer, :)

Regard,
Cheng


Article: 111952
Subject: Re: FPGA Debug Tool
From: Vivian Bessler <vivian.bessler.nospam@sandbyte.com>
Date: Mon, 13 Nov 2006 17:48:34 +0000
Links: << >>  << T >>  << A >>
Hi Antti,
Apologies for the typo.  I'm surprised to hear you had difficulties with 
FPGAXpose.  FPGAXpose is definitely a product that works.  If you pass 
on more details about the error I'll submit a support request and get it 
sorted (if it still exists in the latest version).  Regarding the 
customer list, I was only trying to check the version you evaluated in 
order to see if there were bugs filed against it.

Vivian


Antti wrote:
> Vivian Bessler schrieb:
> 
> 
>>Hi Annti,
>>I don't see your name among our evaluation or full license users.
>>
>>If you need any assistance our support team will be happy to help you out.
>>
>>Vivian
> 
> 
> hi Vivian
> 
> 1 my name first name is Antti
> 2 to my understanding the usual policy of online licensing is that the
> information submitted is handled as confidential. So your public post
> about my name being or not being on the list of the people who have
> submitted data to your website is either violation of such common
> confidentiality policy or your company doesnt have such policy at all.
> 
> ...
> 
> There are tools that work.
> And there are tools that do not.
> 
> Getting the JTAG communication to work with Cable III is something that
> is REALLY easy to handle. I was hoping to see some real results, but
> only witnessed cable communication faults. Not very promising.
> 
> Antti
> 

Article: 111953
Subject: Re: Xilinx USB cable - can't install driver
From: "uvbaz" <uvbaz@stud.uni-karlsruhe.de>
Date: 13 Nov 2006 09:58:24 -0800
Links: << >>  << T >>  << A >>
You should reinstall it, and update the firmware.  <== You can try it,
i am NOT sure. This has also happend by me, but i cant remember clearly
what i've done.: (

Regard,
Cheng

c d saunter schrieb:

> zwsdotcom@gmail.com wrote:
> : This used to work! I've had it put away for a couple of weeks, and now
> : when I plug in the Platform cable it tries to reinstall the driver and
> : when it gets to the second stage (after installing the firmware
> : loader), Windows says that a service installation section in the INF
> : file was invalid.
>
> : Anyone ever seen this before?! How do I fix it?
>
> I'd wait for other suggestions before trying this, but if all else fails
> you can roll back the configuration of XP to before it broke with the
> 'System Restore' feature - http://en.wikipedia.org/wiki/System_Restore
>
> This sucesfully pulled my machine back from the edge when I had some very
> strange USB problems...
> 
> cds


Article: 111954
Subject: Re: SPI module in FPGA
From: "Paul" <pauljbennett@gmail.com>
Date: 13 Nov 2006 10:04:55 -0800
Links: << >>  << T >>  << A >>
You might consider looking at an example on opencores.org to get ya
start, pretty sure they've got an SPI interface.

As for the clock, you can easily divide down your main processor clk
with a few registers, or I imagine the cyclone's have something
analagous to Xilinx's digital clock manager, which lets ya do all sorts
of fun multiplies and divides and things (with the penalty of some
jitter of course).

given the minimal amount of resources it takes - a shift register and a
very tiny amount of control (well.. i guess a shift register is the
receive side, the write side is just a parallel data register and a
mux) i doubt you'll find it worth tying up your processor everytime you
wanna send out some data, unless you're REALLY hard up for that fpga
fabric.... especially since it's probably a rather slow interface that
isnt gonna place a whole lot of timing constraints on the design in
terms of place and route. (i.e. could probably occupy space wherever
the unused resources happen to be, while placement on something like
your processor will be far more critical)

alterauser wrote:
> @firebird:
>
> Typically, the "SPI-interface" of ADCs ist nothing more than a shift
> register carrying out one bit per clock, so it is up to YOU which clock
> speed to choose. In very rare situations, you will create a unique and
> isolated design dealing with high speed ADCs and interfacing to the
> rest of the FPGA. But here, a counter and a bit-BUX should be all to be
> done. The counter should have a fixed relationship to your CPU master
> clock (one one clock domain simpler to handle) and an eye should be
> kept on the timing: Some ADCs respond e.g. on the falling edge of their
> local clock, and additional timing delays caused be drivers might will
> cause tricky edge constellations of data and sampling clock. To deal
> with this, I usually prepare a second clock in the FPGA running at the
> double frequency and driving the output registers (here ADC-clock
> driver).
>
> In a recent video design, the ADCs are fed with 100MHz clock speed
> (full FPGA speed) where the driving clock is passed through register
> FFs clocked with not200Mhz resulting in 25% additional delay and an
> perfect timing constellation between data signals and rising clock.


Article: 111955
Subject: Re: Virtex-4 : OCM
From: "Anonymous" <someone@microsoft.com>
Date: Mon, 13 Nov 2006 18:12:23 GMT
Links: << >>  << T >>  << A >>

"zyan" <czinyan1983@yahoo.com> wrote in message
news:eea051a.-1@webx.sUN8CHnE...
> Hi,
>
> I was trying to run a C program from the OCM BRAM. I have not incorporate
external memory to my design yet. I managed to download the ELF file using
XMD but it didn't run. When I type "stop", the message from XMD was "unable
to stop processor". What could be the problem? What are the settings
required in order to run program from OCM.
>
> Thanks.

I think OCM requires data and instruction memories. Do you have both? Also
the reset vector will be at the top of memory (0xfffffffc) so the I-OCM has
to be at least mapped to that range. (and, of course, your program has to
fit in the avialbale memory)

You also need to verify that xmd is actually attached. It should report a
port number like 1234 if it works. I frequently get lost in xmd and have to
close it and restart.

-Clark



Article: 111956
Subject: Re: Xilinx USB cable - can't install driver
From: Stephan Flock <sflock@freenet.de>
Date: Mon, 13 Nov 2006 19:12:31 +0100
Links: << >>  << T >>  << A >>
I've had a very strange effect with the Spartan-3E starter kit USB.
I would only be able to establish connection to the board via a small 
USB hub, but not with the board connected to the computer's USB port 
directly.
Seems like the USB hub has had some generic driver installed 
(beforehand), that disturbes the driver for the Xilinx USB cable.

Regards,
Stephan

Article: 111957
Subject: Re: MPMC2: MPMC2 with DDR2 SDRAM
From: Siva Velusamy <siva.velusamy@xilinx.com>
Date: Mon, 13 Nov 2006 10:48:20 -0800
Links: << >>  << T >>  << A >>
Antti wrote:
> zyan schrieb:
> 
>> Hi,
>>
>> Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working?
>>
>> Thanks.
> 
> same here :(
> all attempts to get MPMC2 DDR2 designs to work have failed so far
> have tested on custom V4 board with single 16bit device and on ML501
> all attempts failing
> 
> I guess the only way to get going is to purchase a eval board that *IS*
> supported by MPMC2 like ml410 and get it working there, and then
> translate that working design to a custom board.
> 
> Antti
> 

Hi Antti,

MPMC2 works fine on ML410 DDR2. You might want to start with those 
settings and then customize for your project.

BTW, MPMC2 does not support Virtex5 as yet, so it will not work on ML501.

/Siva

Article: 111958
Subject: Re: MPMC2: MPMC2 with DDR2 SDRAM
From: "Jim Wu" <jimwu88NOOOSPAM@yahoo.com>
Date: 13 Nov 2006 11:32:36 -0800
Links: << >>  << T >>  << A >>
It works on ML403 and ML405 boards. Sorry I don't have any specific
information on what to look at since I started from the reference
designs. Have you simulated your design?

Cheers,
Jim
http://home.comcast.net/~jimwu88/tools/


zyan wrote:
> Hi,
>
> Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working?
> 
> Thanks.


Article: 111959
Subject: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
From: "Jim Wu" <jimwu88NOOOSPAM@yahoo.com>
Date: 13 Nov 2006 11:39:35 -0800
Links: << >>  << T >>  << A >>
You may want to use a Makefile for this. You can find an example
Makefile for ISE tools here:
http://home.comcast.net/~jimwu88/tools/

HTH,
Jim



uvbaz wrote:
> hi,  everyone,
>
> I want to run
>
> ncvlog
> ncvhdl
> ncelab
> ncsim
> xst
> ngdbuild
> .....
> under Unix.
> I've write a script for this, but with no control statement. How can i
> control the running flow, namely:
>
> if (NCVLOG ERROR) then ERROR REPORT and STOP THE RUNNING....
>
> or
>
> if (XST ERROR) then ERROR REPORT and STOP THE RUNNING....
> 
> Thanks,
> Cheng


Article: 111960
Subject: Re: Xilinx ISE ucf management
From: "Jim Wu" <jimwu88NOOOSPAM@yahoo.com>
Date: 13 Nov 2006 11:45:30 -0800
Links: << >>  << T >>  << A >>
Why don't you have separate ISE project the two boards? The two
projects can use the same source files if that is what your concern is.

HTH,
Jim
http://home.comcast.net/~jimwu88/tools/



Brad Smallridge wrote:
> >  If you're meaning that you want to have it automatically associate
> > with a given UCF file, depending upon what part you select when you
> > begin a *new* project....   as far as I know, no.    Just out of
> > curiousity, what's your application that makes this behavior
> > desireable?  In my experience UCF files tend to be fairly application
> > specific.....   Multiple projects with the same pinout I take it?
>
> I have two development boards on my desk, a Xilinx ml402 and a ml403.
> They are very similar but also have some slight differences in the UCF
> files. When I switch from one board to another I go into the part properties
> and switch fx12 to sx35, remove a ucf file, and add the other ucf file.
>
> Seems like there should be a better way.
>
> So far the UCF files are different in only that the ml403 has some missing
> pins. Later there may be some placement constraints that would also change.
>
> Brad Smallridge
> AiVision
>
>
> >
> > Brad Smallridge wrote:
> >> Is there any way to switch from a ucf file for
> >> an ML402 dev board to a ucf file for a ML403
> >> board without having to delete one file from
> >> the project and copy the source from another
> >> ucf file? Can it automatically know what ucf
> >> file to use based on the FX12 or SX35 part?
> >>
> >> Brad Smallridge
> >> aivision
> >> dot
> >> com
> >


Article: 111961
Subject: Re: Xilinx platform cable USB
From: Sean Durkin <smd@despammed.com>
Date: Mon, 13 Nov 2006 21:41:41 +0100
Links: << >>  << T >>  << A >>
Manny wrote:
> Hi,
> 
> It might be a naive question, however, I just want to make sure. Is
> Xilinx new USB JTAG backward-compatible with old parallel port JTAG
> development boards?
The programming is done via JTAG, which is an IEEE standard. Both the
USB-cable as well as the old parallel cable use JTAG to talk to the
device. So yes, you can use the USB cable for all boards with a JTAG
connector.

But you need to make sure to use a recent version of ISE. iMPACT doesn't
support the USB cable before the 7.1i release, I think.

cu,
Sean

Article: 111962
Subject: NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent
From: "logjam" <grant@stockly.com>
Date: 13 Nov 2006 12:49:50 -0800
Links: << >>  << T >>  << A >>
I just bought the S3EBOARD from Digilent
(http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Products&Nav2=Programmable)
to be my first FPGA board.

For my first project I want to make an ADM3 serial terminal emulator
with telnet over ethernet ability.  It will just be a character based
display with PS/2 keyboard for input and VGA for output, and the serial
port for the terminal in/output.  My plan is to use one of the slide
switches to select VGA or NTSC.  NTSC video would be provided using a
little PCB connected to the VGA connector (just black and white video
from 2 wires).  The switch would just tell the FPGA what timing and
video method to use.

That part is simple.  The other thing I would like to do is use the
ethernet interface to allow external clients to telnet to the serial
terminal.

I have read about using the MicroBlaze core and lwip, so I am reading
about those to try and see if they will help me any.

Any suggestions or hints that would help me with this project?  Any
sample code on 1 bit NTSC (B/W) using two wires and a few resistors?

I think the hard part will be the telnet function.  Hopefully this
board comes with PS/2 and VGA code examples!  Does anyone have this
board know what kind of examples it comes with?


Article: 111963
Subject: Re: Stratix-III announced
From: rickystickyrick@hotmail.com
Date: 13 Nov 2006 13:26:52 -0800
Links: << >>  << T >>  << A >>

> Virtex-5 are pretty much real and available also, for Stratix-3,
> ECP2M the availability is not yet there yet, thats correct.


I've had ECP2M35 samples for 3-4 weeks now.  That is at least
real if not "available".

Ricky.


Article: 111964
Subject: Re: NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent
From: rponsard@gmail.com
Date: 13 Nov 2006 13:30:55 -0800
Links: << >>  << T >>  << A >>
if you want telnet, you need an IP stack, so you need an OS... then try
uClinux and you are done !

see http://muranaka.info for the reference design (or xilinx
xapp730.pdf) and follow guidelines. runs perfectly out of the box
see also http://petalogix.com (same design)

all you need is an EDK tools chain

enjoy

On Nov 13, 9:49 pm, "logjam" <g...@stockly.com> wrote:
> I just bought the S3EBOARD from Digilent
> (http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Pro...)
> to be my first FPGA board.
>
> For my first project I want to make an ADM3 serial terminal emulator
> with telnet over ethernet ability.  It will just be a character based
> display with PS/2 keyboard for input and VGA for output, and the serial
> port for the terminal in/output.  My plan is to use one of the slide
> switches to select VGA or NTSC.  NTSC video would be provided using a
> little PCB connected to the VGA connector (just black and white video
> from 2 wires).  The switch would just tell the FPGA what timing and
> video method to use.
>
> That part is simple.  The other thing I would like to do is use the
> ethernet interface to allow external clients to telnet to the serial
> terminal.
>
> I have read about using the MicroBlaze core and lwip, so I am reading
> about those to try and see if they will help me any.
>
> Any suggestions or hints that would help me with this project?  Any
> sample code on 1 bit NTSC (B/W) using two wires and a few resistors?
>
> I think the hard part will be the telnet function.  Hopefully this
> board comes with PS/2 and VGA code examples!  Does anyone have this
> board know what kind of examples it comes with?


Article: 111965
Subject: Re: opb_ddr
From: "funkrhythm" <funkrhythm@gmail.com>
Date: 13 Nov 2006 14:02:21 -0800
Links: << >>  << T >>  << A >>
i've had problems with opb_ddr under EDK 8.2 as well

i had a design (on the avnet V4FX12 mini module board) using the
opb_ddr which worked under 8.1 and does not work under 8.2.  the
reference designs that avnet provides worked under 8.1 but not under
8.2 (SP1, i haven't tested it with SP2).  i wound up changing my design
to use an MPMC2 memory controller instead.

-rimas

Guru wrote:
> Hi all,
>
> I have problems with runnig a DDR test on Spartan3E SK.
> I rebuild one of the reference designs in EDK 8.2:
> http://www.xilinx.com/products/boards/s3estarter/files/Xil3S500E_Serial_Flash_v81.zip
> I have three boards and 2 do not pass the test.
> I have about the same problems with a Virtex4 MiniModule and the design
> with opb_ddr.
> Did anyone else experienced the same problems?
> 
> Cheers,
> 
> Guru


Article: 111966
Subject: Re: Field Programmable Object Array
From: "Kashmir" <rich@rangii.com>
Date: 13 Nov 2006 14:21:21 -0800
Links: << >>  << T >>  << A >>
MathStar is hosting a webinar tomorrow.  Good opportunity to learn
more:

Tuesday
November 14th
9am PT/Noon ET

 FPOA: The Next Generation of Programmable Logic
MathStar's new Field Programmable Object Array (FPOA) is a 1 GHz,
reprogrammable device offering up to four times the performance of
FPGAs. This presentation shows the advantages of FPOAs and describes
the capabilities of its "silicon objects," which are composed of
arithmetic logic units (ALUs), multiply-accumulators (MACs), and
register files (RFs). It will also show how FPOAs can be used in video
codec applications, and how the FPOA's performance stacks up against
other alternatives. To register for this event go to:
http://onlineevents.cmptechnetwork.com/cgi-bin4/DM/y/n1jc0JPPTr0QeD0ErvW0EZ


Article: 111967
Subject: Re: NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent
From: Mark McDougall <markm@vl.com.au>
Date: Tue, 14 Nov 2006 10:40:33 +1100
Links: << >>  << T >>  << A >>
logjam wrote:

> My plan is to use one of the slide
> switches to select VGA or NTSC.  NTSC video would be provided using a
> little PCB connected to the VGA connector (just black and white video
> from 2 wires).  The switch would just tell the FPGA what timing and
> video method to use.

If you want to simplify your video, take a look at the projects on
fpgaarcade or c-one that use a scan-doubler to convert composite output
to vga. If you connect your resistor dac to gpio on the board rather
than the vga port, you can output both simultaneously.

> Any suggestions or hints that would help me with this project?  Any
> sample code on 1 bit NTSC (B/W) using two wires and a few resistors?

If you google around you'll find a few samples of ntsc/pal out there.
Most of what I've seen relate to games on FPGA...

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 111968
Subject: Re: Need just a few 5V Spartan
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Mon, 13 Nov 2006 18:46:21 -0600
Links: << >>  << T >>  << A >>


Uwe Bonnes wrote:

>Jon Elson <jmelson@artsci.wustl.edu> wrote:
>...
>  
>
>>I'm checking with the seller to see if I can get less quantity than the 
>>whole
>>lot of 220 pieces.
>>    
>>
>
>Buy all and sell the rest on EBAY ;-)
>
>  
>
Well, that's what HE is already doing, so not much point there!
I bought 25, which should get me some time to revise the whole
board for moving to a newer Spartan 2E chip.

Jon


Article: 111969
Subject: Re: Virtex-4 : OCM
From: zyan <czinyan1983@yahoo.com>
Date: Mon, 13 Nov 2006 17:17:16 -0800
Links: << >>  << T >>  << A >>
Thanks. Yes, I have both I-side and D-side OCM. XMD did not complaint that the address was out-of-range. So I supposed that the program can fit to the OCM. Or is there anyway to check is the program fit the OCM?

- Zyan

Article: 111970
Subject: Re: Why 64-bit PLB?
From: Jeff Cunningham <jcc@sover.net>
Date: Mon, 13 Nov 2006 21:28:16 -0500
Links: << >>  << T >>  << A >>
Antti wrote:

> 
> PPC405 hard macro PLB DBUS *IS* 64 bits
> 

But according to the documentation, the native hard PLB interfaces on 
the PPC core can be configured to operate in 32 bit mode, and they will 
adapt themselves to just use 32 bits (i.e. you don't need any external 
64 to 32 bit mux). For instance, see the PLBC405DCUSSIZE1 parameter in 
the Power PC 405 Processor Block Reference Guide.

-Jeff

Article: 111971
Subject: Nested Generate Statement in VHDL
From: Sudhir.Singh@email.com
Date: 13 Nov 2006 19:33:22 -0800
Links: << >>  << T >>  << A >>
Hi All,
I am using a nested generate construct in my VHDL code to conditionally
instantiate a component a number of times.
I have a constant that specifies how many of these components need to
be generated. If it is zero then none should be generated. I am
catching the zero case by having a compare to zero condition in the
outer generate statement.

my code looks like

gen_tx: if N_TX > 0 generate
  gen_tx_inst: for i in 0 to N_TX-1 generate
     tx_inst: tx port map(...);
  end generate gen_tx_inst;
end generate gen_tx;

Now if I set N_TX to zero, Modelsim compiler issues a warning about the
inner generate, saying "Range 0 to -1 is null". I understand that the
inner range would be 0 to -1 if I set N_TX to 0, thats what I have been
trying to catch by having an outer generate.


Can I safely ignore this warning message? Would the synthesis & PAR
tools (Xilinx) misbehave because of this?
Does anyone have a better method of doing this?

Thanks in advance.
Sudhir


Article: 111972
Subject: Re: Nested Generate Statement in VHDL
From: Mark McDougall <markm@vl.com.au>
Date: Tue, 14 Nov 2006 14:57:51 +1100
Links: << >>  << T >>  << A >>
Sudhir.Singh@email.com wrote:

> my code looks like
> 
> gen_tx: if N_TX > 0 generate
>   gen_tx_inst: for i in 0 to N_TX-1 generate
>      tx_inst: tx port map(...);
>   end generate gen_tx_inst;
> end generate gen_tx;
> 
> Now if I set N_TX to zero, Modelsim compiler issues a warning about the
> inner generate, saying "Range 0 to -1 is null". I understand that the
> inner range would be 0 to -1 if I set N_TX to 0, thats what I have been
> trying to catch by having an outer generate.
> 
> Can I safely ignore this warning message? Would the synthesis & PAR
> tools (Xilinx) misbehave because of this?
> Does anyone have a better method of doing this?

My belief is that you can safely ignore the warning. The VHDL compiler
will insist on 'compiling' or at least parsing the innards of a generate
even if the condition fails, which can be quite annoying! I'm sure
there's a good reason - I'm just a big fan of C macros and I wish that
VHDL had the same. Yes, I am aware of pre-processors but it's not really
an option when you're writing code for customers.

It's also very annoying that generate *requires* a label, and that it
doesn't have an 'else'!

I'm not sure you need to even catch the zero case - the inner loop
should suffice!?!

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 111973
Subject: Re: Nested Generate Statement in VHDL
From: Sudhir.Singh@email.com
Date: 13 Nov 2006 20:56:54 -0800
Links: << >>  << T >>  << A >>
Hi Mark,
Thanks for your reply.
Yeah its really annoying that VHDL doesn't have the if & else construct
for generate.

I also find the different syntaxs for if else type selection based on
whether its a concurrent statement or inside a process, quite annoying.

Thanks.
Sudhir

Mark McDougall wrote:
> Sudhir.Singh@email.com wrote:
>
> > my code looks like
> >
> > gen_tx: if N_TX > 0 generate
> >   gen_tx_inst: for i in 0 to N_TX-1 generate
> >      tx_inst: tx port map(...);
> >   end generate gen_tx_inst;
> > end generate gen_tx;
> >
> > Now if I set N_TX to zero, Modelsim compiler issues a warning about the
> > inner generate, saying "Range 0 to -1 is null". I understand that the
> > inner range would be 0 to -1 if I set N_TX to 0, thats what I have been
> > trying to catch by having an outer generate.
> >
> > Can I safely ignore this warning message? Would the synthesis & PAR
> > tools (Xilinx) misbehave because of this?
> > Does anyone have a better method of doing this?
>
> My belief is that you can safely ignore the warning. The VHDL compiler
> will insist on 'compiling' or at least parsing the innards of a generate
> even if the condition fails, which can be quite annoying! I'm sure
> there's a good reason - I'm just a big fan of C macros and I wish that
> VHDL had the same. Yes, I am aware of pre-processors but it's not really
> an option when you're writing code for customers.
>
> It's also very annoying that generate *requires* a label, and that it
> doesn't have an 'else'!
>
> I'm not sure you need to even catch the zero case - the inner loop
> should suffice!?!
>
> Regards,
>
> --
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266


Article: 111974
Subject: Running an application from external memory in Xilinx
From: "Jhlw" <james.h.w@gmail.com>
Date: 13 Nov 2006 21:15:06 -0800
Links: << >>  << T >>  << A >>
Hello All,

I figured out how to run an application from external memory in Xilinx.
I have EDK ver 8.2.01i and an ML403 board.
What you do is "Mark to init BRAMs" on the default bootloop app in
the Applications window pane, update your bitstream and then load
it into the board using iMPACT.
Change your linker script using "Generate Link Script" for your
large application and set the .text section to SRAM. Rebuild your
app.

You also have to set the .boot section (0x00000010) to SRAM.
I was able to follow how to use XMD and GDB by reading the est_rm.pdf,
but I couldn't find this information on how to set up your linker
script in the installed help files that come with the software, or
in the .pdf manuals that also come with the software.

It really seems to me that Xilinx could just mention that in their
manuals and online help rather than make people guess or dig
through examples.

Once I was running in external memory, I found I had to set the
view to "Mixed" (source and assembly) and I could only put the
breakpoints on the assembly code. I'm happy now, but this shouldn't
have been such a guessing game or scavenger hunt.

Look at
Using SDK
file:///C:/EDK/doc/usenglish/help/platform_studio/platform_studio.htm#html/ps_p_app_using_ps_sdk.htm
Look down on left pane for "Running an Application from External
Memory".
All it says is
"The bitstream must first be initialized with a bootloop, and the FPGA
configured
with this information."
Downloading a Design Using XMD:
file:///C:/EDK/doc/usenglish/help/platform_studio/platform_studio.htm#html/ps_p_app_using_ps_sdk.htm
"Use dow <path to executable file> to download the software
executable."
and then they leave you to follow the rest of the documentation on how
to
set up XMD and GDB. You don't even have to do that latter; GDB will
load your
code for you when you click Run.

It really seems to me that they could put in what you need to know, and
leave out what you don't need to do...




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